WO2011055420A1

WO2011055420A1 - Semiconductor device

Info

Publication number: WO2011055420A1
Application number: PCT/JP2009/068802
Authority: WO
Inventors: 高晴辻
Original assignee: ルネサスエレクトロニクス株式会社
Priority date: 2009-11-04
Filing date: 2009-11-04
Publication date: 2011-05-12
Also published as: TW201126533A

Abstract

An MRAM device (semiconductor device) comprises a normal memory cell array (10N) in which normal memory cells (MC) are arranged, and a reference memory cell array (10R) in which reference memory cells (MCR) used as reference resistances at the time of readout are arranged. Digit lines (DLR) for the reference memory cells (MCR) are connected to digit lines (DL) for the normal memory cells (MC) corresponding thereto, and connection points (ND) are connected to a power supply node (VDD) via a power supply line (ISL). A digit line drive circuit (60N) for the normal memory cells (MC) and a digit line drive circuit (60R) for the reference memory cells (MCR) are provided independently of each other. When data is written into the normal memory cell (MC), a write current flows into the digit line drive circuit (60N) from the power supply node (VDD) via the power supply line (ISL) and the digit line (DL) for the normal memory cell (MC).

Description

Semiconductor device

The present invention relates to a semiconductor device in which thin-film magnetic memory elements utilizing the magnetoresistance effect are integrated on a substrate.

A magnetic random access storage device (MRAM) is a storage device using a memory cell as an element (TMR element) having a tunneling magneto-resistive (TMR) effect. Each memory cell of the MRAM device is provided at an intersection of a bit line and a digit line, and data is written by a current magnetic field generated when a current is passed through both the bit line and the digit line.

When writing data, the memory cell in the same row or column as the memory cell to be written is in a state where a current is passed through one of the bit line and the digit line, that is, a half-selected state. In a half-selected memory cell, the amount of current at the time of writing is adjusted so that magnetic data is not inverted, but there is a possibility that erroneous data inversion occurs. Since the reliability as a memory device is impaired when erroneous data inversion occurs due to the disturb magnetic field in such a half-selected state, a technique for suppressing the disturb magnetic field has been developed.

For example, the MRAM device described in Japanese Patent Application Laid-Open No. 2004-192727 (Patent Document 1) includes a current source for supplying a compensation current to the bit line. The compensation magnetic field generated by the compensation current prevents the data stored in the adjacent TMR element from being destroyed when data is written to the TMR element. The current source for generating the compensation magnetic field is composed of the same number of current source units as that of the bit lines, and one current source unit is connected to one bit line.

In the technique disclosed in WO2003 / 052828 (Patent Document 2), a plurality of write word lines (digit lines) are arranged so as to intersect with the plurality of write word lines and correspond to write data. A large number of memory cells are arranged in a checker pattern with respect to a plurality of data lines (bit lines) through which a current flows. As a result, the leakage magnetic field to the memory cell adjacent to the selected cell during writing is reduced, and the influence on the magnetization state of the TMR element is reduced.

JP 2004-192727 A WO2003 / 052828

Incidentally, the MRAM device is provided with a reference memory cell (reference memory cell) for use as a reference resistor at the time of data reading. For example, when generating a reference resistance using two reference memory cells, one of the two reference memory cells is set to a high resistance state, and the other is set to a low resistance state. By averaging the two, an intermediate resistance value is created and used as a reference resistance.

Since the electrical characteristics of the reference memory cell must be substantially the same as the electrical characteristics of a normal memory cell (normal memory cell), the reference memory cell has a continuous element arrangement with respect to a memory array composed of normal memory cells. Arranged to keep sex. In such a case, a normal memory cell and a reference memory cell may be arranged along the same digit line. As a result, at the time of data writing, there is a possibility that the reference memory cell provided corresponding to the digit line common to the normal memory cell to be written is in a deselected state and erroneously inverted. If the reference memory cell is erroneously inverted, the reference resistance is changed, and the MRAM device malfunctions.

An object of the present invention is to provide a semiconductor device including an MRAM device capable of preventing erroneous reversal of a reference memory cell due to a disturb magnetic field in a counter-selected state.

A semiconductor device according to an embodiment of the present invention includes a normal memory cell array, a reference memory cell array, a plurality of first digit lines, a plurality of second digit lines, a first digit line drive circuit, 2 digit line drive circuits. In the normal memory cell array, a plurality of normal memory cells having a magnetoresistive effect element whose electric resistance changes according to magnetic data are arranged in a matrix. The reference memory cell array includes a plurality of reference memory cells that have a magnetoresistive effect element and are used as a reference resistor by writing magnetic data in advance. The plurality of first digit lines correspond to the rows of the normal memory cell array, respectively. Each first digit line is provided along a corresponding row. A terminal portion of each first digit line in the first direction which is one of the row directions of the normal memory cell array is connected to the first power supply node. The plurality of second digit lines individually correspond to at least some of the plurality of first digit lines. Each second digit line extends along a first direction in connection with the end of the corresponding first digit line. Each row of the reference memory cell array individually corresponds to each of the plurality of second digit lines, and is provided along the corresponding second digit line. When writing magnetic data to the normal memory cell array, the first digit line drive circuit is connected to the first power supply node via the first digit line corresponding to the row including the memory cell to be written. Then, a first write current necessary for writing magnetic data is supplied. When the magnetic data is written in the reference memory cell array in advance, the second digit line drive circuit is connected to the first power supply node via the second digit line corresponding to the row including the reference memory cell to be written. A second write current necessary for writing magnetic data is passed between the two.

According to the above embodiment, the first write current that flows when data is written to the normal memory cell array flows through the first digit line corresponding to the row including the normal memory cell to be written. Never flow through the digit line. Therefore, erroneous inversion of the reference memory cell due to the disturb magnetic field at the time of writing can be prevented.

1 is a block diagram schematically showing an example of a configuration of a semiconductor device 1 according to an embodiment of the present invention. It is a block diagram which shows the whole structure of the MRAM apparatus 4 of FIG. FIG. 3 is a circuit diagram schematically showing a configuration of each memory cell MC configuring the memory array 10 of FIG. 2. It is a figure which shows the relationship between a data write current and the magnetization reversal of a free magnetic layer. FIG. 3 is a plan view schematically showing a layout of each part of the MRAM device 4 of FIG. 2. FIG. 6 is a plan view showing details of a sub memory array region 6 in FIG. 5. FIG. 7 is a plan view showing in detail the

memory cell arrays

10N and 10R of FIG. FIG. 8 is a circuit diagram showing configurations of a BL selection circuit 20 and a readout circuit 30 in FIG. 7. FIG. 8 is a circuit diagram showing a configuration of

DL drive circuits

60N and 60R in FIGS. 6 and 7; FIG. 8 is a circuit diagram showing a configuration of

WL drive circuits

50N and 50R in FIGS. 6 and 7; FIG. 3 is a block diagram showing a configuration of a row decoding circuit 40 in FIG. 2. It is a top view which shows the specific example of the layout of each part of basic unit BU0 of FIG. FIG. 13 is a cross-sectional view taken along a cutting line XIII-XIII in FIG. FIG. 14 is a cross-sectional view taken along a cutting line XIV-XIV in FIG. 12. FIG. 10 is a plan view illustrating an example of a configuration of a MOS transistor 61 in FIG. 9. FIG. 10 is a plan view illustrating an example of a configuration of a MOS transistor 65 in FIG. 9.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

[Configuration of semiconductor device]
FIG. 1 is a block diagram schematically showing an example of the configuration of a semiconductor device 1 according to an embodiment of the present invention.

Referring to FIG. 1, a semiconductor device 1 is a microcomputer including a CPU (Central Processing Unit) and a memory controller 2, a clock generation circuit 3, and an MRAM device 4. The microcomputer of FIG. 1 is shown as an example of an integrated circuit on which the MRAM device 4 is mounted. Conventionally, many kinds of memories such as flash memory and DRAM (Dynamic Random Access Memory) are mixedly mounted in microcomputers for memories such as ROM (Read Only Memory) and RAM. Taking advantage of the features of MRAM, such as high speed, low power consumption, non-volatility, and unlimited rewrites, in the semiconductor device 1, these various types of memory devices are replaced with MRAM. As shown in FIG. 1, the MRAM device 4 receives a command and an address signal from the CPU and the memory controller 2 and receives a clock from the clock generation circuit 3. The MRAM device 4 writes and reads data based on commands and address signals received from the CPU and the memory controller 2, and exchanges data signals with the CPU and the memory controller 2.

[Overall configuration of MARM device]
FIG. 2 is a block diagram showing the overall configuration of the MRAM device 4 of FIG.

Referring to FIG. 2, MRAM device 4 performs random access to memory array 10 in response to command CMD, clock CLK and address signal ADD, thereby writing write data Din and reading read data Dout. And do. MRAM device 4 includes a control circuit 140, a memory array 10, and an input / output circuit 150 for inputting / outputting address signal ADD, write data Din, and read data Dout.

The control circuit 140 controls the overall operation of the MRAM device 4 in response to the command CMD and the clock CLK.

The memory array 10 includes a plurality of normal memory cells MC (normal memory cell array 10N) and a plurality of reference memory cells MCR (reference memory cell array 10R) arranged in a matrix, as will be described with reference to FIGS. . The normal memory cell MC is a memory cell for normal data storage. The reference memory cell MCR is provided as a reference resistance when reading magnetic data stored in the normal memory cell MC, and generates a reference value for data determination of the normal memory cell MC. Each memory cell MC, MCR includes a TMR element and an access transistor ATR.

A plurality of word lines WL, digit lines DL, and bit lines BL are arranged in memory array 10 in order to perform data reading and data writing to normal memory cells MC. Word lines WL and digit lines DL are arranged in the row direction corresponding to the memory cell rows, and bit lines BL are arranged in the column direction corresponding to the memory cell columns. As will be described with reference to FIG. 7, a plurality of word lines WLR, digit lines DLR, and bit lines BLR are also provided for a plurality of reference memory cells MCR.

Input / output circuit 150 includes an address signal latch circuit 153, a write data latch circuit 151, and a read data latch circuit 152 that temporarily hold address signal ADD, write data Din, and read data Dout, respectively. .

The MRAM device 4 further includes a bit line (BL) selection circuit 20, a read circuit 30, a row decode circuit 40, a word line (WL) drive circuit 50, a digit line (DL) drive circuit 60, a column decode circuit 70, and a bit. A line (BL) drive circuit 80 is included.

The BL selection circuit 20 selects a bit line BL corresponding to a normal memory cell MC to be read and a bit line BLR corresponding to a reference memory cell MCR used as a reference resistance at the time of data reading.

The read circuit 30 detects and amplifies the difference between the passing current of the normal memory cell MC selected at the time of data reading and the passing current of the reference memory cell MCR. Read circuit 30 outputs the detected and amplified signal to read data latch circuit 152.

The row decode circuit 40 receives the address signal ADD from the address signal latch circuit 153 and decodes the row address signal RA indicated by the address signal ADD. The row decoding circuit 40 outputs a row selection signal as a decoding result in response to the command CMD and the clock CLK from the control circuit 140. The row selection signal is used for performing row selection of the memory array 10.

The WL drive circuit 50 receives the row selection signal from the row decoding circuit 40 and activates the corresponding word lines WL and WLR when reading data from the normal memory cell MC.

The DL drive circuit 60 receives a row selection signal from the row decode circuit 40 and writes a data write current to the corresponding digit line DL or DLR during data writing.

The column decode circuit 70 receives the address signal ADD supplied from the address signal latch circuit 153 and decodes the column address signal CA indicated by the address signal ADD. The column decode circuit 70 outputs a column selection signal as a decoding result in accordance with the command CMD and the clock CLK supplied from the control circuit 140. The column selection signal is used for performing column selection in the memory array 10.

The BL drive circuit 80 receives a column selection signal from the column decode circuit 70, and writes data to the corresponding bit line BL or BLR in the direction corresponding to the write data Din from the write data latch circuit 151 at the time of data writing. Apply data write current.

The MRAM device 4 further supplies various reference voltages to be supplied to the read circuit 30, the row decode circuit 40, the word line drive circuit 50, the digit line drive circuit 60, the column decode circuit 70, the bit line drive circuit 80, and the like. A reference power supply 160 to be generated is included.

[Configuration and operation of memory cell]
FIG. 3 is a circuit diagram schematically showing the configuration of each memory cell MC, MCR constituting the memory array 10 of FIG. Since the configuration of the normal memory cell MC and the configuration of the reference memory cell MCR are the same, the normal memory cell MC will be described below as a representative.

Referring to FIG. 3, memory cell MC includes a TMR element whose electrical resistance changes according to magnetic data, and an access transistor ATR. Here, the TMR element is a magnetoresistive element having a tunnel junction structure in which a thin insulating layer is sandwiched between a fixed magnetic layer and a free magnetic layer made of a ferromagnetic thin film. The TMR element is in a low resistance state when the magnetization directions of the two layers are parallel, and is in a high resistance state when the magnetization directions are antiparallel, and stores information of “1” and “0” depending on the magnetization direction of the free magnetic layer. be able to. Normally, a MOS (Metal Oxide Semiconductor) transistor is used as the access transistor ATR.

Digit line DL, word line WL, bit line BL, and source line SL are arranged for memory cell MC. Digit lines DL and word lines WL extend in the row direction of the memory cell array, and bit lines BL extend in the column direction. The source line SL extends in the column direction in the case of the normal memory cell MC, and extends in the row direction in the case of the reference memory cell MCR.

In this specification, the row direction is also referred to as the X direction, and the column direction is also referred to as the Y direction. When distinguishing the direction along the X direction, it is distinguished by attaching a sign such as + X direction or -X direction. The same applies to the Y direction.

As shown in FIG. 3, the TMR element has one end connected to the bit line BL and the other end connected to the drain of the access transistor ATR. The source of access transistor ATR is connected to ground node GND through source line SL. The gate of the access transistor ATR is connected to the word line WL.

At the time of data writing, a digit line DL of a memory cell row (hereinafter also referred to as a selected row) corresponding to a selected memory cell to be data-written and a memory cell column (hereinafter referred to as a selected column) corresponding to the selected memory cell The data write currents IDL and IBL are supplied to the bit line BL. Here, the direction of the current IBL flowing through the bit line BL can be switched according to the write data. The direction of magnetization of the free magnetic layer is determined by the direction of the current IBL flowing through the bit line BL.

On the other hand, at the time of data reading, the word line WL corresponding to the selected memory cell is activated to a high voltage state, and the access transistor ATR becomes conductive. As a result, a sense current (cell current) flows from the bit line BL to the source line SL through the TMR element and the access transistor ATR. In the following, the binary high voltage state and low voltage state such as signals, signal lines, and data are also referred to as “H level” and “L level”, respectively.

The above-described source line SL, bit line BL, and digit line DL are formed using a metal wiring layer. On the other hand, the word line WL is integrated with the gate of the access transistor ATR in order to increase the degree of integration and simplify the manufacturing process. Therefore, the word line WL is formed using polysilicon, polycide, or the like.

FIG. 4 is a diagram showing the relationship between the data write current and the magnetization reversal of the free magnetic layer. Referring to FIG. 4, the horizontal axis shows the bit line current IBL flowing through the bit line BL. On the vertical axis, the digit line current IDL flowing through the digit line DL is shown. At the time of data writing, a combined magnetic field of a current magnetic field by the bit line current IBL and a current magnetic field by the digit line current IDL is applied to the TMR element. For example, as shown in FIG. 4, when a current I1 flows as the bit line current IBL and a current I2 flows as the digit line current IDL, a point I3 where the currents I1 and I2 intersect is shown. Is a region outside the asteroid curve, the magnetization direction of the free magnetic layer of the TMR element changes. When the intersection I3 is an area inside the asteroid curve, the data of the TMR element is not updated.

Therefore, in the state where only the bit line current I1 or the digit line current I2 flows (deselected state), the inversion of magnetic data should not occur. However, in actuality, erroneous reversal occurs with a certain probability. The probability of erroneous inversion increases in proportion to the magnitude of the disturb magnetic field received by the TMR element. That is, as the disturb margin amount ΔIBL of the bit line current shown in FIG. 4 decreases or the disturb margin amount ΔIDL of the digit line current decreases, the erroneous inversion probability of the TMR element increases. If the reference memory cell is erroneously inverted due to the disturb magnetic field in the half-selected state, the MRAM device malfunctions, so that the disturb magnetic field needs to be suppressed as much as possible.

[Outline of Layout of Each Part of MRAM Device]
FIG. 5 is a plan view schematically showing the layout of each part of the MRAM device 4 of FIG. 2 and 5,

memory array regions

5A and 5B in which memory array 10 and drive circuits 50, 60 and 80 are provided are arranged side by side in the X direction on substrate SUB. Each

memory array area

5A, 5B is further divided into sub memory array areas 6 of 4 rows and 2 columns.

The row decode circuit 40 is arranged between the

memory array areas

5A and 5B. A plurality of main word lines MWL are arranged from the row decode circuit 40 in the + X direction and the −X direction. The main word line MWL is provided for transmitting a row selection signal from the row decode circuit 40 to the WL drive circuit 50 and the DL drive circuit 60.

Column decode circuits

70A and 70B are arranged in areas adjacent to the −Y direction of the

memory array areas

5A and 5B, respectively. Control circuit 140 and input / output circuit 150 are arranged in a region adjacent to the region where column decode

circuits

70A and 70B are provided in the −Y direction.

FIG. 6 is a plan view showing details of the sub memory array region 6 of FIG.
Referring to FIG. 6, normal memory cell array 10N is provided near the center of sub memory array region 6. Word lines WL and digit lines DL are provided along the row direction of normal memory cell array 10N, and bit lines BL are provided along the column direction. Each memory cell MC is arranged in the vicinity of an intersection between the word line WL (digit line DL) and the bit line BL.

The reference memory cell array 10R is provided in a region adjacent to the region in which the normal memory cell array 10N is provided in the + X direction. A word line WLR and a digit line DLR are provided along the row direction of the reference memory cell array 10R, and bit lines BLR0 and BLR1 are provided along the column direction. Digit line DLR is connected to corresponding digit line DL for normal memory cell array 10N. A connection point ND between the two digit lines DL and DLR is connected to a power supply node VDD via a power supply line ISL.

In FIG. 6, two reference memory cells MCR are provided for each digit line DLR (word line WLR). At the time of factory shipment, for example, one of the two reference memory cells MCR is preliminarily written with magnetic data so that the fixed magnetic layer and the free magnetic layer are antiparallel (that is, in a high resistance state), and the other is Magnetic data is written in advance so that the fixed magnetic layer and the free magnetic layer are parallel (that is, in a low resistance state).

The DL drive circuit 60N for the normal memory cell MC and the DL drive circuit 60R for the reference memory cell MCR are provided independently of each other. The DL drive circuit 60N for the normal memory cell MC is arranged in a region adjacent to the region in which the normal memory cell array 10N is provided in the −X direction.

In the conventional MRAM device, the power supply node VDD is connected to the terminal portion in the + X direction of the digit line DLR for the reference memory cell MCR, and the DL drive circuit 60R for the reference memory cell MCR is not provided. In this case, when magnetic data is previously written in the reference memory cell MCR at the time of factory shipment, a write current is passed through the digit line DLR using the DL drive circuit 60N for the normal memory cell MC. However, in such a configuration, a write current flows through the digit line DLR for the reference memory cell MCR even when data is written to the normal memory cell MC. The disturb magnetic field is applied to the cell MCR, and the reference memory cell MCR may be erroneously inverted by the disturb magnetic field.

In the MRAM device 4 of this embodiment, when data is written to the normal memory cell MC, a write current flows from the power supply node VDD to the DL drive circuit 60N through the power supply wiring ISL and the digit line DL. In this case, since the write current does not flow through the digit line DLR for the reference memory cell MCR, the reference memory cell MCR can be prevented from being affected by the disturb magnetic field during the write access to the normal memory cell MC. However, in the case of the MRAM device 4, the DL drive circuit 60R for the reference memory cell MCR is separated from the DL drive circuit 60N for the normal memory cell MC in order to be used when magnetic data is written in the reference memory cell MCR in advance. It is necessary to provide it. As described in detail in FIG. 7, the MRAM device 4 is configured such that the number of rows in the reference memory cell array 10R is smaller than the number of rows in the normal memory cell array 10N. Thereby, an empty space is created in the installation area of the reference memory cell array 10R, and the DL drive circuit 60R is arranged in this empty space.

When the number of rows of the reference memory cell array 10R is smaller than the number of rows of the normal memory cell array 10N, the WL drive circuit 50N for the normal memory cell MC and the WL drive circuit 60R for the reference memory cell MCR are also provided independently of each other. There is a need. The WL drive circuit 50N for the normal memory cell MC is provided in a region adjacent to the region in which the DL drive circuit 60N is provided in the −X direction. The WL drive circuit 50R for the reference memory cell MCR is provided in an empty space in the area where the reference memory cell array 10R is provided.

The

BL drive circuits

80A and 80B are arranged in a region adjacent to the + Y direction and a region adjacent to the −Y direction, respectively, with respect to the region where the

memory cell arrays

10N and 10R are provided. The bit line currents in both the + Y direction and the −Y direction are generated by the

BL drive circuits

80A and 80B. The BL selection circuit 20 and the readout circuit 30 are arranged in an area adjacent to the area where the BL drive circuit 80A is provided in the + Y direction.

[Details of memory cell array configuration]
FIG. 7 is a plan view showing in detail the

memory cell arrays

10N and 10R of FIG. Referring to FIG. 7, normal memory cell array 10N includes normal memory cells MC in m rows and n columns (n is an integer of 2 or more and m is a multiple of 4). In the following description, the memory cells in the first row and the first column are described as MC <0,0>, and the memory cells MC in the kth row and the lth column (1 ≦ k ≦ m, 1 ≦ l ≦ n) are described. It is described as MC <k-1, l-1>.

M digit lines DL0 to DLm-1 are provided corresponding to the first to mth rows of the normal memory cell array 10N, respectively. The end portions in the −X direction of digit lines DL0 to DLm−1 are connected to DL drive circuit 60N, and the end portions in the + X direction of digit lines DL0 to DLm−1 are connected to power supply line ISL. Power supply line ISL is provided extending in the column direction, and an end in the + Y direction is connected to power supply node VDD. When data is written to normal memory cell MC, write current IDL flows from power supply node VDD to DL drive circuit 60N through power supply line ISL and selected digit line DL. Therefore, since the write current IDL does not flow through the digit lines DLR0 to DLRp-1 for the reference memory cell MCR, erroneous reversal of the reference memory cell MCR due to the disturb magnetic field can be prevented.

Although not shown in FIG. 7, m word lines WL0 to WLm−1 are also provided corresponding to the rows of the normal memory cell array 10N, respectively. Termination portions in the −X direction of the word lines WL0 to WLm−1 are connected to the WL drive circuit 50N.

N bit lines BL0 to BLn−1 are provided corresponding to the first to nth columns of the normal memory cell array 10N, respectively. -Y direction end portions of the bit lines BL0 to BLn-1 are connected to the BL drive circuit 80B, and + Y direction end portions of the bit lines BL0 to BLn-1 are connected to the BL drive circuit 80A and the BL selection circuit 20. .

On the other hand, the reference memory cell array 10R is provided for every four rows of the regular memory cell array 10N. That is, when m = 4p, the reference memory cell array 10R is configured by p rows and 2 columns of reference memory cells MCR.

The reference memory cells MCR <0,0> and MCR <0,1> in the first row are normal memory cells MC <0,0> to MC <0, n−1 in the first row of the normal memory cell array 10N. > (Corresponding to digit line DL0) is provided on an extension line in the row direction. Reference memory cells MCR <0,0> and MCR <0,1> are used as reference resistors when data is read from the first row to the fourth row of normal memory cell array 10N.

Similarly, the reference memory cells MCR <i−1,0> and MCR <i−1,1> in the i-th row (1 ≦ i ≦ p) are the memories in the 4i-3th row of the normal memory cell array 10N. Cells MC <4i-4,0> to MC <4i-4, n-1> (corresponding to digit line DL4i-4) are provided on extension lines in the row direction. The reference memory cells MCR <i−1,0> and MCR <i−1,1> are used as reference resistors when data is read from the 4i-3rd row to the 4ith row of the normal memory cell array 10N.

A dummy cell DC is provided in a region where the reference memory cell MCR is not provided on the extension line in the + X direction of each row of the normal memory cell array 10N in order to suppress shape non-uniformity in the manufacturing process of the semiconductor device. The dummy cell DC includes a shape dummy TMR element but does not include an access transistor. Therefore, the vicinity of the substrate surface in the area where the dummy cell DC is provided becomes an empty space, and the DL drive circuit 60R and the WL drive circuit 50R for the reference memory cell MCR are provided using this space. Although not shown in FIG. 7, the dummy cells DC are also provided in the upper layer of the power supply wiring ISL and around the

memory cell arrays

10N and 10R.

As described above, the reference memory cell MCR is arranged while maintaining the continuity of the element arrangement with the normal memory cell MC, and is used as a reference resistance when data is read from the normal memory cell MC provided in the vicinity. As a result, the electrical characteristics of the reference memory cell MCR can be made substantially the same as the electrical characteristics of the corresponding normal memory cell MC.

For the reference memory cell array 10R configured as described above, p digit lines DLR0 to DLRp-1 are provided corresponding to the first to pth rows of the reference memory cell array 10R, respectively. That is, one digit line DLR is provided for every four digit lines DL0 to DLm−1 for normal memory cells MC. The digit line DLRi-1 in the i-th row (1 ≦ i ≦ p) for the reference memory cell MCR is an extension wiring of the digit line DL4i-4 in the 4i-3th row for the normal memory cell MC in the + X direction. It arrange | positions so that a termination | terminus part may be connected. The −X direction terminations of digit lines DLR0 to DLRp−1 are connected to power supply node VDD via power supply line ISL. The terminal portions in the + X direction of digit lines DLR0 to DLRp-1 are connected to DL drive circuit 60R described in FIG.

However, the digit lines DLR for the reference memory cells MCR and the corresponding digit lines DL for the normal memory cells MC do not necessarily have to be formed continuously. Each digit line DLR is arranged on the extension of the corresponding digit line DL, and a slit is formed between the contact between each digit line DLR and the power supply line ISL and between the corresponding digit line DL and the power supply line ISL. It is also possible to form it.

The DL drive circuit 60R includes p DL driver units DLRDU0 to DLRDUp-1 corresponding to the digit lines DLR0 to DLRp-1, respectively. Each DL driver unit DLRDU supplies a data write current IDLR from the power supply node VDD to the selected digit line DLR via the power supply line ISL when data is written to the reference memory cell MCR. Since power supply line ISL is used in common with the case where data is written to normal memory cell MC, the layout area can be reduced. Each DL driver unit DLRDU is provided in a region adjacent to the region in which the corresponding digit line DLR is provided in the + Y direction. In other words, it is provided in the dummy cell region of the reference memory cell array 10R. Since this area is an empty space in which the reference memory cell MCR is not provided, the DL drive circuit 60R can be provided without an area penalty.

Although not shown in FIG. 7, p word lines WLR0 to WLRp-1 are also provided corresponding to the rows of the reference memory cell array 10R, respectively. Termination portions in the + X direction of the word lines WLR0 to WLRp-1 are connected to the WL drive circuit 50R described with reference to FIG. WL drive circuit 50R includes p WL driver units WLRDU0 to WLRDUp-1 corresponding to word lines WLR0 to WLRp-1, respectively. Each WL driver unit WLRDU is also provided in a region adjacent to the region in which the corresponding word line WLR (digit line DLR) is provided in the + Y direction, that is, in a dummy cell region of the reference memory cell array 10R.

Bit lines BLR0 and BLR1 are provided corresponding to the first column and the second column of the reference memory cell array 10R, respectively. The −Y direction end portions of the bit lines BLR0 and BLR1 are connected to the BL drive circuit 80B, and the + Y direction end portions are connected to the BL drive circuit 80A and the BL selection circuit 20.

One main word line MWL0 to MWLp-1 is provided for every four rows of the normal memory cell array 10N. At the time of data reading and data writing, a row selection signal is transmitted from the row decode circuit 40 to the

WL drive circuits

50N and 50R and the

DL drive circuits

60N and 60R by the main word lines MWL0 to MWLp-1.

By four rows of normal memory cells MC and one row of reference memory cells MCR corresponding to each main word line, and digit lines, word lines, DL driver portions, and WL driver portions corresponding to these memory cells MC and MCR, Basic units BU0 to BUp-1 shown in FIG. 7 are configured.

[Configuration of BL selection circuit and readout circuit]
FIG. 8 is a circuit diagram showing a configuration of BL selection circuit 20 and readout circuit 30 in FIG.

Referring to FIG. 8, BL selection circuit 20 includes an NMOS (N-channel Metal Oxide Semiconductor) transistor individually connected to each of bit lines BL0 to BLn-1, BLR0, and BLR1. FIG. 8 shows

NMOS transistors

21 and 22 connected to the bit lines BL0 and BL1 for the normal memory cell MC, and

NMOS transistors

23 and 24 connected to the bit lines BLR0 and BLR1 for the reference memory cell MCR, respectively. Is shown. The

NMOS transistors

21 and 22 are turned on in response to the column selection signal CSL output from the column decoding circuit 70 of FIG. 2, thereby selecting the bit lines BL0 and BL1. The

NMOS transistors

23 and 24 are turned on by the column selection signal CSL_REF output from the column decoding circuit 70, and thereby the bit lines BLR0 and BLR1 are selected.

Read circuit 30 includes sense amplifiers SA0 and SA1 and internal data read lines LIO0 and LIO1. First input terminals (non-inverting input terminals) of sense amplifiers SA0 and SA1 are connected to internal data read lines LIO0 and LIO1, respectively. The odd-numbered bit lines BL0, BL2,... Are connected to the internal data read line LIO0 via corresponding NMOS transistors. Bit lines BL1, BL3,... Of even-numbered rows are connected to internal data read line LIO1 through corresponding NMOS transistors. The bit line BLR0 for the reference memory cell MCR is connected to the second input terminal (inverted input terminal) of the sense amplifier SA0 via the NMOS transistor 23. A bit line BLR1 for the reference memory cell MCR is connected to the second input terminal (inverted input terminal) of the sense amplifier SA1 through the NMOS transistor 24. The second input terminals of the sense amplifiers SA0 and SA1 are connected to each other via the wiring 31.

Next, a method for reading data from the normal memory cell MC will be described with reference to FIGS. Hereinafter, a case where data is read from memory cells MC <0,0>, MC <0,1> connected to word line WL0 will be described.

First, the WL drive circuit 50N of FIG. 7 activates the word line WL0 (not shown in FIG. 7) of FIG. Subsequently, the BL selection circuit 20 shown in FIGS. 7 and 8 connects the selected bit lines BL0 and BL1 to the internal data read lines LIO0 and LIO1, respectively. At this time, cell currents IC0 and IC1 flow through internal data read lines LIO0 and LIO1, respectively.

On the other hand, the WL driver unit WLRDU0 of FIG. 7 activates the word line WLR0 (not shown in FIG. 7) of FIG. Subsequently, the BL selection circuit 20 shown in FIGS. 7 and 8 connects the selected bit lines BLR0 and BLR1 to the second input terminals of the sense amplifiers SA0 and SA1, respectively. For example, it is assumed that the reference memory cell MCR <0,0> stores data “1” in advance, and the reference memory cell MCR <0,1> stores data “0” in advance. In this case, the cell current ICR0 corresponding to the data “1” flows through the reference memory cell MCR <0,0>, and the cell current ICR1 corresponding to the data “0” flows through the reference memory cell MCR <0,1>. . Here, since the second input terminals of the sense amplifiers SA0 and SA1 are connected to each other, an accurate intermediate between the cell current ICR0 and the cell current ICR1 is provided as a reference current to the second input terminals of the sense amplifiers SA0 and SA1. A current, that is, a current having a magnitude of 1/2 (ICR0 + ICR1) flows.

The sense amplifier SA0 (SA1) compares the cell current IC0 (IC1) of the normal memory cell MC <0,0> (MC <0,1>) with this reference current, so that the logic level is H level or L level. Data Dout0 (Dout1) is output [Configuration of Digit Line Drive Circuit]
FIG. 9 is a circuit diagram showing the configuration of the

DL drive circuits

60N and 60R of FIGS. FIG. 9 shows

DL drive circuits

60N and 60R corresponding to the basic units BU0 and BU1 of FIG.

DL drive circuit 60N for normal memory cell MC includes DL driver units DLDU0 to DLDUm-1 corresponding to digit lines DL0 to DLm-1, respectively, and a current source 64 provided for adjusting the write current amount. . As shown in FIG. 9, DL driver units DLDU0 to DLDU3 correspond to the basic unit BU0. Similarly, DL driver units DLDU4i-4 to DLDU4i-1 correspond to basic unit BUi-1 (1 ≦ i ≦ p). The current source 64 is configured by, for example, an NMOS transistor in which a control voltage is applied to the gate electrode.

Each DL driver unit DLDU includes an NMOS transistor 61, an inverter 62, and a NAND circuit 63. NMOS transistor 61 has its drain connected to corresponding digit line DL and its source connected to ground node GND via current source 64. The inverter 62 and the NAND circuit 63 connected in series function as a gate drive unit 69N that drives the gate of the NMOS transistor 61.

Corresponding main word lines MWL are commonly connected to the first input nodes of the four NAND circuits 63 corresponding to each basic unit BU. As a result, the main word signal MWS as a row selection signal is input to the first input node via the corresponding main word line MWL. Subdecode signals SDW <0> to SDW <3> as row selection signals are individually input to the second input nodes of the four NAND circuits 63. When the input main word signal MWS and subdecode signal SDW are both at the H level, the NMOS transistor 61 of each DL driver unit DLDU becomes conductive. As a result, the write current IDL flows through the digit line DL corresponding to each DL driver unit DLDU. By using main word signals MWS <0> to MWS <p-1> and subdecode signals SDW <0> to SDW <3>, the number of signal lines required to select digit line DL is reduced. Can do.

Next, the DL drive circuit 60R for the reference memory cell MCR includes DL driver units DLRDU0 to DLRDUup-1 connected to the digit lines DLR0 to DLRp-1, respectively, and a current source provided for adjusting the write current amount. 68. As shown in FIG. 9, the DL driver unit DLRDU0 corresponds to the basic unit BU0. Similarly, the DL driver unit DLRDUi-1 corresponds to the basic unit BUi-1 (1 ≦ i ≦ p). The current source 68 is configured by, for example, an NMOS transistor in which a control voltage is applied to the gate electrode.

Each DL driver unit DLRDU includes an NMOS transistor 65, an inverter 66, and a NAND circuit 67. NMOS transistor 65 has a drain connected to corresponding digit line DLR and a source connected to ground node GND via current source 68. The inverter 66 and the NAND circuit 67 connected in series function as a gate drive unit 69R that drives the gate of the NMOS transistor 65.

The corresponding main word line MWL is connected to the first input node of the NAND circuit 67 corresponding to each basic unit BU. As a result, the main word signal MWS is input to the first input node via the corresponding main word line MWL. A write enable signal REF_WE for the reference memory cell is commonly input to the second input node of each NAND circuit 67. Therefore, when both the input main word signal MWS and write enable signal REF_WE are at the H level, the NMOS transistor 65 of each DL driver unit DLRDU becomes conductive. As a result, the write current IDLR flows through the digit line DLR corresponding to each DL driver unit DLRDU. Thus, the digit line DLR for the reference memory cell MCR is selected by the main word signals MWS <0> to MWS <p−1> when the write enable signal REF_WE is at the H level.

[Configuration of word line drive circuit]
FIG. 10 is a circuit diagram showing the configuration of the

WL drive circuits

50N and 50R shown in FIGS. FIG. 10 shows

WL drive circuits

50N and 50R corresponding to the basic units BU0 and BU1 in FIG.

WL drive circuit 50N for normal memory cell MC includes WL driver units WLDU0 to WLDUm-1 corresponding to word lines WL0 to WLm-1. As shown in FIG. 10, the WL unit WLDU0 to WLDU3 corresponds to the basic unit BU0. Similarly, the WL unit WLDU4i-4 to WLDU4i-1 corresponds to the basic unit BUi-1 (1 ≦ i ≦ p).

Each WL driver unit WLDU includes an inverter 51 and a NAND circuit 52 connected in series. The output node of each inverter 51 is connected to the corresponding word line WL. Corresponding main word lines MWL are commonly connected to first input nodes of the four NAND circuits 52 corresponding to the basic units BU0 to BUp-1. As a result, the main word signal MWS is input to the first input node via the corresponding main word line MWL. Sub-decode signals SDR <0> to SDR <3> are individually input to the second input nodes of the four NAND circuits 52. When input main word signal MWS and sub-decode signal SDR are both at H level, word line WL corresponding to each WL driver unit WLDU is activated (H level). Signals necessary for selecting word line WL for normal memory cell MC by using main word signals MWS <0> to MWS <p-1> and sub-decode signals SDR <0> to SDR <3> The number of lines can be reduced.

Next, the WL drive circuit 50R for the reference memory cell MCR includes WL driver units WLRDU0 to WLRDUp-1 corresponding to the word lines WLR0 to WLRp-1, respectively. As shown in FIG. 10, the WL driver unit WLRDU0 corresponds to the basic unit BU0. Similarly, the WL driver unit WLRDUi-1 corresponds to the basic unit BUi-1 (1 ≦ i ≦ p).

Each WL driver unit WLRDU includes an inverter 53 and a NAND circuit 54 connected in series. The output node of inverter 53 is connected to the corresponding word line WLR. A first input node of each NAND circuit 54 is connected to a corresponding main word line MWL. As a result, the main word signal MWS is input to the first input node via the corresponding main word line MWL. A read permission signal REF_RE for the reference memory cell is commonly input to the second input node of each NAND circuit 54. Therefore, when input main word signal MWS and read permission signal REF_RE are both at the H level, word line WLR corresponding to each WL driver unit WLRDU is activated (H level). In this way, the word line WLR for the reference memory cell MCR is selected by the main word signals MWS <0> to MWS <p−1> when the read permission signal REF_RE is at the H level.

[Configuration of row decode circuit]
FIG. 11 is a block diagram showing a configuration of the row decoding circuit 40 of FIG. Referring to FIG. 11, row decode circuit 40 includes

address decoders

41, 42, 44, a test mode decode circuit 43, and a waveform shaping buffer 45.

When the address decoder 41 receives the upper bits of the row address signal from the outside of the MRAM device 4, the address decoder 41 generates p-bit main word signals MWS <0> to MWS <p as row selection signals based on the upper bits of the row address signal. -1> is generated. The generated main word signals MWS <0> to MWS <p-1> are output to the main word lines MWL0 to MWLp-1, respectively.

When the address decoder 42 receives the low-order bit of the row address signal and the write command from the outside of the MRAM device 4, the address decoder 42 generates a 4-bit subdecode signal SDW <0> as a row selection signal based on the low-order bit of the row address signal. Generate SDW <3>. The generated subdecode signals SDW <0> to SDW <3> are output to the corresponding DL driver unit DLDU described in FIG.

The test mode decode circuit 43 generates the write enable signal REF_WE when receiving the upper bits of the row address signal and the test mode entry signal from the outside of the MRAM device 4. The generated write enable signal REF_WE is output to each DL driver unit DLRDU for the reference memory cell MCR described in FIG.

When the address decoder 44 receives the lower bits of the row address signal and the read command from the outside of the MRAM device 4, the address decoder 44 uses a 4-bit sub-decode signal SDR <0> as a row selection signal based on the lower bits of the row address signal. ~ SDR <3> is generated. The generated subdecode signals SDR <0> to SDR <3> are output to the corresponding WL driver unit WLDU described in FIG.

When receiving a read command, the buffer 45 outputs a read permission signal REF_RE to each WL driver unit WLRDU for the reference memory cell MCR described with reference to FIG.

[Specific Example of Layout of Each Part of MRAM Device]
FIG. 12 is a plan view showing a specific example of the layout of each part of the basic unit BU0 of FIG. FIG. 12 shows bit lines BL0 to BLn-1, BLR0 and BLR1 formed in the uppermost fourth metal wiring layer, digit lines DL0 to DL3 and DLR0 formed in the third metal wiring layer, The power supply wiring ISL and the arrangement of the driver units DLDU0 to DLDU3, WLDU0 to WLDU3, DLRDU0, and WLRDU0 are shown.

As shown in FIG. 12, the digit line DL0 for the normal memory cell MC and the digit line DLR0 for the reference memory cell MCR are integrally formed. The integrally formed digit lines DL0 and DLR0 are connected to the DL driver portions DLDU0 and DLRDU0 at both ends via the contact CT, and to the power supply wiring ISL via the contact CT. Each of the digit lines DL1 to DL3 is connected to the corresponding DL driver unit DLDU through the contact CT at the terminal end in the −Y direction, and connected to the power supply line ISL through the contact CT at the terminal end in the + Y direction.

FIG. 13 is a cross-sectional view taken along section line XIII-XIII in FIG. FIG. 13 shows the cross-sectional structure of the reference memory cell MCR and the arrangement of the DL driver unit DLRDU for the reference memory cell MCR. The MRAM device 4 uses a total of four metal wiring layers. The first to fourth metal wiring layers M1 to M4 are stacked in this order from the substrate side via an interlayer insulating film.

As shown in FIG. 13, an access transistor ATR is formed on the main surface of the p-type semiconductor substrate SUB. Access transistor ATR has a source region 111 and a drain region 112 which are n-type regions, and a gate. The gate is formed integrally with the word line WLR. Source region 111 of access transistor ATR is connected to source line SLR formed using first metal interconnection layer M1 via metal layer 113 (referred to as contact 113) formed in the contact hole. .

The main word line MWL is formed using the second metal wiring layer M3. A digit line DLR is formed in the third metal wiring layer M3, which is an upper layer.

The TMR element is formed above the digit line DLR. The TMR element includes a magnetic layer (fixed magnetization layer) PL having a fixed magnetization direction, a magnetic layer (free magnetization layer) FL that is magnetized in a direction according to a data write magnetic field generated by a data write current, Have A tunnel barrier ISO formed of an insulator film is formed between the fixed magnetic layer PL and the free magnetic layer FL.

The TMR element is connected to the drain region 112 of the access transistor ATR via the contact 114 and the barrier metal 115. The barrier metal 115 is a buffer material provided to connect the TMR element and the contact 114. The bit line BL is formed in the fourth metal wiring layer M4 above the TMR element and connected to the free magnetic layer FL of the TMR element.

A dummy TMR element DTMR and a barrier metal 116 are formed in a region where the reference memory cell MCR is not provided. Transistors included in the DL driver unit DLRDU are formed in a space below the barrier metal 116.

FIG. 14 is a cross-sectional view taken along section line XIV-XIV in FIG. FIG. 14 shows the cross-sectional structures of normal memory cell MC and reference memory cell MCR and the arrangement of power supply wiring ISL. Since the cross-sectional structure of reference memory cell MCR has been described with reference to FIG. 13, description thereof will not be repeated. The cross-sectional structure of the normal memory cell MC is the same as the cross-sectional structure of the reference memory cell MCR, and will be briefly described below.

As shown in FIG. 14, the source region 121 of the access transistor ATR for the normal memory cell MC is connected to the source line SL formed in the first metal wiring layer M1 via a contact 123. The drain region (not shown) of access transistor ATR is connected to upper layer barrier metal 125 via a contact (not shown).

In the region where the normal memory cell MC is formed, the main word line MWL is formed in the second metal wiring layer M2. The digit line DL is formed in the third metal wiring layer M3. The bit line BL is formed in the fourth metal wiring layer M4 and connected to the free magnetic layer of the TMR element.

The power supply wiring ISL is formed in the second metal wiring layer M2. The power supply line ISL is connected to the digit lines DL and DLR formed in the third metal wiring layer M3 via a contact 133. In the region where the power supply wiring ISL is formed, the main word line MWL is formed in the first metal wiring layer M1 in order to avoid the power supply wiring ISL. The main word line MWL is connected to the main word line MWL formed in the second metal wiring layer M2 in the adjacent region via

contacts

131 and 132.

Although not shown in FIG. 12, a dummy bit line DBL, a dummy TMR element DTMR, and a dummy barrier metal 116 are formed in the upper layer of the power supply wiring ISL.

FIG. 15 is a plan view showing an example of the configuration of the MOS transistor 61 of FIG. As shown in FIG. 12, it is desirable that the DL driver unit DLDU including the MOS transistor 61 is formed so that the length in the X direction is substantially within the wiring pitch of the digit line DL. Also, the current capacity of the MOS transistor 61 needs to be sufficient to allow the write current IDL to flow. Therefore, as shown in FIG. 15, the source region 161, the drain region 162, and the gate electrode 163 constituting the MOS transistor 61 are formed such that the gate width direction is the Y direction. The gate width W1 is set according to the amount of write current IDL. Drain region 162 is connected to digit line DL by wiring 164.

FIG. 16 is a plan view showing an example of the configuration of the MOS transistor 65 of FIG. As shown in FIG. 12, the length in the X direction of the DL driver unit DLRDU including the MOS transistor 65 is desirably formed within the same degree as the wiring pitch of the four digit lines DL. Therefore, as shown in FIG. 16, a comb-shaped electrode structure is adopted for the

gate electrodes

173A, 173B, and 173C of the MOS transistor 65. The source regions 171A and 171B, the drain regions 172A and 172B, and the

gate electrodes

173A, 173B, and 173C are formed so that the gate width direction is the Y direction. Drain regions 172A and 172B are connected to digit line DLR by wiring 174.

In the case of FIG. 16, the gate width of the MOS transistor 65 corresponds to three times (W2 × 3) the length W2 in the Y direction of the region where the transistor 65 is formed. By using such a configuration, the efficiency of layout arrangement increases. The gate width (W2 × 3) of the MOS transistor 65 may be shorter than the gate width W1 of the MOS transistor 61 shown in FIG. Since the length of the digit line DLR to which the MOS transistor 65 is connected is shorter than the length of the digit line DL to which the MOS transistor 61 is connected, the load impedance of the MOS transistor 65 is smaller than the load impedance of the MOS transistor 61. It is.

[Summary]
As described above, in MRAM device 4 according to the present embodiment, connecting portion ND between digit line DL for normal memory cell MC and digit line DLR for reference memory cell MCR is connected to power supply node VDD. A DL drive circuit 60N for the normal memory cell MC and a DL drive circuit 60R for the reference memory cell MCR are provided separately. As a result, at the time of data writing in the normal memory cell MC, the digit line current IDL flows from the power supply node VDD to the DL drive circuit 60N for the normal memory cell MC via the connecting portion ND and the corresponding digit line DL. The digit line DLR for the cell MCR does not flow. Therefore, erroneous inversion of the reference memory cell MCR due to the disturb magnetic field at the time of writing can be prevented.

Preferably, the number of rows of the reference memory cell array 10R is made smaller than the number of rows of the normal memory cell array 10N. Specifically, each row of the reference memory cell array 10R is formed for each of a plurality of rows (for example, 4 rows) of the normal memory cell array 10N. In this case, each digit line DL for the reference memory cell MCR is also provided for each of the digit lines DL for the plurality of normal memory cells MC. As a result, there is a free space in which the reference memory cell MCR and the digit line DLR corresponding thereto are not provided, and the DL drive circuit 60R for the reference memory cell MCR can be arranged without an area penalty using this free space. .

When the number of rows of the reference memory cell array 10R is smaller than the number of rows of the normal memory cell array 10N, the word line WL for the normal memory cell MC and the word line WLR for the reference memory cell MCR are separated and the normal memory It is necessary to separately provide the word line drive circuit 50N for the cell MC and the word line drive circuit 50R for the reference memory cell MCR. Also in this case, it is possible to arrange the word line drive circuit 50R using the empty space where the reference memory cell MCR and the corresponding digit line DLR and word line WLR are not provided.

[Modification]
Although FIG. 7 shows an example in which one row of the reference memory cell array 10R is provided for every four rows of the normal memory cell array 10N, it is not necessarily limited to this. For example, it is of course possible to provide one reference memory cell array 10R for every 16 rows of the regular memory cell array 10N. Conversely, a configuration in which the row of the normal memory cell array 10N and the row of the reference memory cell array 10R have a one-to-one correspondence requires a new space for arranging the digit line driver unit DLRDU for the reference memory cell MCR. However, it is technically possible.

In FIG. 8, two reference memory cells MCR which are provided in a common sub-memory array region and are preset in one high resistance state and the other low resistance state are simultaneously selected by one word line WLR. Although an example has been shown, the selection of the reference memory cell MCR is not necessarily limited to such an example. For example, when sense amplifiers SA0 and SA1 are provided in common with respect to the first and second sub memory array regions, the reference memory cell MCR provided in the first sub memory array region and the second sub memory array region There may be a case where the reference memory cells MCR provided in the sub memory array region are simultaneously selected by different word lines WLR. In this case, one of the selected reference memory cells MCR is preset in a high resistance state and the other is preset in a low resistance state.

The number of selected reference memory cells MCR is not necessarily two. For example, the electrical resistances of a large number of reference memory cells MCR exceeding two may be averaged, one reference memory cell MCR set to a low resistance state is selected, and a resistance element is added in addition to the reference memory cell Thus, the reference current may be generated. As described above, there are various methods for generating the reference current using the reference memory cell.

FIG. 7 shows an example in which the reference memory cell array 10R is composed of two columns of reference memory cells MCR and two bit lines BLR are provided corresponding to each column. The configuration of is not necessarily limited to such an example. Three or more reference memory cells MCR and three or more bit lines BLR corresponding to each column may be provided, and a necessary number of bit lines BLR may be selected at the time of data reading.

In FIG. 9, the power supply wiring ISL is connected to the power supply node VDD as the first power supply node, and the

current sources

64 and 68 are connected to the ground node GND as the second power supply node. By reversing this connection relationship, power supply line ISL is connected to ground node GND as the first power supply node, and

current sources

64 and 68 are connected to power supply node VDD as the second power supply node. Good. In this case, the write currents IDL and IDLR flow in the opposite direction to that in FIG.

Although FIG. 9 shows the case where one

current source

64, 68 is provided in each sub memory array region, it is not necessarily limited to this. For example, the

current sources

64 and 68 can be arranged for every two basic units BU.

The arrangement of the dummy cells DC is not limited to the position shown in FIG. As described in FIG. 7, the dummy cells are provided around the

memory cell arrays

10N and 10R in order to suppress non-uniformity in the shape of the semiconductor device manufacturing process. For example, in FIG. 12, it may be arranged immediately above and on both sides of the power supply wiring ISL.

The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 semiconductor device (microcomputer), 4 MRAM device, 10 memory array, 10R reference memory cell array, 10N regular memory cell array, 20 BL selection circuit, 30 readout circuit, 40 row decode circuit, 50 word line drive circuit, 50N WL drive circuit (For regular memory cell), 50R WL drive circuit (for reference memory cell), 60 digit line drive circuit, 60N DL drive circuit (for regular memory cell), 60R DL drive circuit (for reference memory cell), 61 NMOS transistor, 65 NMOS transistor, 70, 70A, 70B column decode circuit, 80, 80A, 80B bit line drive circuit, ATR access transistor, BL bit line (for regular memory cells), BLR bit line (reference Memory cell), DL digit line (for regular memory cell), DLR digit line (for reference memory cell), DLDU DL driver part (for regular memory cell), DLRDU DL driver part (for reference memory cell), GND ground node , ISL power supply wiring, MC regular memory cell, MCR reference memory cell, MWL main word line, SL source line (for regular memory cell), SLR source line (for reference memory cell), TMR TMR element, VDD power supply node, WL word Line (for regular memory cells), WLR word line (for reference memory cells), WLDU WL driver section (for regular memory cells), WLRDU WL driver section (for reference memory cells).

Claims

A normal memory cell array in which a plurality of normal memory cells each having a magnetoresistive effect element whose electrical resistance changes according to magnetic data are arranged in a matrix;
A reference memory cell array having a magnetoresistive effect element, in which a plurality of reference memory cells that are used as reference resistances by pre-writing magnetic data are arranged in a matrix;
A plurality of first digit lines each corresponding to a row of the normal memory cell array, each having a plurality of first digit lines provided along the corresponding row, in a first direction which is one of the row directions of the normal memory cell array A terminal portion of each of the plurality of first digit lines is connected to a first power supply node,
A plurality of second digit lines individually corresponding to at least a portion of the plurality of first digit lines, each extending along the first direction in connection with the terminal portion of the corresponding first digit line. Further comprising digit lines, each row of the reference memory cell array individually corresponding to each of the plurality of second digit lines and provided along a corresponding second digit line;
When writing magnetic data to the normal memory cell array, writing magnetic data to and from the first power supply node via the first digit line corresponding to the row including the normal memory cell to be written A first digit line drive circuit for passing a first write current required for
When magnetic data is written in the reference memory cell array in advance, the magnetic data is written to the first power supply node via the second digit line corresponding to the row including the reference memory cell to be written. And a second digit line drive circuit for supplying a second write current necessary for insertion.
2. The semiconductor device according to claim 1, wherein each of the plurality of second digit lines is provided for each of a plurality of the plurality of first digit lines.
The second digit line drive circuit includes a plurality of digit line driver units respectively corresponding to the plurality of second digit lines, and each of the plurality of digit line driver units is connected to a corresponding second digit line. Provided for flowing the second write current, and each of the plurality of digit line driver units is provided in a region adjacent to the corresponding second digit line in the column direction of the normal memory cell array; The semiconductor device according to claim 2.
Each of the plurality of normal memory cells and the plurality of reference memory cells further includes a switch element connected in series with the magnetoresistive effect element and having a control electrode,
The semiconductor device includes:
A plurality of first word lines provided corresponding to the rows of the normal memory cell array and connected to the control electrode of each normal memory cell included in the corresponding row;
A plurality of second word lines provided corresponding to the rows of the reference memory cell array and connected to the control electrode of each reference memory cell included in the corresponding row;
A first word line drive circuit for activating a first word line corresponding to a row including a normal memory cell to be read when reading magnetic data from the normal memory cell array;
And a second word line drive circuit for activating a second word line corresponding to a row including a reference memory cell used as a reference resistor when reading magnetic data from the normal memory cell array. The semiconductor device according to Item 2.
The second word line drive circuit includes a plurality of word line driver units respectively corresponding to the plurality of second word lines, and each of the plurality of word line driver units includes a corresponding second word line. 5. The method according to claim 4, wherein each of the plurality of word line driver units is provided in an area adjacent to a corresponding second word line in a column direction of the normal memory cell array. A semiconductor device according to 1.
The first digit line drive circuit includes a plurality of first MOS transistors respectively corresponding to the plurality of first digit lines, and each of the plurality of first MOS transistors includes a corresponding first digit. Provided between the line and the second power supply node, and allows the first write current to pass in an on state;
The second digit line drive circuit includes a plurality of second MOS transistors respectively corresponding to the plurality of second digit lines, and each of the plurality of second MOS transistors includes a corresponding second digit. Provided between the second power supply node and the second power supply node, and allows the second write current to pass in an on state,
2. The semiconductor device according to claim 1, wherein a gate width of each of the plurality of first MOS transistors is longer than a gate width of each of the plurality of second MOS transistors.
The semiconductor device further includes a power supply line connected to the terminal portion of each of the plurality of first digit lines, extending in a column direction of the normal memory cell array, and connected to the first power supply node. The semiconductor device according to claim 1.
A plurality of normal magnetic memories each including a magnetoresistive element having a laminated structure including a free layer whose magnetization direction is set according to stored data and a fixed layer whose magnetization direction is fixedly set regardless of stored data A regular memory cell array in which cells are arranged in a matrix;
Each of the normal magnetic memory cells includes a magnetoresistive element having a laminated structure including a free layer whose magnetization direction is set according to stored data and a fixed layer whose magnetization direction is fixed regardless of stored data, A reference memory cell array in which reference magnetic memory cells for generating a reference value for data determination when reading data from are arranged in a matrix;
A plurality of first write current lines arranged corresponding to the normal magnetic memory cell rows of the normal memory cell array and applying an induced magnetic field to the corresponding normal magnetic memory cells at the time of data writing;
A plurality of second write current lines arranged corresponding to the reference magnetic memory cell rows of the reference memory cell array and applying an induced magnetic field to the corresponding reference magnetic memory cells at the time of data writing, Each of the second write current lines shares a signal wiring with one of the predetermined number as one extension wiring for the predetermined number of the plurality of first write current lines,
Further, a power supply that is wired in a plane crossing the plurality of first write current lines and the plurality of second write current lines at a plurality of intersections in a boundary region between the normal memory cell array and the reference memory cell array. A plurality of first write current lines and the plurality of second write current lines are electrically connected to the power supply wiring at the plurality of intersections,
A plurality of first write current line drive circuits arranged to face the power supply wiring with the normal memory cell array interposed therebetween, and supplying a write current to the plurality of first write current lines;
A semiconductor device, comprising: a plurality of second write current drive circuits that are arranged to face the power supply wiring with the reference memory cell array interposed therebetween and allow a write current to flow through the plurality of second write current lines.
The reference memory cell array includes a plurality of shape dummy magnetoresistive elements, the plurality of reference magnetic memory cells and the plurality of shape dummy magnetoresistive elements are arranged in a matrix, and a lower layer region of the plurality of shape dummy magnetoresistive elements 9. The semiconductor device according to claim 8, wherein transistors included in the plurality of second write current drive circuits are arranged.
A plurality of main word lines provided corresponding to the predetermined number of the plurality of first write current lines and performing address selection in the row direction by the predetermined number unit; 9. The semiconductor device according to claim 8, wherein a line is also address-selected by a signal of the plurality of main word lines.
The semiconductor device includes:
A plurality of first bit lines arranged corresponding to the normal magnetic memory cell columns of the normal memory cell array and supplying a read current to the corresponding normal magnetic memory cells during data reading;
A plurality of second bit lines that are arranged corresponding to reference magnetic memory cell columns of the reference memory cell array and allow a read current to flow to the corresponding reference magnetic memory cells during the data reading;
Each of the plurality of normal magnetic memory cells and the plurality of reference magnetic memory cells includes an access transistor that conducts at the time of data reading and flows the read current to a corresponding magnetoresistive element;
The semiconductor device includes:
A plurality of first read word lines arranged corresponding to the normal magnetic memory cell rows of the normal memory cell array and connected to the gate electrodes of the access transistors of the corresponding normal magnetic memory cells;
A plurality of second read word lines arranged corresponding to the reference magnetic memory cell row of the reference memory cell array and connected to the gate electrode of the access transistor of the corresponding reference magnetic memory cell;
11. The plurality of first read word lines and the plurality of second read word lines are formed by different wirings, and all are address-selected by signals of the plurality of main word lines. Semiconductor device.