JP2007317948A - Nonvolatile memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile memory wherein the layout area of its memory array can be reduced. <P>SOLUTION: In the nonvolatile memory, each bit line BL is coupled electrically to each tunnel magnetic resistance element TMR of each memory cell. Each tunnel magnetic resistance element TMR is coupled electrically to one electrode of the electrodes of each access transistor ATR formed in each active layer provided in a substrate of an underlay. Further, the other electrode (source) of the electrodes of each access transistor ATR is coupled electrically via a contact CT to each source line SL formed in a first metal wiring layer. Each active layer is so formed zigzag in the shape of a Z character as to form in itself inclusively each access transistor of each memory cell, and the access transistor of the memory cell belonging to the memory-cell row and memory-cell column adjacent to each memory cell. While forming the two access transistors in the one active layer, a pair of memory cells belonging to the memory-cell rows and memory-cell columns adjacent to each other are coupled electrically to each corresponding source line by using a common contact CT. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a nonvolatile memory device, and more specifically to a random access memory including a memory cell having a magnetic tunnel junction (MTJ).

  In recent years, MRAM (Magnetic Random Access Memory) devices have attracted attention as a new generation of nonvolatile storage devices. An MRAM device is a non-volatile memory device that performs non-volatile data storage using a plurality of thin film magnetic bodies formed in a semiconductor integrated circuit and can randomly access each of the thin film magnetic bodies. In particular, in recent years, it has been announced that the performance of MRAM devices will be dramatically improved by using a thin film magnetic material using a magnetic tunnel junction (MTJ) as a memory cell.

  In general, when reading data from a memory cell used as a memory element of these nonvolatile memory devices, a current flowing through a tunnel magnetoresistive element (TMR element) constituting the memory element and a voltage across the TMR are measured. The resistance value of TMR can be measured indirectly.

  On the other hand, the cell structure of the MRAM device has been developed so as to be realized by a simple process like the cell structure of a DRAM (Dynamic Random Access Memory) device.

  Specifically, a memory cell of a general MRAM device has a structure in which a write word line is provided in addition to a read word line, but it is not necessary to provide a write word line. In recent years, a spin injection type memory cell has been proposed as a memory cell.

  In the spin injection type memory cell, the data writing method is different from the current MRAM device. The memory cell of the current MRAM device employs a method of reversing the magnetization by causing a magnetic field to flow through a wiring (including a write word line) adjacent to the TMR element. The memory cell employs a method of reversing the magnetization of the TMR element by the current directly flowing into the TMR element. By changing the direction of current flow, the magnetization of the free layer is switched parallel or antiparallel to the fixed layer. In this respect, it is called a spin injection method because the magnetization is reversed by the action of spin-polarized electrons in the current. As a result, it is not necessary to provide a special write word line for the memory cell of the MRAM device, and a simple cell structure can be realized.

  In order to minimize the layout area of the conventional memory array composed of the memory cells of the spin injection method, the source line SL and the bit line BL through which the data write current provided corresponding to the memory cell crosses each other. Was laid out to do.

  FIG. 29 is a diagram for explaining the layout of a conventional memory array in which source lines SL and bit lines BL of memory cells intersect. Here, a view of a memory array in which a plurality of memory cells are arranged in a matrix is viewed from the upper surface side.

  Referring to FIG. 29, the conventional memory array is provided with word lines WL corresponding to the memory cell rows along the X direction, and bit lines corresponding to the memory cell columns along the Y direction. BL is provided. A source line SL is provided along the X direction corresponding to each of the two memory cell rows. The source line SL is provided so as to cross the bit line BL along with the word line WL along the X direction.

FIG. 30 is a circuit configuration diagram of the conventional memory array shown in FIG.
Referring to FIG. 30, here, memory cells MC1 and MC2 are shown as an example, and each memory cell includes a tunnel magnetoresistive element TMR and an access transistor. Here, memory cells MC1 and MC2 include A case is shown in which access transistors ATR1 and ATR2 are respectively provided correspondingly. Access transistors ATR1 and ATR2 have their gates electrically coupled to word line WL, and their sources are electrically coupled to a common source line SL.

  Referring to FIG. 29 again, bit line BL is formed in the second metal wiring layer above the first metal wiring layer, and is electrically coupled to tunneling magneto-resistance element TMR of the memory cell. Tunneling magneto-resistance element TMR is electrically coupled to one electrode of access transistor ATR formed in an active layer provided on the base of the substrate. The other electrode (source) of access transistor ATR is electrically coupled to source line SL formed in the first metal wiring layer via contact CT. In this configuration, two access transistors are formed in one active layer, and the source line is electrically coupled to one source line using a common contact in two adjacent memory cell rows. A configuration is employed in which the layout area of the memory array is reduced by reducing the number of memory cells. In this example, active layers TA0 to TA2 are shown as an example, and active layer TA0 forms access transistors ATR1 and ATR2.

  Here, a layout area for forming a single memory cell MC of a conventional memory array will be considered.

  For example, when the tunnel magnetoresistive element TMR is arranged directly below the bit line BL, the length in the X axis direction is the width of the bit line BL in the X axis direction due to the length of the tunnel magnetoresistive element TMR in the X axis direction. Let MMx. The width of the space between adjacent memory cell columns is MSx. The length in the Y-axis direction is, for example, the width in the Y-axis direction of the source line SL is MLy. Further, here, for simplicity of explanation, it is assumed that the width in the Y-axis direction in which the tunnel magnetoresistive element TMR is arranged is the same width MLy as the source line SL, and is provided between the source line SL and the tunnel magnetoresistive element TMR. Assuming that the width of the word line WL in the Y-axis direction is MSy and the width of the space between adjacent memory cells is the same width MSy as the word line WL, the length of one memory cell MC in the X-axis direction Becomes MMx + MSx. The length in the Y-axis direction of one memory cell MC is (3MLy + 3MSy) /2=1.5MLy+1.5MSy. That is, one memory cell requires a layout area corresponding to the product of the lengths of the X axis and the Y axis.

  On the other hand, as described above, the spin injection type memory cell has a method of reversing the magnetization by the current flowing directly into the tunnel magnetoresistive element TMR, and thus is composed of a memory cell in which the source line SL and the bit line BL intersect in this way. In the memory array, when the word line WL is raised, only one memory cell can be accessed.

  Consider, for example, the case where a device capable of executing 256 Kbits of 32-bit parallel writing is configured when the maximum length of a source line and a bit line is limited to 512 bits or less due to the relationship between parasitic resistance and wiring capacitance.

  FIG. 31 is a schematic block diagram illustrating a layout of a decoder for selecting a memory cell provided corresponding to a memory array.

  As shown in FIG. 31A, normally, for example, a 512-bit-wide row decoder and column decoder can be provided adjacent to one memory array in the row direction or the column direction. In the case of an injection memory cell, only one cell can be accessed to one memory array, so that it is possible to execute 256 Kbit 32-bit parallel data writing or data reading. , 32 memory arrays of 8K bits are required.

  FIG. 31B shows an example of a device composed of 32 memory arrays of 8K bits. As shown in FIG. 31 (b), the number of drivers arranged in the row decoder and the column decoder is dramatically increased as compared with FIG. 31 (a).

  For example, consider a case where a row decoder corresponding to a row address and a column decoder corresponding to a column address are provided corresponding to an 8K-bit memory array. In this case, it can be realized by arranging 128 and 64 drivers adjacent to the row decoder and the column decoder, respectively. However, when applied to each of 32 memory arrays, the entire row decoder is 128 ×. 32 = 4096 drivers are arranged, and 64 × 32 = 2048 drivers are arranged for the entire column decoder, so that the overall layout area is greatly increased compared to the case of a single memory array. There is a problem of doing.

  Therefore, by arranging the source line SL and the bit line BL in the memory cell so that the source line SL and the bit line BL are both arranged in parallel in the same direction, data writing of a plurality of bits can be executed by one memory array. .

  In addition, although the prior art about this invention was demonstrated based on the general technical information which the applicant acquired, the information which should be disclosed as prior art document information before filing in the range which an applicant memorize | stores The applicant does not have

  FIG. 32 is a diagram for explaining the layout of a conventional memory array when source lines SL and bit lines BL of memory cells are provided in parallel along the Y-axis direction.

  Referring to FIG. 32, this memory array is provided with word lines WL corresponding to the memory cell rows along the X direction, and bit lines BL corresponding to the memory cell columns along the Y direction. Is provided. Further, along the Y direction, source lines SL are provided in parallel to the bit lines BL in correspondence with the memory cell columns, respectively.

FIG. 33 is a circuit configuration diagram of the conventional memory array shown in FIG.
Referring to FIG. 33, here, memory cells MC1 and MC2 are shown as an example, and the connection relationship between the memory cells is the same as that described in FIG. 30, and therefore the detailed description thereof will not be repeated. . However, source line SL provided corresponding to the memory cell column is provided in parallel with bit line BL, and access transistors ATR1 and ATR2 are both electrically coupled to common source line SL.

  Referring to FIG. 32 again, bit line BL is formed in the second metal wiring layer above the first metal wiring layer, and is electrically coupled to tunneling magneto-resistance element TMR of the memory cell. Tunneling magneto-resistance element TMR is electrically coupled to one electrode of access transistor ATR formed in an active layer provided on the base of the substrate. The other electrode (source) of access transistor ATR is electrically coupled to source line SL formed in the first metal wiring layer via contact CT. In this configuration, two access transistors are formed in one active layer and are electrically coupled to corresponding source lines using a common contact CT for two memory cells in the same column. . In this example, active layers TB0 to TB2 forming two access transistors are shown as an example, and the active layer TB0 forms access transistors ATR1 and ATR2.

  Here, a layout area for forming a single memory cell MC of the memory array will be considered.

  As described above, the length in the X-axis direction is caused by the length of the tunnel magnetoresistive element TMR in the X-axis direction when the tunnel magnetoresistive element TMR is arranged immediately below the bit line BL, for example. The width in the X-axis direction is MMx. The width in the X-axis direction when the source line SL is arranged is MLx. Further, the layout interval between the bit line BL and the source line SL in the X-axis direction is MSx. The length in the Y-axis direction is MSy of the width of the word line WL in the Y-axis direction. The width of the source line SL in the Y-axis direction is assumed to be MLy. Similarly, it is assumed that the width in the Y-axis direction in which the tunnel magnetoresistive element TMR is disposed is the same width MLy as that of the source line SL, and the width of the space between adjacent memory cells is assumed to be the same width MSy as that of the word line WL. Accordingly, the length of one memory cell MC in the X-axis direction is MMx + MLx + 2MSx. The length in the Y-axis direction of one memory cell MC is (3MLy + 3MSy) /2=1.5MLy+1.5MSy. That is, one memory cell requires a layout area corresponding to the product of the lengths of the X axis and the Y axis. When compared with the memory cell in which the bit line BL and the source line SL intersect, the length of the memory cell MC in the Y-axis direction is not changed, but the length of the memory cell MC in the X-axis direction is the case where the source line SL is provided. This requires a space for securing the space between the metal wiring width and the adjacent memory cell, and therefore there is a problem that the layout area increases as compared with the memory cell where the source line SL and the bit line BL intersect. That is, there is a problem that the layout area of the memory array increases as the storage capacity increases.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a nonvolatile memory device capable of reducing the layout area of a memory array.

  A nonvolatile memory device according to the present invention includes a plurality of memory cells integrated and arranged in a matrix, a plurality of word lines provided corresponding to memory cell rows, and a plurality provided respectively corresponding to memory cell columns. First current lines and a plurality of second current lines provided corresponding to two memory cell columns adjacent to each other, each provided between the first current lines. . Each memory cell includes a resistor memory element that performs non-volatile data storage in response to a passing current passing through the element, and a corresponding first and second current line in response to activation of a corresponding word line. A switching element for forming a current path between the magnetoresistive elements and a memory cell in each of the two memory cell columns is an adjacent memory cell row and is combined with a memory cell in the adjacent memory cell column. And a common contact portion for electrically coupling with the corresponding second current line.

  Another nonvolatile memory device according to the present invention includes a plurality of memory cells integrated and arranged in rows and columns, a plurality of word lines provided corresponding to the memory cell rows, and two adjacent to each other. And a plurality of first and second current lines respectively provided corresponding to the memory cell columns. Each memory cell includes a resistor memory element that performs non-volatile data storage in response to a passing current passing through the element, and a corresponding first and second current line in response to activation of a corresponding word line. And a switch element for forming a current path through the magnetoresistive element therebetween. Two memory cells adjacent to each other in one of the two memory cell columns are shared by a second current line corresponding to the other memory cell column. A first contact portion is further included. Two memory cells adjacent to each other in the other memory cell column of the two memory cell columns are commonly connected to a first current line corresponding to the one memory cell column. A second contact portion is further included.

  Still another nonvolatile memory device according to the present invention includes a plurality of memory cells arranged in a matrix according to a predetermined rule, a plurality of word lines respectively provided corresponding to memory cell rows, and a memory cell column. A plurality of current lines provided correspondingly, and each of the memory cells includes a resistor memory element that performs nonvolatile data storage according to a passing current passing through the element, and activation of a corresponding word line And a switch element for forming a current path through the magnetoresistive element between the corresponding current line and another adjacent current line. Four memory cells adjacent to each other in the memory cell column form a first and second memory cell set including two memory cells adjacent to each other. Two adjacent memory cells that constitute the same row as the first memory cell set in the two adjacent memory cell columns on one side of the memory cell column form a third memory cell set. Two adjacent memory cells that form the same row as the second memory cell set in the two adjacent memory cell columns on the other side of the memory cell column form a fourth memory cell set. Each memory cell of the first and third memory cell sets includes a current line corresponding to the memory cell column and an adjacent current line corresponding to a memory cell column between the two adjacent memory cell columns on the one side. Each memory cell of the second and fourth memory cell sets includes a current line corresponding to the memory cell column and the other two on the other side. A common second contact portion for electrically coupling adjacent current lines corresponding to memory cell columns between adjacent memory cell columns is provided.

  In the nonvolatile memory device according to the present invention, the first and second current lines are provided along the column direction which is the same direction, and the second current lines are shared by two adjacent memory cell columns. Therefore, the area for laying out the second current line can be reduced to reduce the layout area of the memory cell, and the layout area of the entire memory array can be reduced.

  Another non-volatile memory device according to the present invention is provided with first and second current lines corresponding to each of two memory cell columns, and one memory cell column via a first contact portion. The memory cell and the second current line are electrically coupled, and the memory cell of the other memory cell column and the first current line are electrically coupled via the second contact portion. Therefore, the area for laying out the source lines other than the bit lines can be reduced to reduce the layout area of the memory cells, and the layout area of the entire memory array can be reduced.

  Still another nonvolatile memory device according to the present invention includes a first memory cell set constituted by two memory cells and two adjacent ones constituting the same row as the first memory cell set. Since the third memory cell set constituted by the memory cells is electrically coupled to the current line corresponding to the memory cell column between the third memory cell set via the common first contact portion, The area for laying out the source lines can be reduced to reduce the layout area of the memory cell, and the layout area of the entire memory array can be reduced.

  Embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

(Embodiment 1)
FIG. 1 is a schematic block diagram showing an overall configuration of an MRAM device 1 shown as a representative example of a nonvolatile memory device according to Embodiment 1 of the present invention.

  Referring to FIG. 1, an MRAM device 1 includes a control circuit 5 for controlling the entire operation of MRAM device 1 in response to a control signal CMD, and a memory array including MTJ memory cells MC arranged in a matrix. 10. Here, the rows and columns of the plurality of memory cells MC arranged in each matrix of the memory array 10 are also referred to as memory cell rows and memory cell columns, respectively.

  The MRAM device 1 also includes a row decoder 20, a column decoder 25, and an input / output control circuit 30. The row decoder 20 selectively performs row selection in the memory array 10 to be accessed based on the row address RA included in the address signal ADD. The column decoder 25 selectively performs column selection of the memory array 10 to be accessed based on the column address CA included in the address signal ADD.

  The input / output control circuit 30 controls input / output of data such as the input data DIN and output data DOUT, and transmits the data to the internal circuit or outputs it externally in response to an instruction from the control circuit 5.

  In the following, the binary high voltage state and low voltage state such as signals, signal lines, and data are also referred to as “H” level and “L” level, respectively.

  In this example, a single memory cell MC is typically shown in memory array 10, and a word line WL provided corresponding to a memory cell row and a bit provided corresponding to a memory cell column One line BL and one source line SL are typically shown one by one.

FIG. 2 is a conceptual diagram illustrating memory cell MC according to the first embodiment of the present invention.
Referring to FIG. 2A, memory cell MC according to the first embodiment of the present invention includes tunneling magneto-resistance element TMR and access transistor ATR. Here, the MRAM memory cell having the above-described spin-injection tunneling magneto-resistance element TMR is representatively described. However, the present invention is not limited to this, and nonvolatile data storage is executed in accordance with the passing current passing through the element. Any resistor memory element can be applied in the same manner.

  Tunneling magneto-resistance element TMR and access transistor ATR are connected in series between bit line BL and source line SL. Specifically, access transistor ATR is provided between source line SL and tunneling magneto-resistance element TMR, and its gate is electrically coupled to word line WL. Tunnel magnetoresistive element TMR is electrically coupled between access transistor ATR and bit line BL.

  As will be described later, as a configuration for executing data writing to the memory cell MC, at least one of the bit line BL and the source line SL is set to a high potential or a low potential. That is, in data writing, data writing is executed by forming a current path from the bit line BL side to the source line SL side or from the source line SL side to the bit line BL side via the memory cell MC.

FIG. 2B is a diagram for explaining a cross-sectional view of the tunnel magnetoresistive element TMR.
Referring to FIG. 2B, tunneling magneto-resistance element TMR includes a ferromagnetic layer (fixed layer) (hereinafter also referred to as a pinned layer) PL having a fixed constant magnetization direction, and a current flowing into the element. A tunnel barrier (tunnel film) formed of an insulator film between a ferromagnetic layer (free layer) (hereinafter also simply referred to as a free layer) FL whose magnetization direction is reversed by the pinned layer PL and the free layer FL. ) BAL.

  Free layer FL is magnetized in the same direction as pinned layer PL or in the opposite direction to pinned layer PL, depending on the direction of the data write current that flows according to the level of the stored data to be written. These pinned layer PL, barrier layer BL, and free layer FL form a magnetic tunnel junction.

  The electric resistance of tunneling magneto-resistance element TMR changes according to the relative relationship between the magnetization directions of pinned layer PL and free layer FL. Specifically, the electric resistance of the tunnel magnetoresistive element TMR becomes a low resistance state (minimum value) Rmin when the magnetization direction of the free layer FL and the magnetization direction of the pinned layer PL are the same (parallel). When the magnetization direction is opposite (anti-parallel), a high resistance state (maximum value) Rmax is obtained. By associating the high resistance state Rmax and the low resistance state Rmin with the stored data “0” or “1”, nonvolatile data storage can be executed.

  In data writing, word line WL is activated and access transistor ATR is turned on. In this state, the magnetization direction is reversed depending on whether the data write current is supplied from the free layer FL to the pinned layer PL or the data write current is supplied from the pinned layer PL to the free layer FL.

  FIG. 3 is a diagram illustrating data writing in memory cell MC according to the first embodiment of the present invention.

  Referring to FIG. 3A, here, data write current Iwrite1 flows through tunneling magneto-resistance element TMR by setting bit line BL to a high potential and source line SL to a low potential. That is, in this case, the data write current Iwrite1 flows from the bit line BL side to the source line SL side. On the other hand, referring to FIG. 3B, here, the bit line BL is electrically connected to a low potential and the source line SL is electrically connected to a high potential. In this case, the data write current Iwrite2 flows from the source line SL side to the bit line BL side. That is, current passes from the pinned layer PL to the free layer FL.

  FIG. 4 is a diagram illustrating reversal of the magnetization direction of memory cell MC according to the first embodiment of the present invention.

  Referring to FIG. 4A, the case where the data write current Iwrite1 flows from the bit line BL side to the source line SL side will be described.

  Here, a case where the pinned layer PL is magnetized from right to left is shown. Then, the injected spin-polarized electrons flow from the direction opposite to the direction of the data write current Iwrite1, and spin electrons having the same direction as the magnetization direction of the pinned layer PL flow into the free layer FL. Therefore, the magnetization direction of the free layer FL is the same direction as that of the pinned layer PL, that is, parallel.

  Referring to FIG. 4B, it is a diagram illustrating a case where the data write current Iwrite2 flows from the source line SL side to the bit line BL side.

  Here, a case where the pinned layer PL is magnetized from right to left is shown. Then, the injected spin-polarized electrons flow from the direction opposite to the direction of the data write current Iwrite2, that is, the spin-polarized electrons flow from the free layer FL to the pinned layer PL. Then, the spin-polarized electrons flowing from the free layer FL pass through the spin-polarized electrons in the same direction as the pinned layer PL, and the spin-polarized electrons in the reverse direction are reflected and act on the free layer FL to be opposite to the pinned layer PL. Change direction. As a result, the magnetization directions of the free layer FL and the pinned layer PL are opposite (anti-parallel).

  FIG. 5 is a diagram illustrating a layout configuration of the memory cell according to the first embodiment of the present invention. Here, a view of a memory array in which a plurality of memory cells are arranged in a matrix is viewed from the upper surface side.

  Referring to FIG. 5, the memory array according to the first embodiment of the present invention is provided with two word lines WL corresponding to the memory cell rows along the X direction, and the memory array along the Y direction. Bit lines BL are provided corresponding to the respective cell columns. A source line SL is provided along the Y direction corresponding to each of the two memory cell columns. The source line SL is provided so as to be parallel to the bit line BL along the Y direction. Here, as an example, source lines SL1 and SL2 and bit lines BL1 to BL4 are representatively shown. One of the two word lines provided corresponding to the memory cell row is electrically coupled to the gate of the access transistor of the memory cell corresponding to the odd-numbered column. The other one is electrically coupled to the gate of the access transistor of the memory cell corresponding to the even column. Here, as an example, word lines WL1 to WL6 are representatively shown.

  Similarly to the above, bit line BL is formed in the second metal wiring layer above the first metal wiring layer, and is electrically coupled to tunneling magneto-resistance element TMR of the memory cell. Tunneling magneto-resistance element TMR is electrically coupled to one electrode of access transistor ATR formed in an active layer provided on the base of the substrate. The other electrode (source) of access transistor ATR is electrically coupled to source line SL formed in the first metal wiring layer via contact CT. The active layer according to the first embodiment of the present invention is zigzag in a Z shape so as to form an access transistor of a memory cell and an access transistor of an adjacent memory cell row and an adjacent memory cell column. Formed. In this configuration, two access transistors are formed in one active layer, and a common contact CT is used for two memory cells in adjacent memory cell rows and adjacent memory cell columns. It is electrically coupled to the corresponding source line. In this example, active layers TC <b> 0 to TC <b> 2 that form two access transistors are shown as an example.

  FIG. 6 is a diagram for explaining a cross-sectional structure of KP-KP # memory cells in the layout configuration of the memory array of FIG.

  Referring to FIG. 6, a wiring structure such as memory cell MC, source line SL, and bit line BL is shown.

  Specifically, access transistor ATR formed on P-type semiconductor substrate Psub has source / drain regions 102a and 102b which are N-type regions, and a gate region. The gate region of access transistor ATR is formed as polysilicon gate 106 in the same wiring layer as word line WL from the viewpoint of increasing the degree of integration. Source / drain region 102 a is coupled to tunneling magneto-resistance element TMR through contact hole 103, and tunneling magneto-resistance element TMR is electrically coupled to bit line BL formed in second metal interconnection layer 105. . Source / drain region 102b is electrically coupled to source line SL formed in first-layer metal interconnection layer 108 through contact hole 107 corresponding to contact CT. Note that the source / drain region 102b extends in a direction perpendicular to the paper surface so that the first metal wiring layer 108 forming the source line SL and the contact hole 103 do not overlap, and the contact hole 107 is used for contact. CT is formed. Since the same applies to the wiring structure of other memory cells MC, detailed description thereof will not be repeated.

FIG. 7 is a circuit configuration diagram of the memory cells of the memory array according to the first embodiment of the present invention.
Referring to FIG. 7, as described above, two word lines WL are provided corresponding to the memory cell rows, and here, word lines WL1 to WL6 are shown. Also, bit lines BL1 to BL4 and source lines SL1 and SL2 are shown corresponding to the memory cell columns. The source line SL1 is shared by two adjacent memory cell columns.

  As shown here, for example, memory cell MC1 is electrically coupled so as to share source line SL1 with memory cell MC2 in an adjacent memory cell row and in an adjacent memory cell column.

  Therefore, for example, when word line WL1 is activated, memory cell MC1 is accessed, and data writing is performed using two current lines for tunneling magneto-resistance element TMR sandwiched between bit line BL1 and source line SL1. Can be executed. In addition, since the tunnel magnetoresistive element TMR sandwiched between the bit line BL3 and the source line SL2 is also accessed in parallel, data writing can be executed even using the two current lines. That is, it is possible to execute parallel data writing of a plurality of bits.

  Here, a layout area for forming memory cell MC according to the first embodiment of the present invention will be considered.

  Referring again to FIG. 5, as described above, the length in the X-axis direction is, for example, the width of the bit line BL in the X-axis direction is MMx, and the width of the source line SL in the X-axis direction is MLx. Here, for simplicity of explanation, the layout interval between the bit line BL and the source line SL in the X-axis direction is set to the same width MSx as the source line SL. The width in the Y-axis direction for arranging the tunnel magnetoresistive element TMR is MLy. Here, the width in the Y-axis direction for arranging the two word lines WL is 2MSy. Note that a common active region is provided between the two word lines, and the source line SL and the access transistor ATR are electrically coupled via a contact CT provided on the common active region.

  The length in the X-axis direction of one memory cell MC is (2MMx + MLx + 3MSx) /2=MMx+0.5MLx+1.5MSx. Similarly, assuming that the width in the Y-axis direction in which the tunnel magnetoresistive element TMR is disposed is the same width MLy as the source line SL, the length in the Y-axis direction of one memory cell MC is (2MLy + 4MSy). / 2 = MLy + 2MSy. That is, one memory cell requires a layout area corresponding to the product of the lengths of the X axis and the Y axis. Compared with the layout area of the conventional memory cell of FIG. 31, when considering the length in the X-axis direction, MLx is generally larger than MSx, so the length in the X-axis direction is reduced, and Yx Considering the axial direction, MLy is generally larger than MSy, so the length in the Y-axis direction is also reduced, so the area of the memory cell MC is reduced, and the layout area of the memory array as a whole is greatly reduced. It becomes possible to do.

(Embodiment 2)
FIG. 8 is a diagram illustrating a layout configuration of the memory cell according to the second embodiment of the present invention. Here, a view of a memory array in which a plurality of memory cells are arranged in a matrix is viewed from the upper surface side.

  Referring to FIG. 8, the memory array according to the first embodiment of the present invention is provided with two word lines WL corresponding to the memory cell rows along the X direction, and the memory array along the Y direction. Bit lines BL are provided corresponding to the respective cell columns. Here, a configuration in the case where a bit line BL provided in an adjacent memory cell column is used as the source line SL is shown. That is, by using one of the two adjacent memory cell columns as the bit line BL and the other as the source line SL, the source line SL described in the first embodiment is eliminated. As an example, bit lines BL1 to BL4 are representatively shown. One of the two word lines provided corresponding to the memory cell row is electrically coupled to the gate of the access transistor of the memory cell corresponding to the odd-numbered column. The other one is electrically coupled to the gate of the access transistor of the memory cell corresponding to the even column. Here, word lines WL1 to WL8 are representatively shown as an example.

  Similarly to the above, bit line BL is formed in the second metal wiring layer above the first metal wiring layer, and is electrically coupled to tunneling magneto-resistance element TMR of the memory cell. Tunneling magneto-resistance element TMR is electrically coupled to one electrode of access transistor ATR formed in an active layer provided on the base of the substrate. The other electrode (source) of access transistor ATR is electrically coupled to a strap ST formed in a first metal wiring layer, which will be described later, via contact CT, and strap ST is adjacent to contact ST # via contact CT #. Electrically coupled to the bit line BL. The active layer according to the second embodiment of the present invention is provided so as to form access transistors of two memory cells in the same column. In this example, the active layers TD0 to TD2 are shown as an example. As will be described later, in this configuration, two access transistors are formed in one active layer and are electrically coupled to source lines corresponding to adjacent memory cell columns using a common contact portion. The contact portion includes a contact CT, a strap ST, and a contact CT #. The same applies to other configurations.

  FIG. 9 is a diagram illustrating a cross-sectional structure of the memory cell in the layout configuration of the memory array of FIG.

  FIG. 9A illustrates a cross-sectional structure of the memory cell when cut along KQ-KQ #.

  Referring to FIG. 9A, a wiring structure such as memory cell MC, source line SL, and bit line BL is shown.

  Specifically, access transistor ATR formed on P-type semiconductor substrate Psub has source / drain regions 102a and 102b which are N-type regions, and a gate region. The gate region of access transistor ATR is formed as polysilicon gate 106 in the same wiring layer as word line WL from the viewpoint of increasing the degree of integration. Source / drain region 102 a is coupled to tunneling magneto-resistance element TMR through contact hole 103, and tunneling magneto-resistance element TMR is electrically coupled to bit line BL formed in second metal interconnection layer 105. . Source / drain region 102b is electrically coupled to strap ST through contact hole 109 corresponding to contact CT. Strap ST is provided along the X-axis direction, and is electrically coupled to bit line BL provided in an adjacent memory cell column via contact hole 109 # corresponding to contact CT #. The same applies to access transistors formed in the same active layer. In this example, the source / drain region 102b is shared. Since the same applies to the wiring structure of other memory cells MC, detailed description thereof will not be repeated.

FIG. 9B illustrates a cross-sectional structure when cut along KR-KR #.
Referring to FIG. 9B, here, strap ST electrically coupled to source / drain region 102b via contact hole 109 is shown, and strap ST is connected to second region via contact hole 109 #. It is electrically coupled to bit line BL formed in the metal wiring layer. In other words, it is electrically coupled to the bit line of the adjacent memory cell column via contact holes 109 and 109 # and strap ST. Here, as an example, the case where the transistor of the memory cell corresponding to the bit line BL3 is electrically coupled to the bit line BL4 is shown.

  The strap ST is provided between two adjacent word lines with reference to FIG. 8, and as an example, the access transistor of the memory cell corresponding to the bit line BL1 is electrically coupled to the bit line BL2. The strap ST for performing the operation and the strap ST for electrically coupling the access transistor of the memory cell corresponding to the bit line BL2 and the bit line BL1 are alternately provided.

  FIG. 10 is a circuit configuration diagram of the memory cells of the memory array according to the second embodiment of the present invention.

  Referring to FIG. 10, as described above, two word lines WL are provided corresponding to the memory cell rows, and here, word lines WL1 to WL8 are shown. In addition, bit lines BL1 to BL4 provided corresponding to the memory cell columns are shown. As shown here, for example, the memory cell MC1 provided corresponding to the bit line BL1 is electrically connected to the bit line BL2 corresponding to the adjacent memory cell column together with the adjacent memory cell MC2 of the same column. Are combined. The memory cell MC3 provided corresponding to the bit line BL2 is electrically coupled to the bit line BL1 corresponding to the adjacent memory cell column together with the adjacent memory cell MC4 in the same column. That is, two adjacent memory cells in one of the two memory cell columns are electrically coupled to each other through a common contact with a bit line corresponding to the other memory cell column. Two memory cells adjacent to each other in the other memory cell column are electrically coupled to the bit line corresponding to the one memory cell column through a common contact.

  Therefore, when word line WL1 is activated, memory cell MC1 can supply data write current using bit lines BL1 and BL2, and can perform data writing. In addition, since tunnel magnetoresistive element TMR sandwiched between bit line BL3 and bit line BL4 is also accessed in parallel, data writing can be executed using the two current lines. That is, it is possible to execute parallel data writing of a plurality of bits.

  Here, a layout area for forming memory cell MC according to the first embodiment of the present invention will be considered.

  Referring to FIG. 8 again, since the length of the memory cell in the X-axis direction does not require the source line SL, the space width MSx between the bit line BL width MMx and the adjacent memory cell column is required. Only. That is, the length in the X-axis direction of one memory cell MC is MMx + MSx. Therefore, the length in the X-axis direction is shorter by MLx + MSx than the conventional memory cell described in FIG.

  Then, considering the length in the Y-axis direction, the width in the Y-axis direction for forming the strap ST is MLy. Further, here, when the word line WL for forming the gate region of the access transistor ATR is formed adjacent to the active layer, the pitch interval between the active layer and the word line WL is set to ensure a margin of the isolation region. The case where it forms a little apart is shown. Here, the width MSy + α is shown as an example. Assuming that MSy + α is MLy for simplicity, the length in the Y-axis direction of one memory cell MC is (4MLy + 4MSy + 2α) / 2 = 2MLy + 2MSy + α = 3MLy + MSy. That is, one memory cell requires a layout area corresponding to the product of the lengths of the X axis and the Y axis. Compared with the layout area of the memory cell described with reference to FIG. 32, the length in the Y-axis direction extends by 1.5 MLy−0.5 MSy, but the length in the X-axis direction is greatly reduced by MLx + MSx. In view of the area, the area of the memory cell MC can be greatly reduced, and the layout area of the memory array as a whole can be further reduced as compared with the conventional memory cell described with reference to FIG.

(Modification of Embodiment 2)
FIG. 11 is a diagram illustrating a layout configuration of a memory cell according to a modification of the second embodiment of the present invention. Here, a view of a memory array in which a plurality of memory cells are arranged in a matrix is viewed from the upper surface side.

  Referring to FIG. 11, the active layer forming access transistor ATR extends along the memory cell column, that is, along the Y-axis direction, as compared with the layout configuration of the memory cell described in FIG. It differs in that it is formed. Specifically, an active layer E0 is formed on the substrate in parallel with the bit line BL. Here, a case is shown in which active layers TE0 and TE1 are formed on the substrate on the substrate of the memory cell columns of bit lines BL1 and BL2, respectively.

  FIG. 12 is a diagram for explaining the cross-sectional structure of the memory cell in the layout configuration of the memory array of FIG.

  FIG. 12A illustrates a cross-sectional structure of the memory cell when cut along KS-KS #.

  Here, a case where a plurality of dummy access transistors ATR are provided adjacent to the active layer TE0 is shown in comparison with the cross-sectional structure described in FIG. Other parts are the same as those described with reference to FIG. 9, and therefore detailed description thereof will not be repeated.

  FIG. 12B is a diagram for explaining a cross-sectional structure of the memory cell when cut by KT-KT #.

  In this case as well, a cross-sectional structure similar to that described in FIG. 9 is shown, but the active layer is shown extending in the same direction without being separated.

  FIG. 13 is a circuit configuration diagram of the memory cells of the memory array according to the modification of the second embodiment of the present invention.

  Referring to FIG. 13, as described above, two word lines WL are provided corresponding to the memory cell rows. Here, word lines WL1 to WL8 are shown. In addition, bit lines BL1 to BL4 provided corresponding to the memory cell columns are shown. The basic configuration is the same as that described with reference to FIG. 10 except that a dummy access transistor is provided in the same active layer. That is, the access transistor is continuously formed. Here, the access transistor to which the symbol “x” is added indicates a dummy access transistor that is not used for accessing the memory cell. The dummy access transistors are connected in series, and different word lines are provided in the gate regions. Therefore, even when any one word line WL is activated and the dummy access transistor is turned on, a current path is not formed, and there is a problem in executing data writing. Absent.

  In this configuration, the active layer TE0 extends along the Y-axis direction and is laid out on the substrate, and the layout pattern of the access transistor ATR and the tunnel magnetoresistive element TMR can be formed uniformly. The processing is facilitated, and it is not necessary to secure the margin of the separation region described with reference to FIG. Therefore, since the length of the memory cell in the Y-axis direction can be further shortened, the area of the memory cell can be reduced, and the layout area of the memory array as a whole can be further reduced as compared with the second embodiment. .

(Embodiment 3)
FIG. 14 is a diagram illustrating a layout configuration of the memory cell according to the third embodiment of the present invention. Here, a view of a memory array in which a plurality of memory cells are arranged in a matrix is viewed from the upper surface side.

  Referring to FIG. 14, in the memory array according to the third embodiment of the present invention, word lines WL are provided corresponding to the memory cell rows along the X direction, and the words of the adjacent memory cell rows according to a certain rule. Electrically coupled to the wire. A bit line BL is provided along the Y direction corresponding to each memory cell column. As an example, bit lines BL1 to BL7 are representatively shown. Here, word lines WL1 to WL8 are representatively shown as an example.

  The plurality of memory cells of the memory array have an arrangement pattern according to a predetermined rule. Specifically, as an array pattern of the memory cells constituting one memory cell column, memory cells are arranged in two consecutive rows with seven memory cell rows as a set, and the remaining five rows The arrangement pattern is such that two memory cells are arranged in a row, and the arrangement pattern of adjacent memory cell columns is the same arrangement with the same arrangement pattern shifted by two rows.

  In addition, as an array pattern of memory cells constituting one memory cell row, four memory cells are continuously arranged with one set of seven memory cell columns, and the remaining three columns are not arranged. Further, the memory cells are arranged in the next four columns in succession, and the remaining three columns are repeated arrangement patterns that are not arranged. As an arrangement pattern of adjacent memory cell rows, the same arrangement pattern has four columns each. The arrangement pattern is shifted.

  The connection relationship with the word line WL will be described. A word line WL provided corresponding to a memory cell row is provided, and memory cells arranged in four consecutive columns in the array pattern of the memory cell row. Of the memory cells are electrically coupled to the word line WL of the memory cell row, and the even-numbered memory cell is electrically coupled to the word line WL corresponding to the adjacent memory cell row. Is done.

  This configuration shows a configuration in which a bit line BL provided in an adjacent memory cell column is used as a source line SL, and bit lines at both ends of any three adjacent bit lines are sandwiched between them. A configuration using a bit line as a source line is shown.

  Bit line BL is formed in the second metal wiring layer above the first metal wiring layer, as described above, and is electrically coupled to tunneling magneto-resistance element TMR of the memory cell. Tunneling magneto-resistance element TMR is electrically coupled to one electrode of access transistor ATR formed in an active layer provided on the base of the substrate. The other electrode (source) of access transistor ATR is electrically coupled to strap ST # formed in the first metal wiring layer via contact CT, and is connected to adjacent bit line BL via strap ST #. Electrically coupled.

  More specifically, four memory cells adjacent to each other in the memory cell column constitute a first and second memory cell set including two memory cells adjacent to each other. Further, the memory cell column is adjacent to one side of the memory cell column, and the first memory cell set and the third memory cell set including the two adjacent memory cells constituting the same row are common. Are electrically coupled to the bit line corresponding to the next memory cell column through the contact. The second memory cell column on the other side is the same as the second memory cell set and the fourth memory cell set including the two adjacent memory cells constituting the same row as the second memory cell set. Are electrically coupled to the bit line corresponding to the next memory cell column through the contact.

  For example, FIG. 14 shows memory cell sets MCU1 and MCU2 each including two memory cells in a memory cell column corresponding to bit line BL5. For memory cell set MCU1, two adjacent bit lines are shown. The memory cell set MCU1 in the memory cell column corresponding to BL7 and the memory cell set in the same row are electrically coupled to each other by the strap ST # through the contact CT, and the strap ST # and the adjacent bit line BL6 are connected to each other. The case where it is electrically coupled via the contact CT # is shown. Further, for the memory cell set MCU2, the memory cell set MCU2 of the memory cell column corresponding to the two adjacent bit lines BL3 and the memory cell set in the same row are electrically coupled to each other by the strap ST # via the contact CT. In this example, strap ST # and one adjacent bit line BL4 are electrically coupled via contact CT #.

  The active layer according to the third embodiment of the invention is provided so as to form access transistors for two memory cells in the same column. In this example, the active layers TF0 to TF2 are shown as an example. In this configuration, two access transistors are formed in one active layer, and are electrically coupled to bit lines corresponding to adjacent memory cell columns using a common contact.

  In this configuration, since two memory cell sets MCU share one common strap ST #, the number of ST # layouts is reduced compared to the configuration of the second embodiment. Accordingly, the area for laying out the strap ST # can be reduced, the length of the memory cell in the Y-axis direction can be reduced, the layout area of the memory cell MC can be reduced, and the layout of the memory array as a whole The area can be reduced.

  FIG. 15 is a circuit configuration diagram of the memory cells of the memory array according to the third embodiment of the present invention.

  Referring to FIG. 15, as described above, two word lines WL are provided corresponding to the memory cell rows. Here, word lines WL1 to WL8 are shown. In addition, bit lines BL1 to BL7 provided corresponding to the memory cell columns are shown. As shown here, for example, the memory cell MC1 provided corresponding to the bit line BL1 is electrically connected to the bit line BL2 corresponding to the adjacent memory cell column together with the adjacent memory cell MC2 of the same column. Are combined. Memory cell MC3 provided corresponding to bit line BL3 in the same row as memory cells MC1 and MC2 and adjacent memory cell MC4 in the same column are electrically connected to bit line BL2 corresponding to the adjacent memory cell column. Are combined.

  Therefore, when the word line WL1 is activated, the two memory cells MC1 and MC3 are accessed, and either the pair of the bit line BL1 and the bit line BL2 or the pair of the bit line BL3 and the bit line BL2 is accessed. Can be used to write data to any one of the corresponding memory cells. In this case, by setting the potential levels of the three bit lines, a data write current can be supplied to a desired memory cell, and data writing can be executed. The data writing and data reading will be described later. Memory cells MC1 and MC3 form one memory cell unit that is accessed simultaneously. Memory cells MC2 and MC4 form one memory cell unit that is accessed simultaneously.

  Since the tunnel magnetoresistive element TMR sandwiched between the bit line BL4 and the bit line BL5 or the bit line BL5 and the bit line BL6 is also accessed in parallel, data writing can be executed using the two current lines. Can do. That is, it is possible to execute parallel data writing of a plurality of bits.

  Now, consider a layout area for forming memory cell MC according to the third embodiment of the present invention.

  Referring to FIG. 14 again, since the length of the memory cell in the X-axis direction does not require the source line SL, the space width MSx between the bit line BL width MMx and the adjacent memory cell column is required. Only. That is, the length in the X-axis direction of one memory cell MC is MMx + MSx. Therefore, it becomes shorter by MLx + MSx than the conventional memory cell described in FIG.

  Then, considering the length in the Y-axis direction, the width in the Y-axis direction for forming the strap ST # is MLy. Further, as described in the second embodiment, since it is necessary to form the active layer and the word line WL with a little pitch interval in order to secure a margin of the isolation region, the word line WL is formed here. The width in the Y-axis direction to be arranged is shown as MSy + α.

  Then, the length in the Y-axis direction of one memory cell MC is (7MLy + 7MSy + 3α) / 4. That is, it is further shortened by (MLy + MSy + α) / 4 along the Y-axis direction as compared with the memory cell of the second embodiment. One memory cell requires a layout area corresponding to the product of the lengths of the X axis and the Y axis. Compared with the layout area of the memory cell of the second embodiment of the present invention, the length in the Y-axis direction is further shortened by (MLy + MSy + α) / 4, so the area of the memory cell MC is greatly reduced, and the memory array as a whole This layout area can be further reduced as compared with the second embodiment.

(Modification of Embodiment 3)
FIG. 16 is a diagram illustrating a layout configuration of a memory cell according to a modification of the third embodiment of the present invention. Here, a view of a memory array in which a plurality of memory cells are arranged in a matrix is viewed from the upper surface side.

  Referring to FIG. 16, the active layer forming access transistor ATR extends along the memory cell column, that is, along the Y-axis direction, as compared with the layout configuration of the memory cell described in FIG. It differs in that it is formed. Specifically, an active layer TG0 is formed on the substrate in parallel with the bit line BL. Here, a case where active layers TG0 to TG2 are respectively formed on the substrate on the substrate of the memory cell column corresponding to the bit lines BL1 to BL3 is shown.

  FIG. 17 is a circuit configuration diagram of the memory cells of the memory array according to the modification of the third embodiment of the present invention.

  Referring to FIG. 17, as described above, two word lines WL are provided corresponding to the memory cell rows. Here, word lines WL1 to WL8 are shown. In addition, bit lines BL1 to BL7 provided corresponding to the memory cell columns are shown. The basic configuration is the same as that described with reference to FIG. 15 except that a dummy access transistor is provided in the same active layer. That is, the access transistor is continuously formed. As described above, the access transistor to which the symbol “x” is added indicates a dummy access transistor that is not used for accessing the memory cell. The dummy access transistors are connected in series, and different word lines are provided in the gate regions. Therefore, even when any one word line WL is activated and the dummy access transistor is turned on, a current path is not formed, and there is a problem in executing data writing. Absent.

  In this configuration, the active layer TG0 extends along the Y-axis direction and is laid out on the substrate, and the layout pattern of the access transistor ATR and the tunnel magnetoresistive element TMR can be formed uniformly. The processing is facilitated, and it is not necessary to secure a margin of the separation region described with reference to FIG. That is, the pitch interval for laying out the word lines WL can be set to MSy. Therefore, since the length of the memory cell in the Y-axis direction can be further reduced, the area of the memory cell can be reduced, and the layout area of the memory array as a whole can be further reduced as compared with the third embodiment. .

(Embodiment 4)
In a fourth embodiment of the present invention, a decoder capable of executing 256 Kbit 32-bit parallel data writing and data reading corresponding to the above memory array will be described.

Here, the memory array described in Embodiment 3 is used as an example for description.
FIG. 18 is a diagram illustrating a peripheral circuit of the memory array according to the fourth embodiment of the present invention.

  Referring to FIG. 18, an example of a memory array and a decoder for selecting the memory array is shown here.

  Further, there are provided circuits constituting a data write circuit for executing data write of the selected memory cell and a data read circuit for executing data read. In this example, x included in the data write circuit is provided. As an example, a data write unit WDCx that performs data write to a bit-th memory cell and a data read unit RDCx that performs data read from an x-th memory cell included in the data read circuit are shown as an example. Has been.

  The memory array is divided into four column blocks CBL0 to CBL3 in the column direction. Here, a part of the column block CBL0 which is one column block is shown as an example. Each column block CBL is divided into 32 block areas BU. As an example, in this example, a block BUx and a block BUx + 1 surrounded by a dotted line region are shown. In this configuration, any one of the four column blocks CBL0 to CBL3 is selected, and in the selected column block CBL, 1-bit data writing or data reading is performed in each of the 32 block regions BU. Is configured to be executable. That is, the data can be written or read in parallel in 32 bits.

  First, a column decoder part CLDC for selecting any one of the column blocks CBL0 to CBL3 and a column that is provided adjacent to the memory array and performs column selection in response to a column selection instruction from the column decoder part CLDC A switch part CLSG is provided. The column switch section CLSG is composed of a plurality of column switches CLG. Specifically, each column switch CLG includes a plurality of gate transistors that electrically couple one bit line provided in each column block CBL and a switch control unit SWC described later. Specifically, it is composed of four gate transistors that are electrically coupled to the bit lines provided in each column block CBL, and in response to a column selection instruction of the column decoder section CLDC, the column blocks CBL0 to CBL3. Among these, a bit line included in one column block CBL is electrically coupled to a switch control unit SWC described later.

  Note that the column decoder CLDC selects any one of the column blocks CBL0 to CBL3 based on a combination of two bits of the column addresses CA0 and CA1. In this example, a case where the column block CBL0 is selected will be described.

  Next, the row selection operation will be described. The lower two bits RA0 and RA1 of the row addresses RA0 to RA10 are used in the column selection operation and are used in the switch control unit SWC and the data write unit WDCx or the data read unit RDCx, which will be described later. The row selection operation of the word line WL is executed using the remaining row addresses RA2-RA10.

  In this configuration, every seven word lines are divided into a plurality of groups. In this example, a word driver WDV provided corresponding to each of the seven word lines WL is shown as an example.

  In the configuration according to the fourth embodiment, a predecoder PDC is provided, and predecodes input row addresses RA2 to RA10 to generate a 4-bit predecode signal.

FIG. 19 is a schematic block diagram of predecoder PDC according to the fourth embodiment of the present invention.
Referring to FIG. 19, predecoder PDC according to the fourth embodiment of the present invention has one decoder unit DEC7a and decoder units DEC7b and DEC7b #. The decoder unit DEC7b and the decoder unit DEC7b # have the same function and the same circuit configuration.

  FIG. 20 is a circuit configuration diagram of predecoder unit PDEC7a included in decoder unit DEC7a according to the fourth embodiment of the present invention.

  Referring to FIG. 20, predecoder unit PDEC 7a according to the fourth embodiment of the present invention receives a 5-bit address input and generates 32 predecode signals. Specifically, for example, an “H” level signal is output from one of the output terminals S0 to S31 based on the row addresses RA6 to RA10 input to the input terminals A0 to A5. The remaining output terminals S output “L” level signals.

  FIG. 21 is a circuit configuration diagram of a division circuit that outputs a quotient and a remainder divided by 7 in response to input of 32 predecode signals from the predecoder unit PDEC7a.

FIG. 21A is a circuit that outputs the quotient of the division circuit.
More specifically, for example, an “H” level signal is output from one output terminal Q of the output terminals Q8 to Q12 of a circuit that outputs a quotient in response to input of 32 predecode signals. The remaining output terminals Q are at “L” level.

FIG. 21B is a circuit that outputs the remainder of the division circuit.
More specifically, for example, an “H” level signal is output from one output terminal R of the output terminals R0 to R6 of the circuit that outputs the remainder in response to the input of 32 predecode signals. The remaining output terminals R are at “L” level.

  These division circuits are designed to output the quotient and remainder obtained by dividing by 7 in response to the input of 32 predecode signals.

  FIG. 22 is a circuit configuration diagram of decoder unit DEC7b according to the fourth embodiment of the present invention.

  Referring to FIG. 22, decoder unit DEC 7b according to the fourth embodiment of the present invention provides a predecode signal obtained on the basis of a combination of a predecode signal indicating a remainder input from the upper stage and a 2-bit row address RA. It is a circuit block diagram of the division circuit which outputs the quotient and remainder which divided by 7 in response to the input.

  Referring to FIG. 22A, specifically, a circuit configuration of a predecoder unit that generates four predecode signals in response to input of a 2-bit row address RA is shown. Specifically, for example, an “H” level signal is output from one of the output terminals S0 to S3 based on the combination of the row addresses RA4 to RA5 input to the input terminals A0 to A1. The remaining output terminals S output “L” level signals.

  Referring to FIG. 22B, here, a predecode signal obtained based on a combination of the output terminals S0-S3 of the predecoder unit of FIG. 22A and a signal indicating the remainder from the decoder unit DEC7a. A circuit configuration diagram for outputting the quotient of the division circuit divided by 7 in response to the input of. Specifically, for example, an “H” level signal is output from one of the output terminals Q4 to Q7 of the circuit that outputs the quotient. The remaining output terminals Q are at “L” level.

  Referring to FIG. 22C, here, a predecode signal obtained based on a combination of the output terminals S0-S3 of the predecoder unit of FIG. 22A and a signal indicating the remainder from the decoder unit DEC7a. The circuit configuration diagram for outputting the remainder of the division circuit divided by 7 in response to the input of. Specifically, an “H” level signal, for example, is output from one output terminal R of the output terminals R0 to R6 of the circuit that outputs the remainder in response to the input of the predecode signal. The remaining output terminals R are at “L” level.

  These division circuits output the quotient and the remainder in response to the input of the predecode signal obtained based on the combination of the output terminals S0 to S3 of the predecoder unit and the signal indicating the remainder from the decoder unit DEC7a. It is designed to be.

  Similarly, the other decoder unit DEC7b # receives the quotient and remainder divided by 7 in response to the input of the row addresses RA2 and RA3 and the predecode signal indicating the remainder from the upper decoder unit DEC7b. Output. Specifically, for example, an “H” level signal is output from one of the output terminals Q0 to Q3 of the circuit that outputs the quotient. The remaining output terminals Q are at “L” level. Further, for example, an “H” level signal is output from one of the output terminals R0 to R6 of the circuit that outputs the remainder. The remaining output terminals R are at “L” level.

  Referring again to FIG. 19, as described above, one predecode signal indicating a quotient is output from one output terminal of output terminals Q8-Q12 of decoder unit DEC7a. Further, one predecode signal indicating a quotient is output from one output terminal of the output terminals Q4 to Q7 of the decoder unit DEC7b. Also, one predecode signal indicating a quotient is output from one output terminal of the output terminals Q0 to Q3 of the decoder unit DEC7b #, and one indicating a remainder from one output terminal of the output terminals R0 to R6. A predecode signal is output. That is, this predecoder PDC outputs a 3-bit predecode signal indicating the quotient divided by 7 and a 1-bit predecode signal indicating the remainder in response to the input of the row address RA2-RA10.

  Based on the combination of the predecode signals indicating the quotient, one of the word line groups divided into a plurality of groups is selected with the seven word lines as one group as described above. In FIG. 18, the signal lines connected to the output terminals Q8 to Q12, the signal lines connected to the output terminals Q4 to Q7, and the signal lines connected to the output terminals Q0 to Q3, respectively. An AND circuit AD that selects one of word line groups divided into a plurality of groups is shown as an example. Then, based on the combination of the output result from the AND circuit AD and the signal lines connected to the output terminals R0 to R6 indicating the remainder, the seven lines included in the word line group selected by the word driver WDV. One word line of the word lines WL is selected.

Next, the selection operation in each block area BU will be described.
Adjacent to the memory array, a selected column block CBL and a switch control unit SWC electrically coupled to the data read circuit or the data write circuit are provided.

  The switch control unit SWC includes a plurality of switch units SDCUx provided corresponding to the plurality of block regions BUx included in the column block CBL. Switch unit SDCUx controls electrical coupling between corresponding block region BUx and corresponding data read unit RDCx or data write unit WDCx included in the data read circuit or data write circuit.

  In addition, a sub-decoder SDC that outputs selection signals to the seven selection lines that control the switch control unit SWC is provided. The subdecoder SDC selects and activates one of the seven selection lines based on the combination of the row address RA1 and the predecode signal indicating the remainder of the predecoder PDC.

  Switch unit SDCUx selects three bit lines adjacent to each other in response to an instruction of a selection signal from subdecoder SDC and is electrically coupled to data read unit RDCx or data write unit WDCx.

  Here, for example, consider a case where the word line WL is selected in one block region BU.

  When one of the plurality of word lines WL is activated in response to the input of the row addresses RA2 to RA10, four memory cells are accessible in one block area BU. Specifically, as described in the third embodiment, two sets of memory cell units each including two memory cells accessed simultaneously are accessed. One memory cell unit is electrically coupled to three bit lines. In the case of this configuration, since two memory cell units are accessed, current paths of six bit lines in total of three bit lines are provided. Is formed.

  The subdecoder SDC selects one of the seven selection lines based on the combination of the row address RA1 and the predecode signal indicating the remainder of the predecoder PDC. Accordingly, the switch unit SDCUx selects one of the two accessible memory cell units. Specifically, the data read unit RDCx or the data write unit WDCx is selected by selecting three bit lines corresponding to one set of memory cell units out of six bit lines corresponding to two sets of memory cell units. Electrically coupled with.

  More specifically, switch unit SDCUx electrically couples the first bit line of the three bit lines and internal node N0. The middle second bit line is electrically coupled to internal node N1. Further, the third bit line is electrically coupled to internal node N2.

  Then, the data write unit WDCx writes the row address RA0 and the write data DWx in order to write data corresponding to the write data DWx to any one of the selected memory cell units. Is used to set the voltage level of the internal node.

Here, the configuration of data writing unit WDCx will be described.
Data write unit WDCx includes AND circuit 11, exclusive OR circuits 12 and 13, and buffers 14 and 15. The exclusive OR circuit 12 executes an exclusive OR operation based on the input of the row address / RA0, which is an inverted signal of the row address RA0, and the write data DWx, and outputs the result to the buffer 14. The buffer 14 operates based on the input of the control signal R / W that defines the data read operation or data write operation, buffers the output result of the exclusive OR circuit 12 and transmits it to the node N2. The exclusive OR circuit 13 executes an exclusive OR operation based on the input of the row address RA0 and the write data DWx and outputs the result to the buffer 15. The buffer 15 operates based on the input of the control signal R / W defining data reading or data writing, and buffers the output result of the exclusive OR circuit 13 and transmits it to the node N0. The AND circuit 11 transmits an AND logic operation result to the node N1 based on the input of the write data DWx and the control signal R / W. In the case of data reading or data writing, control signal R / W is set to “L” level and “H” level, respectively.

  Therefore, for example, when data reading is executed, the output of AND circuit 11 is at “L” level based on the input of control signal R / W (“L” level), and buffers 14 and 15 are controlled. In response to the input of the signal R / W (“L” level), it does not operate and both outputs are at the “L” level. That is, in the case of data reading, data writing unit WDCx does not function.

  On the other hand, when data writing is executed, the output of AND circuit 11 is set to a logic level corresponding to write data DWx based on the input of control signal R / W (“H” level). Specifically, when the write data DWx is at “H” level corresponding to “1”, the node N1 is set to “H” level, and the write data DWx is “L” corresponding to “0”. In the case of the level, the node N1 is set to the “L” level.

  The exclusive OR circuits 12 and 13 receive the row address RA0 and the inverted address row address / RA0, respectively, and execute an exclusive OR operation with the write data DWx. Since the logical level is the same as that of the write data DWx, the exclusive OR circuit whose inputs match among the exclusive OR circuits 12 and 13 outputs an “L” level signal, and the other input does not match. The OR circuit outputs “H” level.

  For example, when row address RA0 is at “H” level and write data DWx is at “H” level, signals of “L” level and “H” level are respectively sent from buffers 14 and 15 to nodes N2 and N0. Each is transmitted. That is, the nodes N0 to N2 are set to “H” level, “H” level, and “L” level, respectively. On the other hand, when row address RA0 is at "H" level and write data DWx is at "L" level, "H" level and "L" level signals from buffers 14 and 15, respectively, are sent to nodes N2 and N0. Each is transmitted. That is, the nodes N0 to N2 are set to “L” level, “L” level, and “H” level, respectively.

  On the other hand, when row address RA0 is at “L” level and write data DWx is at “H” level, signals of “H” level and “L” level from buffers 14 and 15 are sent to nodes N2 and N0, respectively. Each is transmitted. That is, the nodes N0 to N2 are set to “L” level, “H” level, and “H” level, respectively. On the other hand, when row address RA0 is at “L” level and write data DWx is at “L” level, signals of “L” level and “H” level from buffers 14 and 15 are sent to nodes N2 and N0, respectively. Each is transmitted. That is, the nodes N0 to N2 are set to “H” level, “L” level, and “L” level, respectively.

  As described above, the switch unit SDCUx selects one of the two accessible memory cell units, and the first to third of the three bit lines corresponding to the selected memory cell unit. Are connected to nodes N0, N1, and N2, respectively.

  Therefore, when row address RA0 is at "H" level, the memory cell sandwiched between the second bit line and the third bit line corresponding to the memory cell unit is accessed, and write data DWx It is possible to execute data writing according to the above. Specifically, when write data DWx is at “H” level, node N2 is electrically connected to second node via the access transistor ATR and tunneling magneto-resistance element TMR from the second bit line electrically coupled to node N1. A data write current is supplied to the third bit line that is coupled to each other. On the other hand, when write data DWx is at "L" level, it is electrically coupled to node N1 through access transistor ATR and tunneling magneto-resistance element TMR from the third bit line electrically coupled to node N2. A data write current is supplied to the second bit line.

  On the other hand, when the row address RA0 is at "L" level, the memory cell sandwiched between the first bit line and the second bit line corresponding to the memory cell unit is accessed, and the write data DWx It is possible to execute data writing according to the above. Specifically, when write data DWx is at “H” level, node N0 is electrically connected to node N0 via access transistor ATR and tunneling magneto-resistance element TMR from the second bit line electrically coupled to node N1. A data write current is supplied to the first bit line coupled to the first bit line. On the other hand, when write data DWx is at "L" level, it is electrically coupled to node N1 through access transistor ATR and tunneling magneto-resistance element TMR from the first bit line electrically coupled to node N0. A data write current is supplied to the second bit line.

  In the memory array of the present configuration, any one of the column blocks CBL0 to CBL3 is selected by the column decoder section CLDC to which the 2-bit column addresses CA0 and CA1 are input. Each column block CBL is divided into 32 block areas BU, and one word line WL is selected based on the output result of the predecoder PDC to which the row address RA2-RA10 is input. In each block area BU, two memory cell units corresponding to the selected word line WL are selected, and one of the two memory cell units is selected by the sub-decoder SDC to which the row address RA1 is input. Is done. Then, the data write unit WDCx provided corresponding to each block region BU responds to the input row address RA0 and either one of the two memory cells constituting the selected memory cell unit. Is written in accordance with the write data DWx. Since the column block CBL is composed of 32 block areas BU as a whole, 32-bit parallel data writing is executed by executing 1-bit data writing in each block area BU. Can do.

  Although data writing has been described here, the same applies to data reading. Here, the configuration of the data reading unit DRCx will be described.

  Data read unit DRCx includes buffers 16 and 17 and sense amplifiers 18 and 19. Sense amplifier 18 electrically couples each of nodes N1 and N2 and an input node to supply a data read current. For example, by setting one electrode on the + side to a high potential and the other electrode on the − side to a low potential, a data read current corresponding to the resistance value Rmax or Rmin is supplied to the memory cell selected via the access transistor ATR. The The data read current flowing through the selected selected memory cell is compared with a reference current, for example, a data read current corresponding to a resistance value Rmid intermediate between Rmax and Rmin, to thereby determine the data read current. Read data is transmitted to the buffer 16 based on the comparison result. Buffer 16 operates in response to row address RA0 at "H" level, and buffers read data from sense amplifier 18 and outputs it as read data DRx.

  Sense amplifier 19 electrically couples each of nodes N0 and N1 and an input node, and transmits read data to buffer 17 based on the data read current, similarly to sense amplifier 18. The buffer 17 operates in response to the row address RA0 being at “L” level, and buffers the read data from the sense amplifier 19 and outputs it as read data DRx.

  Specifically, as described above, the switch unit SDCUx selects one of two accessible memory cell units, and among the three bit lines corresponding to the selected memory cell unit. Are connected to nodes N0, N1, and N2, respectively.

  When data reading is executed, node N1, which is a common node of sense amplifiers 18 and 19, is set to a predetermined voltage level (“H” level). Nodes N0 and N2 are set to the level of ground voltage GND ("L" level). Then, a data read current is supplied to each of the two memory cells constituting the memory cell unit. Specifically, the data read current corresponding to the resistance value of tunneling magneto-resistance element TMR is supplied from the second bit line to the first bit line via access transistor ATR. Further, a data read current corresponding to the resistance value of tunneling magneto-resistance element TMR is supplied from the second bit line to the third bit line via access transistor ATR.

  Sense amplifiers 18 and 19 detect a data read current corresponding to the resistance value of tunneling magneto-resistance element TMR flowing in nodes N2 and N0, amplify the data compared with a reference current, and read data corresponding to each buffer. 16 and 17 are output.

  As described above, one of the buffers 16 and 17 is selected in response to the row address RA0, and when the row address RA0 is at "H" level, the second bit line corresponding to the memory cell unit and 3 Read data DRx of a memory cell sandwiched between the second bit line is output. On the other hand, when row address RA0 is at "L" level, read data DRx of a memory cell sandwiched between the first bit line and the third bit line corresponding to the memory cell unit is output. The above-described data reading method is an example, and is not particularly limited as long as it is a configuration capable of supplying a data reading current to a selected memory cell and detecting it. It is naturally possible to adopt a configuration in which, for example, a voltage generated based on the data read current is compared with the reference voltage, instead of executing a current comparison in which the data read current is compared with the reference current.

  In the memory array of the present configuration, any one of the column blocks CBL0 to CBL3 is selected by the column decoder section CLDC to which the 2-bit column addresses CA0 and CA1 are input. Each column block CBL is divided into 32 block areas BU, and one word line WL is selected based on the output result of the predecoder PDC to which the row address RA2-RA10 is input. In each block area BU, two memory cell units corresponding to the selected word line WL are selected, and one of the two memory cell units is selected by the sub-decoder SDC to which the row address RA1 is input. Is done. The data read unit RDCx provided corresponding to each block region BU responds to the input row address RA0 and is one of the tunnel magnetoresistive elements of the two memory cells constituting the selected memory cell unit. Read data DRx corresponding to the resistance value of TMR is output. Since the column block CBL is composed of 32 block areas BU as a whole, it is possible to execute 32-bit parallel data reading by executing 1-bit data reading in each block area BU. .

  With this configuration, in the case of the configuration of the conventional memory array in which the source line SL and the bit line BL are crossed as described above, for example, 256K bits of 32-bit parallel data writing or data In order to be able to execute reading, it was necessary to configure 32 memory arrays of 8K bits. However, with this configuration, 32-bit parallel data writing or data Since reading can be executed, the layout area of the decoder for selecting memory cells provided as peripheral circuits of the memory array can be reduced, and the chip area as a whole can be greatly reduced.

(Modification of Embodiment 4)
In the fourth embodiment, the decoder capable of executing 32-bit parallel data writing or data reading has been described. However, in the modification of the fourth embodiment of the present invention, a simple decoder is used. A method for further reducing the layout area by reducing the circuit scale of the decoder will be described.

  FIG. 23 illustrates a peripheral circuit of the memory array according to the modification of the fourth embodiment of the present invention.

  Referring to FIG. 23, the difference from the configuration described in FIG. 18 is that predecoder PDC is replaced with predecoder PDC #, and AND circuit AD is replaced with AND circuit AD #. Since the other points are the same, detailed description thereof will not be repeated.

  FIG. 24 is a schematic block diagram of predecoder PDC # forming part of the decoder according to the modification of the fourth embodiment of the present invention.

  FIG. 24A shows a decoder unit DEC8a that receives and inputs the row addresses RA2-RA7.

  FIG. 24B shows a decoder unit DEC8b that receives and inputs the row addresses RA8-RA10.

  In the predecoder PDC described with reference to FIG. 19, the predecoder PDC that predecodes the input row address RA and generates a predecode signal indicating the quotient and remainder divided by 7 has been described. The predecoder PDC # according to the modification of the fourth embodiment uses only a predecoded signal.

  FIG. 25 is a circuit configuration diagram of decoder units DEC8a and DEC8b according to the modification of the fourth embodiment of the present invention.

  FIG. 25A is a circuit configuration diagram of the decoder unit DEC8a. The decoder unit DEC8a is composed of three units that predecode the row address RA of 2 bits each. Specifically, the row addresses RA2 and RA3 are predecoded and, for example, an “H” level signal is output from one of the output terminals Q0 to Q3. The remaining output terminals Q are at “L” level. Similarly, row addresses RA4 and RA5 are predecoded and, for example, an “H” level signal is output from one of output terminals Q4-Q7. The remaining output terminals Q are at “L” level. Further, the row addresses RA6 and RA7 are predecoded and a signal of, for example, “H” level is output from one output terminal Q of the output terminals Q8 to Q11. The remaining output terminals Q are at “L” level.

  FIG. 25B is a circuit configuration diagram of the decoder unit DEC8b. Decoder unit DEC8b predecodes 3-bit row addresses RA8-RA10 and outputs, for example, an "H" level signal from one of output terminals R0-R7. The remaining output terminals R are at the “L” level.

  Based on the combination of the predecode signals output from the output terminals Q0 to Q11, one of the word line groups divided into a plurality of groups is selected with the seven word lines as one group as described above. . In FIG. 23, the signal lines connected to the output terminals Q8 to Q11, the signal lines connected to the output terminals Q4 to Q7, and the signal lines connected to the output terminals Q0 to Q3, respectively, An AND circuit AD # that selects one of word line groups divided into a plurality of groups is shown as an example. The seven word lines included in the word line group selected by the word driver WDV based on the combination of the output result from the AND circuit AD # and the signal lines connected to the output terminals R0 to R6. One word line of WL is selected.

  Thus, 32-bit parallel data writing or data reading can be executed on the memory array in accordance with the above-described method.

  Then, by using the predecoder PDC # described with reference to FIGS. 24 and 25, a simpler circuit configuration can be realized than the predecoder PDC described with reference to FIGS. The layout area occupied by # can be reduced, and the entire chip can be further reduced.

  Note that the output terminal R7 of the decoder unit DEC8b is not connected to the signal line. That is, the decoder unit DEC8b invalidates the address selection corresponding to the row address RA8-RA10 from which the "H" level signal is output from the output terminal R7 as a result of the row address RA8-RA10 being input and predecoded.

  Therefore, since the address selection according to one combination of the input of the row addresses RA8 to RA10 is invalidated, the memory array as a whole cannot access the 1 / 8th memory array.

  FIG. 26 illustrates a region of the memory array accessible by the decoder according to the fourth embodiment of the present invention.

  For example, when a storage area of 32 Kbytes is provided for the entire memory array, access is invalid for 4 Kbytes, which is one-eighth, but the remaining 28 Kbytes are valid.

  Therefore, in devices that can limit the storage area, by adopting this method, priority is given to the simplification of the layout area and circuit configuration, realizing a chip with a reduced layout area as well as a reduced number of components. Is possible.

(Embodiment 5)
In the above embodiment, the configuration of an MRAM memory cell having a spin injection tunneling magneto-resistance element TMR has been described as a memory cell mainly having a resistor memory element. The same applies to the MRAM memory cell. Further, the resistor memory element is not limited to the tunnel magnetoresistive element, and other elements can naturally be used. For example, an OUM cell having a chalcogenide layer can be used.

  FIG. 27 is a plan view showing a part of a memory cell array composed of OUM cells.

  Referring to FIG. 27, memory cell 300 having chalcogenide layer 310 is arranged corresponding to the intersection of word lines WL and bit lines BL arranged in a matrix.

28 is a cross-sectional view taken along the line PQ in FIG.
Referring to FIG. 28, switching transistor 220 has an n-type region 222 formed on p-type region 221 and a p-type region 223 formed in n-type region 222. The switching transistor 220 is formed of a pnp-type vertical parasitic bipolar transistor having a p-type region 221, an n-type region 222, and a p-type region 223.

  The n-type region 222 corresponds to the word line WL. A heating element 230 that generates heat due to the passing current is provided between the chalcogenide layer 210 and the switching transistor 220. At the time of data writing, switching transistor 222 is turned on, and a data write current that passes through chalcogenide layer 210 and heating element 230 flows from bit line BL. Depending on the supply pattern of the data write current (for example, supply period and supply current amount), chalcogenide layer 210 changes in phase to either a crystalline state or an amorphous state. The chalcogenide layer 210 has different electrical resistances in each of an amorphous state and a crystalline state. Specifically, an amorphous chalcogenide layer has a higher electrical resistance than that during crystallization.

  That is, the OUM cell has one of the electrical resistances Rmax and Rmin depending on the stored data, like the MRAM memory cell.

  Therefore, it is naturally possible to use an OUM cell in place of the MRAM memory cell.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a schematic block diagram showing an overall configuration of an MRAM device 1 shown as a representative example of a nonvolatile memory device according to a first embodiment of the present invention. FIG. 4 is a conceptual diagram illustrating memory cell MC according to the first embodiment of the present invention. FIG. 7 is a diagram illustrating data writing in memory cell MC according to the first embodiment of the present invention. FIG. 6 is a diagram illustrating reversal of the magnetization direction of memory cell MC according to the first embodiment of the present invention. It is a diagram illustrating a layout configuration of a memory cell according to the first embodiment of the present invention. FIG. 6 is a diagram illustrating a cross-sectional structure of a memory cell of KP-KP # in the layout configuration of the memory array of FIG. 5. FIG. 3 is a circuit configuration diagram of a memory cell in the memory array according to the first embodiment of the present invention. FIG. 11 is a diagram illustrating a layout configuration of a memory cell according to a second embodiment of the present invention. FIG. 9 is a diagram illustrating a cross-sectional structure of a memory cell in the layout configuration of the memory array of FIG. 8. FIG. 7 is a circuit configuration diagram of a memory cell of a memory array according to a second embodiment of the present invention. It is a figure explaining the layout structure of the memory cell according to the modification of Embodiment 2 of this invention. FIG. 12 is a diagram illustrating a cross-sectional structure of a memory cell in the layout configuration of the memory array of FIG. 11. FIG. 11 is a circuit configuration diagram of a memory cell of a memory array according to a modification of the second embodiment of the present invention. It is a figure explaining the layout structure of the memory cell according to Embodiment 3 of this invention. FIG. 10 is a circuit configuration diagram of a memory cell of a memory array according to a third embodiment of the present invention. It is a figure explaining the layout structure of the memory cell according to the modification of Embodiment 3 of this invention. FIG. 11 is a circuit configuration diagram of a memory cell of a memory array according to a modification of the third embodiment of the present invention. It is a figure explaining the peripheral circuit of the memory array according to Embodiment 4 of this invention. It is a schematic block diagram of predecoder PDC according to Embodiment 4 of the present invention. It is a circuit block diagram of predecoder unit PDEC7a included in decoder unit DEC7a according to the fourth embodiment of the present invention. FIG. 6 is a circuit configuration diagram of a division circuit that outputs a quotient and a remainder divided by 7 in response to input of 32 predecode signals from the predecoder unit PDEC7a. It is a circuit block diagram of decoder unit DEC7b according to the fourth embodiment of the present invention. It is a figure explaining the peripheral circuit of the memory array according to the modification of Embodiment 4 of this invention. It is a schematic block diagram of predecoder PDC # which constitutes a part of a decoder according to a modification of the fourth embodiment of the present invention. It is a circuit block diagram of decoder units DEC8a and DEC8b according to the modification of Embodiment 4 of this invention. It is a figure explaining the area | region of the memory array accessible by the decoder according to Embodiment 4 of this invention. It is a top view which shows a part of memory cell array comprised by the OUM cell. It is PQ sectional drawing in FIG. It is a diagram illustrating a layout of a conventional memory array in which a source line SL and a bit line BL of a memory cell intersect. FIG. 30 is a circuit configuration diagram of the conventional memory array shown in FIG. 29. It is a schematic block diagram illustrating a layout of a decoder for selecting a memory cell provided corresponding to a memory array. It is a diagram illustrating a layout of a conventional memory array when source lines SL and bit lines BL of memory cells are provided in parallel along the Y-axis direction. FIG. 33 is a circuit configuration diagram of the conventional memory array shown in FIG. 32.

Explanation of symbols

  1 MRAM device, 5 control circuit, 10 memory array, 20 row decoder, 25 column decoder, 30 input / output control circuit.

Claims (21)

A plurality of memory cells integrated and arranged in a matrix;
A plurality of word lines provided corresponding to the memory cell rows,
A plurality of first current lines respectively provided corresponding to the memory cell columns;
A plurality of second current lines provided respectively corresponding to two memory cell columns adjacent to each other, each provided between the first current lines;
Each of the memory cells
A resistive storage element that performs non-volatile data storage in response to a passing current passing through the element;
A switch element for forming a current path via the magnetoresistive element between the corresponding first and second current lines in response to activation of the corresponding word line;
The memory cells in each of the two memory cell columns are adjacent memory cell rows and are electrically coupled to the corresponding second current line by forming a set with the memory cells in the adjacent memory cell column. A non-volatile memory device including a common contact portion.   The nonvolatile memory device according to claim 1, wherein the plurality of word lines are provided in a direction substantially orthogonal to the plurality of first and second current lines. The resistor memory element is
A fixed magnetization layer electrically coupled to the corresponding first current line and magnetized in a first magnetization direction;
Based on spin-polarized electrons that are electrically coupled to the corresponding second current lines and that pass through the corresponding first and second current lines during data writing and that correspond to the inflow direction of the passing current A free magnetic layer that is magnetized in one of a first magnetization direction or a second magnetization direction that is opposite to the first magnetization direction;
The nonvolatile memory device according to claim 1, further comprising a barrier layer that is provided between the fixed magnetization layer and the free magnetization layer and is a nonmagnetic material. The resistor memory element is
A heating element that generates heat by a data write current supplied according to the level of stored data for performing data storage;
The nonvolatile memory device according to claim 1, further comprising: a phase change element that is heated by the heating element and is capable of transitioning between two phase states having different electric resistances. The plurality of word lines each include a plurality of first and second word lines provided corresponding to the memory cell rows,
The switch element of each memory cell forms a MOS transistor,
A gate of a MOS transistor of a memory cell corresponding to an odd column of the plurality of memory cells is electrically coupled to a corresponding first word line;
2. The nonvolatile memory device according to claim 1, wherein a gate of a MOS transistor of a memory cell corresponding to an even column of the plurality of memory cells is electrically coupled to a corresponding second word line.   The nonvolatile memory device according to claim 1, wherein each memory cell in the same memory cell column is electrically coupled to the corresponding first and second current lines through different contacts. A plurality of memory cells integrated and arranged in a matrix;
A plurality of word lines provided corresponding to the memory cell rows,
Each including a plurality of first and second current lines respectively provided corresponding to two memory cell columns adjacent to each other;
Each of the memory cells
A resistive storage element that performs non-volatile data storage in response to a passing current passing through the element;
A switching element for forming a current path through the magnetoresistive element between the corresponding first and second current lines in response to activation of the corresponding word line,
Two memory cells adjacent to each other in one memory cell column of the two memory cell columns are commonly used to electrically couple with a second current line corresponding to the other memory cell column. A first contact portion of
Two memory cells adjacent to each other in the other memory cell column of the two memory cell columns are commonly used to electrically couple with a first current line corresponding to one memory cell column. A non-volatile memory device further including the second contact portion. The switch element of each memory cell forms a MOS transistor,
The nonvolatile memory device according to claim 7, wherein each MOS transistor of each memory cell in the same column is formed in a common active region. The plurality of word lines each include a plurality of first and second word lines provided corresponding to the memory cell rows,
The switch element of each memory cell forms a MOS transistor,
The gate of the MOS transistor of one memory cell of two adjacent memory cells in the same row is electrically coupled to the corresponding first word line, and the gate of the MOS transistor of the other memory cell is the corresponding first The nonvolatile memory device according to claim 7, wherein the nonvolatile memory device is electrically coupled to two word lines. Each of the plurality of first and second word lines is alternately provided,
A common first contact portion corresponding to two adjacent memory cells in one of the two memory cell columns and two adjacent ones in the other memory cell column 10. The nonvolatile memory device according to claim 9, wherein a common second contact portion of the memory cells is alternately provided between the plurality of first and second word lines. Each of the first and second current lines is formed using a first metal wiring layer,
The common second and first contact portions of the two adjacent memory cells respectively coupled to the corresponding first and second current lines are lower than the first metal wiring layer. The nonvolatile memory device according to claim 7, wherein the nonvolatile memory device is formed using two metal wiring layers. Each of the first current lines is provided corresponding to an odd number of memory cell columns,
Each of the second current lines is provided corresponding to an even number of memory cell columns,
Each of the odd columns of memory cells is electrically coupled to a corresponding second current line through the common first contact;
The nonvolatile memory device according to claim 7, wherein each of the even-numbered memory cells is electrically coupled to a corresponding first current line via the common second contact. A plurality of memory cells integrated and arranged in a matrix according to a predetermined rule;
A plurality of word lines provided corresponding to the memory cell rows,
A plurality of current lines provided corresponding to the memory cell columns,
Each of the memory cells
A resistive storage element that performs non-volatile data storage in response to a passing current passing through the element;
A switching element for forming a current path via the magnetoresistive element between the corresponding current line and another adjacent current line in response to activation of the corresponding word line,
Four memory cells adjacent to each other in the memory cell column constitute a first and second memory cell set including two memory cells adjacent to each other.
Two adjacent memory cells constituting the same row as the first memory cell set in the two adjacent memory cell columns on one side of the memory cell column constitute a third memory cell set,
Two adjacent memory cells constituting the same row as the second memory cell set of the two adjacent memory cell columns on the other side of the memory cell column constitute a fourth memory cell set,
Each memory cell of the first and third memory cell sets includes an adjacent current line corresponding to a memory cell column between the current line corresponding to the memory cell column and the two adjacent memory cell columns on the one side. And a common first contact portion for electrically coupling
Each memory cell of the second and fourth memory cell sets includes an adjacent current line corresponding to a memory cell column between the current line corresponding to the memory cell column and the second adjacent memory cell column on the other side. And a non-volatile memory device having a common second contact portion for electrically coupling the two.   14. The nonvolatile memory according to claim 13, wherein the common first and second contact portions have a common strap for electrically coupling a corresponding switch element of each corresponding memory cell and the adjacent current line. Sex memory device. Each of the current lines is formed using a first metal wiring layer,
The nonvolatile memory device according to claim 14, wherein the common strap is formed by using a second metal wiring layer that is lower than the first metal wiring layer. A selection circuit for selecting a plurality of word lines;
The plurality of word lines are divided into a plurality of groups of seven adjacent to each other,
The selection circuit selects one group divided into the plurality of groups based on a quotient obtained by dividing an address input in binary number by 7, and corresponds to one group selected based on a remainder. The nonvolatile memory device according to claim 13, wherein one of the word lines is selected. A word line selection circuit for selecting one of the plurality of word lines according to an input address;
The plurality of word lines are divided into a plurality of groups of seven adjacent to each other,
The selection circuit selects one group divided into the plurality of groups based on a quotient obtained by dividing an address input in binary number by 7, and corresponds to one group selected based on a remainder. The nonvolatile memory device according to claim 13, wherein one of the word lines is selected. A bit line selection circuit for selecting three adjacent bit lines among the plurality of current lines according to an input address;
In response to activation of a selected word line corresponding to the selected memory cell, at least two memory cells in the same row in one of the first and third memory cell sets and the second and fourth memory cell sets are accessed. The selected three bit lines are electrically coupled to each other through the two memory cells,
The nonvolatile memory device according to claim 13, further comprising a data write circuit for setting voltage levels of three bit lines selected by the bit line selection circuit according to write data. A bit line selection circuit for selecting three adjacent bit lines among the plurality of current lines according to an input address;
In response to activation of a selected word line corresponding to the selected memory cell, at least two memory cells in the same row in one of the first and third memory cell sets and the second and fourth memory cell sets are accessed. The selected three bit lines are electrically coupled to each other through the two memory cells,
A data read circuit is further provided for generating read data based on data read currents flowing through two bit lines adjacent to each other via the resistor memory element of the selected memory cell among the selected three bit lines. The nonvolatile memory device according to claim 13. A word line selection circuit for selecting one of the plurality of word lines according to an input address;
The plurality of word lines are divided into a plurality of groups of seven adjacent to each other,
The selection circuit selects one group divided into the plurality of groups based on a quotient obtained by dividing an address input in binary number by 7, and corresponds to one group selected based on a remainder. Select one of the word lines,
A bit line selection circuit for selecting three of the plurality of bit lines according to an input address;
The nonvolatile memory device according to claim 13, wherein the bit line selection circuit selects the three bit lines based on a remainder obtained by dividing the binary input address by seven. A word line selection circuit for selecting one of the plurality of word lines according to an input address;
The plurality of word lines are divided into a plurality of groups of seven adjacent to each other,
The word line selection circuit selects one group of the plurality of groups by using the remaining bits excluding 3 bits of the address inputted in binary number, and corresponds to each combination of the 3-bit addresses. 14. One of the eight decode signals is activated, and one of the seven word lines corresponding to each of the seven decode signals of the eight decode signals is selected. The non-volatile storage device described.

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