SG11201705246UA - Metal layers for a three-port bit cell - Google Patents
Metal layers for a three-port bit cellInfo
- Publication number
- SG11201705246UA SG11201705246UA SG11201705246UA SG11201705246UA SG11201705246UA SG 11201705246U A SG11201705246U A SG 11201705246UA SG 11201705246U A SG11201705246U A SG 11201705246UA SG 11201705246U A SG11201705246U A SG 11201705246UA SG 11201705246U A SG11201705246U A SG 11201705246UA
- Authority
- SG
- Singapore
- Prior art keywords
- metal layers
- bit cell
- port bit
- port
- cell
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/418—Address circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/14—Word line organisation; Word line lay-out
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/10—Integrated device layouts
-
- H10P50/00—
-
- H10W20/069—
-
- H10W20/42—
-
- H10W20/43—
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Manufacturing & Machinery (AREA)
- General Engineering & Computer Science (AREA)
- Geometry (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/620,480 US9524972B2 (en) | 2015-02-12 | 2015-02-12 | Metal layers for a three-port bit cell |
| PCT/US2015/062644 WO2016130194A1 (en) | 2015-02-12 | 2015-11-25 | Metal layers for a three-port bit cell |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| SG11201705246UA true SG11201705246UA (en) | 2017-09-28 |
Family
ID=54834961
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SG11201705246UA SG11201705246UA (en) | 2015-02-12 | 2015-11-25 | Metal layers for a three-port bit cell |
Country Status (8)
| Country | Link |
|---|---|
| US (3) | US9524972B2 (enExample) |
| EP (1) | EP3257080B1 (enExample) |
| JP (1) | JP6884103B2 (enExample) |
| KR (2) | KR102504733B1 (enExample) |
| CN (1) | CN107210295B (enExample) |
| BR (1) | BR112017017345B1 (enExample) |
| SG (1) | SG11201705246UA (enExample) |
| WO (1) | WO2016130194A1 (enExample) |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9524972B2 (en) | 2015-02-12 | 2016-12-20 | Qualcomm Incorporated | Metal layers for a three-port bit cell |
| US9793211B2 (en) | 2015-10-20 | 2017-10-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dual power structure with connection pins |
| US10740531B2 (en) | 2016-11-29 | 2020-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit, system for and method of forming an integrated circuit |
| US10002786B1 (en) | 2016-12-15 | 2018-06-19 | Globalfoundries Inc. | Interconnection cells having variable width metal lines and fully-self aligned variable length continuity cuts |
| US10043703B2 (en) * | 2016-12-15 | 2018-08-07 | Globalfoundries Inc. | Apparatus and method for forming interconnection lines having variable pitch and variable widths |
| US9887127B1 (en) | 2016-12-15 | 2018-02-06 | Globalfoundries Inc. | Interconnection lines having variable widths and partially self-aligned continuity cuts |
| US9978682B1 (en) * | 2017-04-13 | 2018-05-22 | Qualcomm Incorporated | Complementary metal oxide semiconductor (CMOS) standard cell circuits employing metal lines in a first metal layer used for routing, and related methods |
| CN109427388B (zh) | 2017-09-04 | 2020-09-25 | 华为技术有限公司 | 一种存储单元和静态随机存储器 |
| US10410714B2 (en) * | 2017-09-20 | 2019-09-10 | Qualcomm Incorporated | Multi-level cell (MLC) static random access memory (SRAM) (MLC SRAM) cells configured to perform multiplication operations |
| CN111554336A (zh) * | 2019-02-12 | 2020-08-18 | 联华电子股份有限公司 | 静态随机存取存储器单元 |
| US11302388B2 (en) | 2020-08-25 | 2022-04-12 | Qualcomm Incorporated | Decoding for pseudo-triple-port SRAM |
| US11398274B2 (en) | 2020-08-25 | 2022-07-26 | Qualcomm Incorporated | Pseudo-triple-port SRAM |
| US11361817B2 (en) | 2020-08-25 | 2022-06-14 | Qualcomm Incorporated | Pseudo-triple-port SRAM bitcell architecture |
| US11910587B2 (en) * | 2021-02-26 | 2024-02-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory circuit having SRAM memory cells and method for forming a SRAM memory cell structure |
| US11955169B2 (en) | 2021-03-23 | 2024-04-09 | Qualcomm Incorporated | High-speed multi-port memory supporting collision |
| US20240389292A1 (en) * | 2023-05-16 | 2024-11-21 | Qualcomm Incorporated | Fly bitline design for pseudo triple port memory |
Family Cites Families (35)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3357382B2 (ja) * | 1991-05-28 | 2002-12-16 | 株式会社日立製作所 | 多ポートメモリ |
| JP4885365B2 (ja) | 2000-05-16 | 2012-02-29 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| JP4171201B2 (ja) | 2001-10-23 | 2008-10-22 | 松下電器産業株式会社 | 半導体記憶装置 |
| KR100526884B1 (ko) * | 2003-08-25 | 2005-11-09 | 삼성전자주식회사 | 듀얼 포트 에스램의 레이아웃 구조 및 그에 따른 형성방법 |
| JP2005175415A (ja) | 2003-12-05 | 2005-06-30 | Taiwan Semiconductor Manufacturing Co Ltd | 集積回路デバイスとその製造方法 |
| SG115742A1 (en) * | 2004-04-05 | 2005-10-28 | Taiwan Semiconductor Mfg | Sram device having high aspect ratio cell boundary |
| JP2006310467A (ja) * | 2005-04-27 | 2006-11-09 | Renesas Technology Corp | 半導体記憶装置 |
| US7324382B2 (en) * | 2006-05-31 | 2008-01-29 | Grace Semiconductor Manufacturing Corporation | Current-mode sensing structure used in high-density multiple-port register in logic processing and method for the same |
| US7525868B2 (en) * | 2006-11-29 | 2009-04-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multiple-port SRAM device |
| JP5078338B2 (ja) | 2006-12-12 | 2012-11-21 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
| US20080291767A1 (en) * | 2007-05-21 | 2008-11-27 | International Business Machines Corporation | Multiple wafer level multiple port register file cell |
| JP2009043304A (ja) * | 2007-08-06 | 2009-02-26 | Renesas Technology Corp | 半導体装置 |
| JP2009238332A (ja) * | 2008-03-27 | 2009-10-15 | Renesas Technology Corp | 半導体記憶装置 |
| JP2009260083A (ja) * | 2008-04-17 | 2009-11-05 | Renesas Technology Corp | 半導体記憶装置 |
| JP5231924B2 (ja) * | 2008-10-03 | 2013-07-10 | 株式会社東芝 | 半導体記憶装置 |
| US8675397B2 (en) * | 2010-06-25 | 2014-03-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cell structure for dual-port SRAM |
| JP5503480B2 (ja) * | 2010-09-29 | 2014-05-28 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| JP5165040B2 (ja) | 2010-10-15 | 2013-03-21 | ルネサスエレクトロニクス株式会社 | 半導体集積回路 |
| CN102385908A (zh) | 2011-09-06 | 2012-03-21 | 复旦大学 | 一种多端口寄存器堆存储单元及其布局布线方法 |
| US20130083591A1 (en) | 2011-09-29 | 2013-04-04 | John J. Wuu | Alternating Wordline Connection in 8T Cells for Improving Resiliency to Multi-Bit SER Upsets |
| US8437166B1 (en) * | 2011-11-16 | 2013-05-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Word line driver cell layout for SRAM and other semiconductor devices |
| US9831345B2 (en) * | 2013-03-11 | 2017-11-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET with rounded source/drain profile |
| US9026973B2 (en) * | 2013-03-14 | 2015-05-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | System and method for arbitrary metal spacing for self-aligned double patterning |
| JPWO2015019411A1 (ja) * | 2013-08-06 | 2017-03-02 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置 |
| US9281311B2 (en) * | 2013-09-19 | 2016-03-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory cell array including a write-assist circuit and embedded coupling capacitor and method of forming same |
| US9202557B2 (en) * | 2013-09-23 | 2015-12-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Three-dimensional two-port bit cell |
| US8929130B1 (en) * | 2013-11-12 | 2015-01-06 | Taiwan Semiconductor Manufacturing Company Limited | Two-port SRAM cell structure |
| US9208854B2 (en) * | 2013-12-06 | 2015-12-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Three dimensional dual-port bit cell and method of assembling same |
| US9312185B2 (en) * | 2014-05-06 | 2016-04-12 | International Business Machines Corporation | Formation of metal resistor and e-fuse |
| US9412742B2 (en) * | 2014-06-10 | 2016-08-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Layout design for manufacturing a memory cell |
| US9536596B2 (en) * | 2014-08-26 | 2017-01-03 | Qualcomm Incorporated | Three-port bit cell having increased width |
| US9455026B2 (en) * | 2014-11-18 | 2016-09-27 | Qualcomm Incorporated | Shared global read and write word lines |
| US9876017B2 (en) * | 2014-12-03 | 2018-01-23 | Qualcomm Incorporated | Static random access memory (SRAM) bit cells with wordline landing pads split across boundary edges of the SRAM bit cells |
| US9368443B1 (en) * | 2015-01-20 | 2016-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory metal scheme |
| US9524972B2 (en) | 2015-02-12 | 2016-12-20 | Qualcomm Incorporated | Metal layers for a three-port bit cell |
-
2015
- 2015-02-12 US US14/620,480 patent/US9524972B2/en active Active
- 2015-11-25 JP JP2017541025A patent/JP6884103B2/ja active Active
- 2015-11-25 BR BR112017017345-0A patent/BR112017017345B1/pt active IP Right Grant
- 2015-11-25 WO PCT/US2015/062644 patent/WO2016130194A1/en not_active Ceased
- 2015-11-25 KR KR1020177021683A patent/KR102504733B1/ko active Active
- 2015-11-25 SG SG11201705246UA patent/SG11201705246UA/en unknown
- 2015-11-25 EP EP15805719.0A patent/EP3257080B1/en active Active
- 2015-11-25 CN CN201580075694.8A patent/CN107210295B/zh active Active
- 2015-11-25 KR KR1020227018296A patent/KR20220076545A/ko not_active Ceased
-
2016
- 2016-11-09 US US15/347,530 patent/US10141317B2/en not_active Expired - Fee Related
-
2018
- 2018-10-03 US US16/150,637 patent/US20190035796A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| HK1244354A1 (zh) | 2018-08-03 |
| CN107210295B (zh) | 2020-11-20 |
| US10141317B2 (en) | 2018-11-27 |
| BR112017017345B1 (pt) | 2022-12-06 |
| EP3257080B1 (en) | 2023-08-02 |
| US20170062439A1 (en) | 2017-03-02 |
| JP2018508991A (ja) | 2018-03-29 |
| CN107210295A (zh) | 2017-09-26 |
| WO2016130194A1 (en) | 2016-08-18 |
| KR102504733B1 (ko) | 2023-02-27 |
| KR20170116021A (ko) | 2017-10-18 |
| EP3257080C0 (en) | 2023-08-02 |
| KR20220076545A (ko) | 2022-06-08 |
| EP3257080A1 (en) | 2017-12-20 |
| US9524972B2 (en) | 2016-12-20 |
| BR112017017345A2 (pt) | 2018-04-10 |
| JP6884103B2 (ja) | 2021-06-09 |
| US20160240539A1 (en) | 2016-08-18 |
| US20190035796A1 (en) | 2019-01-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| SG11201705246UA (en) | Metal layers for a three-port bit cell | |
| GB201621478D0 (en) | One hand replace battery design method | |
| GB201813622D0 (en) | Method providing for a storage element | |
| PL3054042T5 (pl) | Sposób wytwarzania laminatu i laminat | |
| EP3198645A4 (en) | 1s1r memory cells incorporating a barrier layer | |
| GB201513582D0 (en) | A nickle-based alloy | |
| AU201613397S (en) | A headphone | |
| GB201715554D0 (en) | Bit incorporating ductile inserts | |
| SG10201510521UA (en) | Method for predicting a demand for a business | |
| GB201507418D0 (en) | A tool for forming a composite component | |
| GB2555033B (en) | A lithium-sulphur cell | |
| GB2532355B (en) | A Hydraulic accumulator | |
| GB201514139D0 (en) | A datum feature for a composite component | |
| GB201512961D0 (en) | Pipe beveling tool | |
| GB201500813D0 (en) | A pack | |
| PL3271626T3 (pl) | Zawór | |
| GB2547330B (en) | Storage arrangement for well operations | |
| GB2540395B (en) | A tool for a pipe | |
| GB201421169D0 (en) | Hydraulic fitting and method for manufacturing such a fitting | |
| GB201500812D0 (en) | A pack | |
| GB2540392B (en) | A tool for a pipe | |
| GB2540393B (en) | A tool for a pipe | |
| GB2539057B (en) | A valve | |
| GB201519988D0 (en) | Method for manufacturing a design object | |
| GB201507415D0 (en) | A Tool For Manufacturing A Composite Component |