JP6884103B2 - ３ポートのビットセルのための金属層 - Google Patents

３ポートのビットセルのための金属層 Download PDF

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JP6884103B2
JP6884103B2 JP2017541025A JP2017541025A JP6884103B2 JP 6884103 B2 JP6884103 B2 JP 6884103B2 JP 2017541025 A JP2017541025 A JP 2017541025A JP 2017541025 A JP2017541025 A JP 2017541025A JP 6884103 B2 JP6884103 B2 JP 6884103B2
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metal layer
bit cell
word line
read
length
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Japanese (ja)
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JP2018508991A5 (enExample
JP2018508991A (ja
Inventor
ニラドリ・ナラヤン・モジュムダー
リツ・チャバ
ピン・リュウ
スタンリー・スンチョル・ソン
ジョンゼ・ワン
チョ・フェイ・イェプ
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クアルコム，インコーポレイテッド
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/418—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H10P50/00—
    • H10W20/069—
    • H10W20/42—
    • H10W20/43—

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Manufacturing & Machinery (AREA)
  • General Engineering & Computer Science (AREA)
  • Geometry (AREA)
  • Static Random-Access Memory (AREA)
JP2017541025A 2015-02-12 2015-11-25 ３ポートのビットセルのための金属層 Active JP6884103B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/620,480 2015-02-12
US14/620,480 US9524972B2 (en) 2015-02-12 2015-02-12 Metal layers for a three-port bit cell
PCT/US2015/062644 WO2016130194A1 (en) 2015-02-12 2015-11-25 Metal layers for a three-port bit cell

Publications (3)

Publication Number Publication Date
JP2018508991A JP2018508991A (ja) 2018-03-29
JP2018508991A5 JP2018508991A5 (enExample) 2018-12-13
JP6884103B2 true JP6884103B2 (ja) 2021-06-09

Family

ID=54834961

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017541025A Active JP6884103B2 (ja) 2015-02-12 2015-11-25 ３ポートのビットセルのための金属層

Country Status (8)

Country Link
US (3) US9524972B2 (enExample)
EP (1) EP3257080B1 (enExample)
JP (1) JP6884103B2 (enExample)
KR (2) KR20220076545A (enExample)
CN (1) CN107210295B (enExample)
BR (1) BR112017017345B1 (enExample)
SG (1) SG11201705246UA (enExample)
WO (1) WO2016130194A1 (enExample)

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US9793211B2 (en) 2015-10-20 2017-10-17 Taiwan Semiconductor Manufacturing Co., Ltd. Dual power structure with connection pins
US10740531B2 (en) 2016-11-29 2020-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit, system for and method of forming an integrated circuit
US9887127B1 (en) 2016-12-15 2018-02-06 Globalfoundries Inc. Interconnection lines having variable widths and partially self-aligned continuity cuts
US10043703B2 (en) * 2016-12-15 2018-08-07 Globalfoundries Inc. Apparatus and method for forming interconnection lines having variable pitch and variable widths
US10002786B1 (en) 2016-12-15 2018-06-19 Globalfoundries Inc. Interconnection cells having variable width metal lines and fully-self aligned variable length continuity cuts
US9978682B1 (en) * 2017-04-13 2018-05-22 Qualcomm Incorporated Complementary metal oxide semiconductor (CMOS) standard cell circuits employing metal lines in a first metal layer used for routing, and related methods
CN112216323B (zh) * 2017-09-04 2024-06-14 华为技术有限公司 一种存储单元和静态随机存储器
US10410714B2 (en) * 2017-09-20 2019-09-10 Qualcomm Incorporated Multi-level cell (MLC) static random access memory (SRAM) (MLC SRAM) cells configured to perform multiplication operations
CN111554336A (zh) * 2019-02-12 2020-08-18 联华电子股份有限公司 静态随机存取存储器单元
US11302388B2 (en) 2020-08-25 2022-04-12 Qualcomm Incorporated Decoding for pseudo-triple-port SRAM
US11398274B2 (en) 2020-08-25 2022-07-26 Qualcomm Incorporated Pseudo-triple-port SRAM
US11361817B2 (en) 2020-08-25 2022-06-14 Qualcomm Incorporated Pseudo-triple-port SRAM bitcell architecture
US11910587B2 (en) * 2021-02-26 2024-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Memory circuit having SRAM memory cells and method for forming a SRAM memory cell structure
US11955169B2 (en) 2021-03-23 2024-04-09 Qualcomm Incorporated High-speed multi-port memory supporting collision
US20240389292A1 (en) * 2023-05-16 2024-11-21 Qualcomm Incorporated Fly bitline design for pseudo triple port memory

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US20080291767A1 (en) * 2007-05-21 2008-11-27 International Business Machines Corporation Multiple wafer level multiple port register file cell
JP2009043304A (ja) * 2007-08-06 2009-02-26 Renesas Technology Corp 半導体装置
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US9876017B2 (en) * 2014-12-03 2018-01-23 Qualcomm Incorporated Static random access memory (SRAM) bit cells with wordline landing pads split across boundary edges of the SRAM bit cells
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US9524972B2 (en) 2015-02-12 2016-12-20 Qualcomm Incorporated Metal layers for a three-port bit cell

Also Published As

Publication number Publication date
US20160240539A1 (en) 2016-08-18
US20170062439A1 (en) 2017-03-02
KR20220076545A (ko) 2022-06-08
US10141317B2 (en) 2018-11-27
EP3257080A1 (en) 2017-12-20
KR102504733B1 (ko) 2023-02-27
KR20170116021A (ko) 2017-10-18
HK1244354A1 (zh) 2018-08-03
US20190035796A1 (en) 2019-01-31
CN107210295B (zh) 2020-11-20
JP2018508991A (ja) 2018-03-29
BR112017017345B1 (pt) 2022-12-06
EP3257080C0 (en) 2023-08-02
US9524972B2 (en) 2016-12-20
WO2016130194A1 (en) 2016-08-18
CN107210295A (zh) 2017-09-26
EP3257080B1 (en) 2023-08-02
BR112017017345A2 (pt) 2018-04-10
SG11201705246UA (en) 2017-09-28

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