KR20220076545A - 3-포트 비트 셀을 위한 금속층들 - Google Patents

3-포트 비트 셀을 위한 금속층들 Download PDF

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Publication number
KR20220076545A
KR20220076545A KR1020227018296A KR20227018296A KR20220076545A KR 20220076545 A KR20220076545 A KR 20220076545A KR 1020227018296 A KR1020227018296 A KR 1020227018296A KR 20227018296 A KR20227018296 A KR 20227018296A KR 20220076545 A KR20220076545 A KR 20220076545A
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KR
South Korea
Prior art keywords
metal layer
bit cell
read
bit
write
Prior art date
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Ceased
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KR1020227018296A
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English (en)
Korean (ko)
Inventor
닐라드리 나라얀 모줌더
리투 차바
핑 리우
스탠리 승철 송
종제 왕
초 페이 옙
Original Assignee
퀄컴 인코포레이티드
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Publication of KR20220076545A publication Critical patent/KR20220076545A/ko
Ceased legal-status Critical Current

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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B10/00Static random access memory [SRAM] devices
    • H10B10/12Static random access memory [SRAM] devices comprising a MOSFET load element
    • H01L27/1104
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/418Address circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419Read-write [R-W] circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/14Word line organisation; Word line lay-out
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/16Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • H01L27/0207
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B10/00Static random access memory [SRAM] devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10Integrated device layouts
    • H10P50/00
    • H10W20/069
    • H10W20/42
    • H10W20/43

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Manufacturing & Machinery (AREA)
  • General Engineering & Computer Science (AREA)
  • Geometry (AREA)
  • Static Random-Access Memory (AREA)
KR1020227018296A 2015-02-12 2015-11-25 3-포트 비트 셀을 위한 금속층들 Ceased KR20220076545A (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US14/620,480 US9524972B2 (en) 2015-02-12 2015-02-12 Metal layers for a three-port bit cell
US14/620,480 2015-02-12
PCT/US2015/062644 WO2016130194A1 (en) 2015-02-12 2015-11-25 Metal layers for a three-port bit cell
KR1020177021683A KR102504733B1 (ko) 2015-02-12 2015-11-25 3-포트 비트 셀을 위한 금속층들

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
KR1020177021683A Division KR102504733B1 (ko) 2015-02-12 2015-11-25 3-포트 비트 셀을 위한 금속층들

Publications (1)

Publication Number Publication Date
KR20220076545A true KR20220076545A (ko) 2022-06-08

Family

ID=54834961

Family Applications (2)

Application Number Title Priority Date Filing Date
KR1020177021683A Active KR102504733B1 (ko) 2015-02-12 2015-11-25 3-포트 비트 셀을 위한 금속층들
KR1020227018296A Ceased KR20220076545A (ko) 2015-02-12 2015-11-25 3-포트 비트 셀을 위한 금속층들

Family Applications Before (1)

Application Number Title Priority Date Filing Date
KR1020177021683A Active KR102504733B1 (ko) 2015-02-12 2015-11-25 3-포트 비트 셀을 위한 금속층들

Country Status (8)

Country Link
US (3) US9524972B2 (enExample)
EP (1) EP3257080B1 (enExample)
JP (1) JP6884103B2 (enExample)
KR (2) KR102504733B1 (enExample)
CN (1) CN107210295B (enExample)
BR (1) BR112017017345B1 (enExample)
SG (1) SG11201705246UA (enExample)
WO (1) WO2016130194A1 (enExample)

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US9793211B2 (en) 2015-10-20 2017-10-17 Taiwan Semiconductor Manufacturing Co., Ltd. Dual power structure with connection pins
US10740531B2 (en) 2016-11-29 2020-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit, system for and method of forming an integrated circuit
US10002786B1 (en) 2016-12-15 2018-06-19 Globalfoundries Inc. Interconnection cells having variable width metal lines and fully-self aligned variable length continuity cuts
US10043703B2 (en) * 2016-12-15 2018-08-07 Globalfoundries Inc. Apparatus and method for forming interconnection lines having variable pitch and variable widths
US9887127B1 (en) 2016-12-15 2018-02-06 Globalfoundries Inc. Interconnection lines having variable widths and partially self-aligned continuity cuts
US9978682B1 (en) * 2017-04-13 2018-05-22 Qualcomm Incorporated Complementary metal oxide semiconductor (CMOS) standard cell circuits employing metal lines in a first metal layer used for routing, and related methods
CN109427388B (zh) 2017-09-04 2020-09-25 华为技术有限公司 一种存储单元和静态随机存储器
US10410714B2 (en) * 2017-09-20 2019-09-10 Qualcomm Incorporated Multi-level cell (MLC) static random access memory (SRAM) (MLC SRAM) cells configured to perform multiplication operations
CN111554336A (zh) * 2019-02-12 2020-08-18 联华电子股份有限公司 静态随机存取存储器单元
US11302388B2 (en) 2020-08-25 2022-04-12 Qualcomm Incorporated Decoding for pseudo-triple-port SRAM
US11398274B2 (en) 2020-08-25 2022-07-26 Qualcomm Incorporated Pseudo-triple-port SRAM
US11361817B2 (en) 2020-08-25 2022-06-14 Qualcomm Incorporated Pseudo-triple-port SRAM bitcell architecture
US11910587B2 (en) * 2021-02-26 2024-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Memory circuit having SRAM memory cells and method for forming a SRAM memory cell structure
US11955169B2 (en) 2021-03-23 2024-04-09 Qualcomm Incorporated High-speed multi-port memory supporting collision
US20240389292A1 (en) * 2023-05-16 2024-11-21 Qualcomm Incorporated Fly bitline design for pseudo triple port memory

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JP4171201B2 (ja) 2001-10-23 2008-10-22 松下電器産業株式会社 半導体記憶装置
KR100526884B1 (ko) * 2003-08-25 2005-11-09 삼성전자주식회사 듀얼 포트 에스램의 레이아웃 구조 및 그에 따른 형성방법
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JP2006310467A (ja) * 2005-04-27 2006-11-09 Renesas Technology Corp 半導体記憶装置
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JP2009043304A (ja) * 2007-08-06 2009-02-26 Renesas Technology Corp 半導体装置
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Also Published As

Publication number Publication date
HK1244354A1 (zh) 2018-08-03
CN107210295B (zh) 2020-11-20
US10141317B2 (en) 2018-11-27
BR112017017345B1 (pt) 2022-12-06
EP3257080B1 (en) 2023-08-02
US20170062439A1 (en) 2017-03-02
JP2018508991A (ja) 2018-03-29
CN107210295A (zh) 2017-09-26
WO2016130194A1 (en) 2016-08-18
KR102504733B1 (ko) 2023-02-27
SG11201705246UA (en) 2017-09-28
KR20170116021A (ko) 2017-10-18
EP3257080C0 (en) 2023-08-02
EP3257080A1 (en) 2017-12-20
US9524972B2 (en) 2016-12-20
BR112017017345A2 (pt) 2018-04-10
JP6884103B2 (ja) 2021-06-09
US20160240539A1 (en) 2016-08-18
US20190035796A1 (en) 2019-01-31

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