JP2019526170A5 - - Google Patents

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Publication number
JP2019526170A5
JP2019526170A5 JP2019500874A JP2019500874A JP2019526170A5 JP 2019526170 A5 JP2019526170 A5 JP 2019526170A5 JP 2019500874 A JP2019500874 A JP 2019500874A JP 2019500874 A JP2019500874 A JP 2019500874A JP 2019526170 A5 JP2019526170 A5 JP 2019526170A5
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JP
Japan
Prior art keywords
metal
cell
distance
integrated circuit
circuit structure
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Application number
JP2019500874A
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English (en)
Japanese (ja)
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JP7015824B2 (ja
JP2019526170A (ja
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Priority claimed from US15/207,691 external-priority patent/US9977854B2/en
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Publication of JP2019526170A publication Critical patent/JP2019526170A/ja
Publication of JP2019526170A5 publication Critical patent/JP2019526170A5/ja
Application granted granted Critical
Publication of JP7015824B2 publication Critical patent/JP7015824B2/ja
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JP2019500874A 2016-07-12 2017-07-10 セル境界外に延在する金属層セグメントを有する標準セルを実装する集積回路 Active JP7015824B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/207,691 2016-07-12
US15/207,691 US9977854B2 (en) 2016-07-12 2016-07-12 Integrated circuit implementing standard cells with metal layer segments extending out of cell boundary
PCT/US2017/041349 WO2018013472A1 (en) 2016-07-12 2017-07-10 Integrated circuit implementing standard cells with metal layer segments extending out of cell boundary

Publications (3)

Publication Number Publication Date
JP2019526170A JP2019526170A (ja) 2019-09-12
JP2019526170A5 true JP2019526170A5 (enExample) 2020-08-13
JP7015824B2 JP7015824B2 (ja) 2022-02-03

Family

ID=57890630

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2019500874A Active JP7015824B2 (ja) 2016-07-12 2017-07-10 セル境界外に延在する金属層セグメントを有する標準セルを実装する集積回路

Country Status (7)

Country Link
US (1) US9977854B2 (enExample)
EP (1) EP3270414A1 (enExample)
JP (1) JP7015824B2 (enExample)
KR (1) KR102294210B1 (enExample)
CN (1) CN109791930B (enExample)
TW (1) TWI732900B (enExample)
WO (1) WO2018013472A1 (enExample)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102458446B1 (ko) * 2016-03-03 2022-10-26 삼성전자주식회사 스탠다드 셀을 포함하는 반도체 장치 및 그것의 전자 설계 자동화 방법
US10691849B2 (en) * 2017-09-28 2020-06-23 Taiwan Semiconductor Manufacturing Co., Ltd. Metal cut optimization for standard cells
DE102018122541A1 (de) 2017-09-29 2019-04-04 Taiwan Semiconductor Manufacturing Co., Ltd. Stiftmodifizierung für standardzellen
US10559558B2 (en) * 2017-09-29 2020-02-11 Taiwan Semiconductor Manufacturing Co., Ltd. Pin modification for standard cells
TWI681309B (zh) * 2018-05-10 2020-01-01 瑞昱半導體股份有限公司 電子裝置測試資料庫產生方法
US10784869B2 (en) * 2018-07-16 2020-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit and method of manufacturing the same
DE102019125900B4 (de) 2018-09-28 2022-03-24 Taiwan Semiconductor Manufacturing Co., Ltd. Metallschnittgebiet-positionierungsverfahren und system
US10997348B2 (en) 2018-09-28 2021-05-04 Taiwan Semiconductor Manufacturing Company Ltd. Metal cut region location method and system
US10769342B2 (en) * 2018-10-31 2020-09-08 Taiwan Semiconductor Manufacturing Company Ltd. Pin access hybrid cell height design
KR102539066B1 (ko) * 2018-11-09 2023-06-01 삼성전자주식회사 서로 다른 타입의 셀들을 포함하는 집적 회로, 그 설계 방법 및 설계 시스템
US11011417B2 (en) 2019-05-31 2021-05-18 International Business Machines Corporation Method and structure of metal cut
US10909297B1 (en) * 2019-08-15 2021-02-02 Taiwan Semiconductor Manufacturing Company Limited Deterministic system for device layout optimization
EP4073677A1 (en) * 2019-12-09 2022-10-19 Synopsys, Inc. Electrical circuit design using cells with metal lines
CN111931450B (zh) * 2020-08-11 2024-09-20 上海华力微电子有限公司 一种集成电路数字后端设计的方法和系统
US11290109B1 (en) * 2020-09-23 2022-03-29 Qualcomm Incorporated Multibit multi-height cell to improve pin accessibility
CN115117052A (zh) 2021-03-18 2022-09-27 三星电子株式会社 提供增加的引脚接入点的集成电路及其设计方法
CN118551721B (zh) * 2024-07-30 2024-10-18 上海聪链信息科技有限公司 N12设计中的防违例绕线方法、装置、设备及存储介质

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04216668A (ja) * 1990-12-15 1992-08-06 Sharp Corp 半導体集積回路
US6174742B1 (en) 1998-10-30 2001-01-16 Lsi Logic Corporation Off-grid metal layer utilization
US7036103B2 (en) * 1999-10-14 2006-04-25 Synopsys, Inc. Detailed placer for optimizing high density cell placement in a linear runtime
US6351841B1 (en) 2000-03-21 2002-02-26 Cadence Design Systems, Inc. Method and apparatus for creating multi-gate transistors with integrated circuit polygon compactors
US7089521B2 (en) * 2004-01-27 2006-08-08 International Business Machines Corporation Method for legalizing the placement of cells in an integrated circuit layout
US6903389B1 (en) 2004-06-15 2005-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Variable layout design for multiple voltage applications
US7194717B2 (en) * 2004-09-08 2007-03-20 Lsi Logic Corporation Compact custom layout for RRAM column controller
JP4796817B2 (ja) 2005-10-31 2011-10-19 エルピーダメモリ株式会社 基本セル設計方法、レイアウト設計方法、設計装置およびプログラム
US7640522B2 (en) * 2006-01-14 2009-12-29 Tela Innovations, Inc. Method and system for placing layout objects in a standard-cell layout
US8214778B2 (en) * 2007-08-02 2012-07-03 Tela Innovations, Inc. Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US7564077B2 (en) * 2006-05-05 2009-07-21 Texas Instruments Incorporated Performance and area scalable cell architecture technology
US7888705B2 (en) 2007-08-02 2011-02-15 Tela Innovations, Inc. Methods for defining dynamic array section with manufacturing assurance halo and apparatus implementing the same
US8136072B2 (en) 2008-11-03 2012-03-13 Arm Limited Standard cell placement
US7919792B2 (en) 2008-12-18 2011-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. Standard cell architecture and methods with variable design rules
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
JP5325162B2 (ja) * 2010-05-18 2013-10-23 パナソニック株式会社 半導体装置
US8423946B1 (en) * 2010-05-25 2013-04-16 Marvell International Ltd. Circuitry having programmable power rails, architectures, apparatuses, and systems including the same, and methods and algorithms for programming and/or configuring power rails in an integrated circuit
US8431968B2 (en) 2010-07-28 2013-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Electromigration resistant standard cell device
US8742464B2 (en) 2011-03-03 2014-06-03 Synopsys, Inc. Power routing in standard cells
US8612914B2 (en) * 2011-03-23 2013-12-17 Synopsys, Inc. Pin routing in standard cells
US8513978B2 (en) 2011-03-30 2013-08-20 Synopsys, Inc. Power routing in standard cell designs
US8451026B2 (en) * 2011-05-13 2013-05-28 Arm Limited Integrated circuit, method of generating a layout of an integrated circuit using standard cells, and a standard cell library providing such standard cells
US8987831B2 (en) 2012-01-12 2015-03-24 Taiwan Semiconductor Manufacturing Company, Ltd. SRAM cells and arrays
CN104134657B (zh) * 2013-05-02 2018-01-26 台湾积体电路制造股份有限公司 单元高度为标称最小间距的非整数倍的标准单元
US9659129B2 (en) 2013-05-02 2017-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Standard cell having cell height being non-integral multiple of nominal minimum pitch
KR102152772B1 (ko) * 2013-11-18 2020-09-08 삼성전자 주식회사 레이아웃 디자인 시스템, 레이아웃 디자인 방법, 및 이를 이용하여 제조된 반도체 장치
US9887209B2 (en) * 2014-05-15 2018-02-06 Qualcomm Incorporated Standard cell architecture with M1 layer unidirectional routing
US9876017B2 (en) * 2014-12-03 2018-01-23 Qualcomm Incorporated Static random access memory (SRAM) bit cells with wordline landing pads split across boundary edges of the SRAM bit cells
US9727685B2 (en) * 2015-05-14 2017-08-08 Globalfoundries Inc. Method, apparatus, and system for improved standard cell design and routing for improving standard cell routability
KR102504289B1 (ko) * 2016-04-07 2023-02-28 삼성전자 주식회사 인접 핀들 사이의 라우팅 간섭을 제거하는 구조를 갖는 표준 셀과 이를 포함하는 장치

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