JP7015824B2 - セル境界外に延在する金属層セグメントを有する標準セルを実装する集積回路 - Google Patents

セル境界外に延在する金属層セグメントを有する標準セルを実装する集積回路 Download PDF

Info

Publication number
JP7015824B2
JP7015824B2 JP2019500874A JP2019500874A JP7015824B2 JP 7015824 B2 JP7015824 B2 JP 7015824B2 JP 2019500874 A JP2019500874 A JP 2019500874A JP 2019500874 A JP2019500874 A JP 2019500874A JP 7015824 B2 JP7015824 B2 JP 7015824B2
Authority
JP
Japan
Prior art keywords
cell
metal
distance
boundary
segment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2019500874A
Other languages
English (en)
Japanese (ja)
Other versions
JP2019526170A (ja
JP2019526170A5 (enExample
Inventor
ロウハニ オミド
コルドス ローン
ハメル ケリー
クレイ ドナルド
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ATI Technologies ULC
Advanced Micro Devices Inc
Original Assignee
ATI Technologies ULC
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ATI Technologies ULC, Advanced Micro Devices Inc filed Critical ATI Technologies ULC
Publication of JP2019526170A publication Critical patent/JP2019526170A/ja
Publication of JP2019526170A5 publication Critical patent/JP2019526170A5/ja
Application granted granted Critical
Publication of JP7015824B2 publication Critical patent/JP7015824B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/20—Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H10D84/968—Macro-architecture
    • H10D84/974—Layout specifications, i.e. inner core regions
    • H10D84/975—Wiring regions or routing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Physics & Mathematics (AREA)
  • Architecture (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2019500874A 2016-07-12 2017-07-10 セル境界外に延在する金属層セグメントを有する標準セルを実装する集積回路 Active JP7015824B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/207,691 2016-07-12
US15/207,691 US9977854B2 (en) 2016-07-12 2016-07-12 Integrated circuit implementing standard cells with metal layer segments extending out of cell boundary
PCT/US2017/041349 WO2018013472A1 (en) 2016-07-12 2017-07-10 Integrated circuit implementing standard cells with metal layer segments extending out of cell boundary

Publications (3)

Publication Number Publication Date
JP2019526170A JP2019526170A (ja) 2019-09-12
JP2019526170A5 JP2019526170A5 (enExample) 2020-08-13
JP7015824B2 true JP7015824B2 (ja) 2022-02-03

Family

ID=57890630

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2019500874A Active JP7015824B2 (ja) 2016-07-12 2017-07-10 セル境界外に延在する金属層セグメントを有する標準セルを実装する集積回路

Country Status (7)

Country Link
US (1) US9977854B2 (enExample)
EP (1) EP3270414A1 (enExample)
JP (1) JP7015824B2 (enExample)
KR (1) KR102294210B1 (enExample)
CN (1) CN109791930B (enExample)
TW (1) TWI732900B (enExample)
WO (1) WO2018013472A1 (enExample)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102458446B1 (ko) * 2016-03-03 2022-10-26 삼성전자주식회사 스탠다드 셀을 포함하는 반도체 장치 및 그것의 전자 설계 자동화 방법
US10691849B2 (en) * 2017-09-28 2020-06-23 Taiwan Semiconductor Manufacturing Co., Ltd. Metal cut optimization for standard cells
DE102018122541A1 (de) 2017-09-29 2019-04-04 Taiwan Semiconductor Manufacturing Co., Ltd. Stiftmodifizierung für standardzellen
US10559558B2 (en) * 2017-09-29 2020-02-11 Taiwan Semiconductor Manufacturing Co., Ltd. Pin modification for standard cells
TWI681309B (zh) * 2018-05-10 2020-01-01 瑞昱半導體股份有限公司 電子裝置測試資料庫產生方法
US10784869B2 (en) * 2018-07-16 2020-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit and method of manufacturing the same
DE102019125900B4 (de) 2018-09-28 2022-03-24 Taiwan Semiconductor Manufacturing Co., Ltd. Metallschnittgebiet-positionierungsverfahren und system
US10997348B2 (en) 2018-09-28 2021-05-04 Taiwan Semiconductor Manufacturing Company Ltd. Metal cut region location method and system
US10769342B2 (en) * 2018-10-31 2020-09-08 Taiwan Semiconductor Manufacturing Company Ltd. Pin access hybrid cell height design
KR102539066B1 (ko) * 2018-11-09 2023-06-01 삼성전자주식회사 서로 다른 타입의 셀들을 포함하는 집적 회로, 그 설계 방법 및 설계 시스템
US11011417B2 (en) 2019-05-31 2021-05-18 International Business Machines Corporation Method and structure of metal cut
US10909297B1 (en) * 2019-08-15 2021-02-02 Taiwan Semiconductor Manufacturing Company Limited Deterministic system for device layout optimization
EP4073677A1 (en) * 2019-12-09 2022-10-19 Synopsys, Inc. Electrical circuit design using cells with metal lines
CN111931450B (zh) * 2020-08-11 2024-09-20 上海华力微电子有限公司 一种集成电路数字后端设计的方法和系统
US11290109B1 (en) * 2020-09-23 2022-03-29 Qualcomm Incorporated Multibit multi-height cell to improve pin accessibility
CN115117052A (zh) 2021-03-18 2022-09-27 三星电子株式会社 提供增加的引脚接入点的集成电路及其设计方法
CN118551721B (zh) * 2024-07-30 2024-10-18 上海聪链信息科技有限公司 N12设计中的防违例绕线方法、装置、设备及存储介质

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007123682A (ja) 2005-10-31 2007-05-17 Elpida Memory Inc 基本セル設計方法、レイアウト設計方法、設計装置およびプログラム
JP2015149491A (ja) 2007-08-02 2015-08-20 テラ イノヴェイションズ インク 半導体チップ、定義方法および設計方法

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04216668A (ja) * 1990-12-15 1992-08-06 Sharp Corp 半導体集積回路
US6174742B1 (en) 1998-10-30 2001-01-16 Lsi Logic Corporation Off-grid metal layer utilization
US7036103B2 (en) * 1999-10-14 2006-04-25 Synopsys, Inc. Detailed placer for optimizing high density cell placement in a linear runtime
US6351841B1 (en) 2000-03-21 2002-02-26 Cadence Design Systems, Inc. Method and apparatus for creating multi-gate transistors with integrated circuit polygon compactors
US7089521B2 (en) * 2004-01-27 2006-08-08 International Business Machines Corporation Method for legalizing the placement of cells in an integrated circuit layout
US6903389B1 (en) 2004-06-15 2005-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Variable layout design for multiple voltage applications
US7194717B2 (en) * 2004-09-08 2007-03-20 Lsi Logic Corporation Compact custom layout for RRAM column controller
US7640522B2 (en) * 2006-01-14 2009-12-29 Tela Innovations, Inc. Method and system for placing layout objects in a standard-cell layout
US8214778B2 (en) * 2007-08-02 2012-07-03 Tela Innovations, Inc. Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US7564077B2 (en) * 2006-05-05 2009-07-21 Texas Instruments Incorporated Performance and area scalable cell architecture technology
US8136072B2 (en) 2008-11-03 2012-03-13 Arm Limited Standard cell placement
US7919792B2 (en) 2008-12-18 2011-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. Standard cell architecture and methods with variable design rules
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
JP5325162B2 (ja) * 2010-05-18 2013-10-23 パナソニック株式会社 半導体装置
US8423946B1 (en) * 2010-05-25 2013-04-16 Marvell International Ltd. Circuitry having programmable power rails, architectures, apparatuses, and systems including the same, and methods and algorithms for programming and/or configuring power rails in an integrated circuit
US8431968B2 (en) 2010-07-28 2013-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Electromigration resistant standard cell device
US8742464B2 (en) 2011-03-03 2014-06-03 Synopsys, Inc. Power routing in standard cells
US8612914B2 (en) * 2011-03-23 2013-12-17 Synopsys, Inc. Pin routing in standard cells
US8513978B2 (en) 2011-03-30 2013-08-20 Synopsys, Inc. Power routing in standard cell designs
US8451026B2 (en) * 2011-05-13 2013-05-28 Arm Limited Integrated circuit, method of generating a layout of an integrated circuit using standard cells, and a standard cell library providing such standard cells
US8987831B2 (en) 2012-01-12 2015-03-24 Taiwan Semiconductor Manufacturing Company, Ltd. SRAM cells and arrays
CN104134657B (zh) * 2013-05-02 2018-01-26 台湾积体电路制造股份有限公司 单元高度为标称最小间距的非整数倍的标准单元
US9659129B2 (en) 2013-05-02 2017-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Standard cell having cell height being non-integral multiple of nominal minimum pitch
KR102152772B1 (ko) * 2013-11-18 2020-09-08 삼성전자 주식회사 레이아웃 디자인 시스템, 레이아웃 디자인 방법, 및 이를 이용하여 제조된 반도체 장치
US9887209B2 (en) * 2014-05-15 2018-02-06 Qualcomm Incorporated Standard cell architecture with M1 layer unidirectional routing
US9876017B2 (en) * 2014-12-03 2018-01-23 Qualcomm Incorporated Static random access memory (SRAM) bit cells with wordline landing pads split across boundary edges of the SRAM bit cells
US9727685B2 (en) * 2015-05-14 2017-08-08 Globalfoundries Inc. Method, apparatus, and system for improved standard cell design and routing for improving standard cell routability
KR102504289B1 (ko) * 2016-04-07 2023-02-28 삼성전자 주식회사 인접 핀들 사이의 라우팅 간섭을 제거하는 구조를 갖는 표준 셀과 이를 포함하는 장치

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007123682A (ja) 2005-10-31 2007-05-17 Elpida Memory Inc 基本セル設計方法、レイアウト設計方法、設計装置およびプログラム
JP2015149491A (ja) 2007-08-02 2015-08-20 テラ イノヴェイションズ インク 半導体チップ、定義方法および設計方法

Also Published As

Publication number Publication date
KR102294210B1 (ko) 2021-08-27
TW201813050A (zh) 2018-04-01
US20180018419A1 (en) 2018-01-18
CN109791930B (zh) 2021-08-27
EP3270414A1 (en) 2018-01-17
JP2019526170A (ja) 2019-09-12
US9977854B2 (en) 2018-05-22
TWI732900B (zh) 2021-07-11
KR20190018542A (ko) 2019-02-22
CN109791930A (zh) 2019-05-21
WO2018013472A1 (en) 2018-01-18

Similar Documents

Publication Publication Date Title
JP7015824B2 (ja) セル境界外に延在する金属層セグメントを有する標準セルを実装する集積回路
Kahng et al. VLSI physical design: from graph partitioning to timing closure
CN107239588B (zh) 集成电路设计的定制布局
CN103544333B (zh) 半导体器件设计方法、系统和计算机程序产品
CN107066681B (zh) 集成电路和制造集成电路的计算机实现方法
US9053283B2 (en) Methods for layout verification for polysilicon cell edge structures in finFET standard cells using filters
CN104050306B (zh) 用于FinFET标准单元中多晶硅单元边缘结构的布局验证方法
CN107918694B (zh) 用于减少集成电路上的延迟的方法
US9928337B2 (en) Integrated circuit and design method for same
CN110941936B (zh) 集成电路、集成电路形成方法及设计系统、多位元正反器
US8234612B2 (en) Cone-aware spare cell placement using hypergraph connectivity analysis
WO2015015319A2 (en) Architecture of spare wiring structures for improved engineering change orders
JP4141322B2 (ja) 半導体集積回路の自動配線方法及び半導体集積回路の設計のプログラム
ITVI20100166A1 (it) Integrated circuit design framework comprising automatic analysis functonality
TWI789911B (zh) 用於電容值提取的系統、方法及儲存媒體
TWI718245B (zh) 積體電路、製造其的電腦實施方法以及定義其的標準元件
KR20160051532A (ko) 집적 회로 및 그것의 레이아웃을 설계하는 방법
US8966429B2 (en) Bit slice elements utilizing through device routing
US20040003363A1 (en) Integrated circuit design and manufacture utilizing layers having a predetermined layout
US9293450B2 (en) Synthesis of complex cells
JP4668974B2 (ja) 半導体装置の設計方法、半導体装置設計システム及びコンピュータプログラム
Lienig et al. Methodologies for Physical Design: Models, Styles, Tasks, and Flows
US20240086609A1 (en) Integrated circuit design method, system and computer program product
Chen et al. Challenges and solutions in modern analog placement
Ozaki et al. MGX: An integrated symbolic layout system for VLSI

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20190409

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20200706

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20200706

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20200706

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20200729

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20201113

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20201208

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20210225

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20210507

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20210803

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20211202

C60 Trial request (containing other claim documents, opposition documents)

Free format text: JAPANESE INTERMEDIATE CODE: C60

Effective date: 20211202

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20211213

C21 Notice of transfer of a case for reconsideration by examiners before appeal proceedings

Free format text: JAPANESE INTERMEDIATE CODE: C21

Effective date: 20211214

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20220104

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20220124

R150 Certificate of patent or registration of utility model

Ref document number: 7015824

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250