JP2016514371A - 縦型メモリの浮遊ゲートメモリセル - Google Patents
縦型メモリの浮遊ゲートメモリセル Download PDFInfo
- Publication number
- JP2016514371A JP2016514371A JP2016500651A JP2016500651A JP2016514371A JP 2016514371 A JP2016514371 A JP 2016514371A JP 2016500651 A JP2016500651 A JP 2016500651A JP 2016500651 A JP2016500651 A JP 2016500651A JP 2016514371 A JP2016514371 A JP 2016514371A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- oxide layer
- floating gate
- protrusion
- dielectric layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015654 memory Effects 0.000 title claims abstract description 116
- 150000004767 nitrides Chemical class 0.000 claims description 110
- 230000004888 barrier function Effects 0.000 claims description 65
- 230000000903 blocking effect Effects 0.000 claims description 56
- 239000000463 material Substances 0.000 description 65
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 59
- 229920005591 polysilicon Polymers 0.000 description 59
- 238000000034 method Methods 0.000 description 49
- 238000004519 manufacturing process Methods 0.000 description 43
- 238000010586 diagram Methods 0.000 description 24
- 238000005530 etching Methods 0.000 description 24
- 230000008569 process Effects 0.000 description 21
- 238000000151 deposition Methods 0.000 description 12
- 238000007373 indentation Methods 0.000 description 12
- 230000008021 deposition Effects 0.000 description 11
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 10
- 239000004020 conductor Substances 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 230000003071 parasitic effect Effects 0.000 description 6
- 230000002829 reductive effect Effects 0.000 description 6
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 4
- 239000012808 vapor phase Substances 0.000 description 4
- 230000009467 reduction Effects 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000012071 phase Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229920001577 copolymer Polymers 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
- H01L2924/1435—Random access memory [RAM]
- H01L2924/1438—Flash memory
Abstract
Description
本出願は、参照によってその全体が本明細書に組み込まれる、2013年3月15日に出願された、U.S. Application Serial No. 13/838,297の優先権の利益を主張する。
第2のFG層566のポリシリコンは、任意でドープされてよい。
Claims (23)
- 第1の誘電体層と第2の誘電体層との間の制御ゲートと、
前記第1の誘電体層と前記第2の誘電体層との間の浮遊ゲートであって、前記制御ゲートに向かって伸びる突起を含む、浮遊ゲートと、
前記浮遊ゲートと前記制御ゲートとの間の電荷ブロック構造であって、前記電荷ブロック構造の少なくとも一部が前記突起の周りを覆う、電荷ブロック構造と、
を備える、メモリセル。 - 前記浮遊ゲートが、前記第1の誘電体層と前記第2の誘電体層とに接する、請求項1に記載の前記メモリセル。
- 前記突起が、前記制御ゲートに向かって伸びる、前記浮遊ゲートの唯一の突起である、請求項1に記載の前記メモリセル。
- 前記誘電体層の間の前記浮遊ゲートの長さが、前記誘電体層の間の前記制御ゲートの長さに実質的に等しい、請求項1に記載の前記メモリセル。
- 前記電荷ブロック構造が、第1の酸化物層と窒化物層と第2の酸化物層とを備え、前記電荷ブロック構造のバリア構造の少なくとも一部が、前記突起の周りを覆い、前記第2の酸化物層を備える、請求項1に記載の前記メモリセル。
- 前記浮遊ゲートが、前記窒化物層と前記第2の酸化物層とに接している、請求項5に記載の前記メモリセル。
- 前記第2の酸化物層が、前記窒化物層を前記浮遊ゲートから完全に隔てる、請求項5に記載の前記メモリセル。
- 前記浮遊ゲートが、前記第2の酸化物層に接し、前記窒化物層には接していない、請求項5に記載の前記メモリセル。
- 前記窒化物層の第1の部分及び前記第2の酸化物層の第1の部分が、前記突起と前記第1の誘電体層の上面との間にあり、前記窒化物層の第2の部分及び前記第2の酸化物層の第2の部分が、前記突起と前記第2の誘電体層の下面との間にある、請求項5に記載の前記メモリセル。
- 前記突起が中央の突起を備え、前記浮遊ゲートが、
前記第1の誘電体層の前記上面に隣接する第1の突起と、
前記第2の誘電体層の前記下面に隣接する第2の突起と、
をさらに備え、
前記中央の突起が、前記第1の突起と第2の突起との間にあり、前記第2の酸化物層の前記第1の部分が、前記第1の突起と前記中央の突起との間にあり、前記第2の酸化物層の前記第2の部分が、前記第2の突起と前記中央の突起との間にある、
請求項9に記載の前記メモリセル。 - メモリセルから成る縦型ストリングを含む装置であって、メモリセルから成る前記縦型ストリングのメモリセルが、
第1の誘電体層と第2の誘電体層との間の制御ゲートと、
前記第1の誘電体層と前記第2の誘電体層との間の浮遊ゲートと、
前記浮遊ゲートと前記制御ゲートとの間の電荷ブロック構造であって、バリア膜を備え、前記バリア膜の実質的に垂直な部分が、前記制御ゲートと前記浮遊ゲートとの間にあり、前記バリア膜の第1の実質的に水平な部分が、前記第1の誘電体層と前記浮遊ゲートとの間に部分的に水平方向に伸び、前記バリア膜の第2の実質的に水平な部分が、前記第2の誘電体層と前記浮遊ゲートとの間に部分的に水平方向に伸びる、電荷ブロック構造と、
を備える、装置。 - 前記浮遊ゲートの第1の部分が、前記バリア膜の前記第1の実質的に水平な部分によって、前記第1の誘電体層の上面から隔てられ、さらに、前記浮遊ゲートの第2の部分が、前記バリア膜の前記第2の実質的に水平な部分によって、前記第2の誘電体層の下面から隔てられている、請求項11に記載の前記装置。
- 前記バリア膜の前記実質的に垂直な部分の厚さが、前記バリア膜の前記第1の実質的に水平な部分の厚さよりも大きく、前記バリア膜の前記第2の実質的に水平な部分の厚さよりも大きい、請求項11に記載の前記装置。
- 前記誘電体層の間の前記浮遊ゲートの長さが、前記誘電体層の間の前記制御ゲートの長さに実質的に等しい、請求項11に記載の前記装置。
- 前記バリア膜が窒化物層を備える、請求項11に記載の前記装置。
- 前記電荷ブロック構造が、第1の酸化物層と第2の酸化物層とをさらに備える、請求項11に記載の前記装置。
- 前記バリア膜が窒化物層を備える、請求項16に記載の前記装置。
- 前記浮遊ゲートの第1の部分が、前記バリア膜の前記第1の実質的に水平な部分と前記第2の酸化物層の第1の部分とによって、前記第1の誘電体層の上面から隔てられ、さらに、前記浮遊ゲートの第2の部分が、前記バリア膜の前記第2の実質的に水平な部分と前記第2の酸化物層の第2の部分とによって、前記第2の誘電体層の下面から隔てられている、請求項16に記載の前記装置。
- 前記浮遊ゲートの第3の部分が、前記第2の酸化物層の第3の部分によって、前記第1の誘電体層の前記上面から隔てられ、さらに、前記浮遊ゲートの第4の部分が、前記第2の酸化物層の第4の部分によって、前記第2の誘電体層の前記下面から隔てられている、請求項18に記載の前記装置。
- 前記浮遊ゲートが前記制御ゲートに向かって伸びる突起を含む、請求項16に記載の前記装置。
- 前記浮遊ゲートが、前記第1の誘電体層と前記第2の誘電体層とに接する、請求項20に記載の前記装置。
- 前記突起が、前記バリア膜の前記第1の実質的に水平な部分と前記第2の酸化物層の第1の部分とによって、前記第1の誘電体層の上面から隔てられ、さらに、前記突起が、前記バリア膜の少なくとも前記第2の実質的に水平な部分と前記第2の酸化物層の第2の部分とによって、前記第2の誘電体層の下面から隔てられている、請求項20に記載の前記装置。
- 前記第2の酸化物層の前記第1と前記第2との部分が、前記第2の酸化物層の第1と第2との実質的に水平な部分を備え、前記第2の酸化物層が、実質的に垂直な部分をさらに備え、前記第2の酸化物層の前記実質的に垂直な部分の厚さ、前記第2の酸化物層の前記第1の実質的に水平な部分の厚さ、及び前記第2の酸化物層の前記第2の実質的に水平な部分の厚さが、実質的に同じである、請求項22に記載の前記装置。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/838,297 | 2013-03-15 | ||
US13/838,297 US9184175B2 (en) | 2013-03-15 | 2013-03-15 | Floating gate memory cells in vertical memory |
PCT/US2014/020658 WO2014149740A1 (en) | 2013-03-15 | 2014-03-05 | Floating gate memory cells in vertical memory |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2016514371A true JP2016514371A (ja) | 2016-05-19 |
JP5965091B2 JP5965091B2 (ja) | 2016-08-03 |
Family
ID=51523692
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2016500651A Active JP5965091B2 (ja) | 2013-03-15 | 2014-03-05 | 縦型メモリの浮遊ゲートメモリセル |
Country Status (7)
Country | Link |
---|---|
US (4) | US9184175B2 (ja) |
EP (2) | EP2973710B1 (ja) |
JP (1) | JP5965091B2 (ja) |
KR (2) | KR101821943B1 (ja) |
CN (2) | CN105164808B (ja) |
TW (2) | TWI655782B (ja) |
WO (1) | WO2014149740A1 (ja) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017163044A (ja) * | 2016-03-10 | 2017-09-14 | 東芝メモリ株式会社 | 半導体装置およびその製造方法 |
US9793282B2 (en) | 2013-03-15 | 2017-10-17 | Micron Technology, Inc. | Floating gate memory cells in vertical memory |
US10141322B2 (en) | 2013-12-17 | 2018-11-27 | Intel Corporation | Metal floating gate composite 3D NAND memory devices and associated methods |
US10170639B2 (en) | 2013-01-24 | 2019-01-01 | Micron Technology, Inc. | 3D memory |
US10217799B2 (en) | 2013-03-15 | 2019-02-26 | Micron Technology, Inc. | Cell pillar structures and integrated flows |
US10847527B2 (en) | 2013-03-15 | 2020-11-24 | Micron Technology, Inc. | Memory including blocking dielectric in etch stop tier |
US10923487B2 (en) | 2018-09-18 | 2021-02-16 | Toshiba Memory Corporation | Semiconductor memory device |
US11665893B2 (en) | 2013-11-01 | 2023-05-30 | Micron Technology, Inc. | Methods and apparatuses having strings of memory cells including a metal source |
Families Citing this family (45)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9252149B2 (en) * | 2012-04-30 | 2016-02-02 | Hewlett-Packard Development Company, L.P. | Device including active floating gate region area that is smaller than channel area |
US9093152B2 (en) | 2012-10-26 | 2015-07-28 | Micron Technology, Inc. | Multiple data line memory and methods |
US9147493B2 (en) * | 2013-06-17 | 2015-09-29 | Micron Technology, Inc. | Shielded vertically stacked data line architecture for memory |
US9275909B2 (en) | 2013-08-12 | 2016-03-01 | Micron Technology, Inc. | Methods of fabricating semiconductor structures |
KR20150050877A (ko) * | 2013-11-01 | 2015-05-11 | 에스케이하이닉스 주식회사 | 트랜지스터 및 이를 포함하는 반도체 장치 |
US9478643B2 (en) * | 2013-12-24 | 2016-10-25 | Intel Corporation | Memory structure with self-aligned floating and control gates and associated methods |
US9240416B2 (en) * | 2014-06-12 | 2016-01-19 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
US9524779B2 (en) | 2014-06-24 | 2016-12-20 | Sandisk Technologies Llc | Three dimensional vertical NAND device with floating gates |
US9627391B2 (en) * | 2014-07-10 | 2017-04-18 | Kabushiki Kaisha Toshiba | Non-volatile memory device |
US9917096B2 (en) * | 2014-09-10 | 2018-03-13 | Toshiba Memory Corporation | Semiconductor memory device and method for manufacturing same |
US20160079252A1 (en) * | 2014-09-11 | 2016-03-17 | Kabushiki Kaisha Toshiba | Semiconductor memory device and method for manufacturing the same |
US9793124B2 (en) * | 2014-10-07 | 2017-10-17 | Micron Technology, Inc. | Semiconductor structures |
US10672785B2 (en) | 2015-04-06 | 2020-06-02 | Micron Technology, Inc. | Integrated structures of vertically-stacked memory cells |
US9608000B2 (en) | 2015-05-27 | 2017-03-28 | Micron Technology, Inc. | Devices and methods including an etch stop protection material |
WO2016194211A1 (ja) * | 2015-06-04 | 2016-12-08 | 株式会社 東芝 | 半導体記憶装置及びその製造方法 |
KR102456494B1 (ko) * | 2016-03-29 | 2022-10-20 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 제조 방법 |
US10727241B2 (en) * | 2016-06-30 | 2020-07-28 | Intel Corporation | 3D NAND structures including group III-N material channels |
KR102395563B1 (ko) * | 2016-07-25 | 2022-05-06 | 에스케이하이닉스 주식회사 | 비휘발성 메모리 소자 및 이의 제조 방법 |
US10090318B2 (en) * | 2016-08-05 | 2018-10-02 | Micron Technology, Inc. | Vertical string of memory cells individually comprising a programmable charge storage transistor comprising a control gate and a charge storage structure and method of forming a vertical string of memory cells individually comprising a programmable charge storage transistor comprising a control gate and a charge storage structure |
US9941293B1 (en) | 2016-10-12 | 2018-04-10 | Sandisk Technologies Llc | Select transistors with tight threshold voltage in 3D memory |
US9773882B1 (en) | 2017-01-12 | 2017-09-26 | Micron Technology, Inc. | Integrated structures |
US10083981B2 (en) | 2017-02-01 | 2018-09-25 | Micron Technology, Inc. | Memory arrays, and methods of forming memory arrays |
US10431591B2 (en) | 2017-02-01 | 2019-10-01 | Micron Technology, Inc. | NAND memory arrays |
US10164009B1 (en) | 2017-08-11 | 2018-12-25 | Micron Technology, Inc. | Memory device including voids between control gates |
US10680006B2 (en) | 2017-08-11 | 2020-06-09 | Micron Technology, Inc. | Charge trap structure with barrier to blocking region |
US10453855B2 (en) | 2017-08-11 | 2019-10-22 | Micron Technology, Inc. | Void formation in charge trap structures |
US10446572B2 (en) | 2017-08-11 | 2019-10-15 | Micron Technology, Inc. | Void formation for charge trap structures |
US10283513B1 (en) * | 2017-11-06 | 2019-05-07 | Sandisk Technologies Llc | Three-dimensional memory device with annular blocking dielectrics and method of making thereof |
KR102505240B1 (ko) | 2017-11-09 | 2023-03-06 | 삼성전자주식회사 | 3차원 반도체 메모리 장치 |
US10714494B2 (en) | 2017-11-23 | 2020-07-14 | Macronix International Co., Ltd. | 3D memory device with silicon nitride and buffer oxide layers and method of manufacturing the same |
US10937482B2 (en) * | 2017-12-27 | 2021-03-02 | Micron Technology, Inc. | Memory cells and arrays of elevationally-extending strings of memory cells |
US10937904B2 (en) | 2017-12-27 | 2021-03-02 | Micron Technology, Inc. | Programmable charge-storage transistor, an array of elevationally-extending strings of memory cells, and a method of forming an array of elevationally-extending strings of memory cells |
US10622450B2 (en) | 2018-06-28 | 2020-04-14 | Intel Corporation | Modified floating gate and dielectric layer geometry in 3D memory arrays |
US11527548B2 (en) | 2018-12-11 | 2022-12-13 | Micron Technology, Inc. | Semiconductor devices and electronic systems including an etch stop material, and related methods |
KR102574451B1 (ko) | 2019-02-22 | 2023-09-04 | 삼성전자 주식회사 | 집적회로 소자 및 그 제조 방법 |
CN110148598A (zh) * | 2019-04-19 | 2019-08-20 | 华中科技大学 | 一种基于二维半导体材料垂直沟道的三维闪存存储器及其制备 |
KR20210002137A (ko) | 2019-06-20 | 2021-01-07 | 삼성전자주식회사 | 수직형 메모리 장치 |
US11508746B2 (en) | 2019-10-25 | 2022-11-22 | Micron Technology, Inc. | Semiconductor device having a stack of data lines with conductive structures on both sides thereof |
US11605588B2 (en) | 2019-12-20 | 2023-03-14 | Micron Technology, Inc. | Memory device including data lines on multiple device levels |
TWI749549B (zh) | 2020-05-08 | 2021-12-11 | 力晶積成電子製造股份有限公司 | 記憶體結構及其製造方法 |
DE102020133314A1 (de) * | 2020-05-28 | 2021-12-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | 3d-speicher mit leitfähigen graphitstreifen |
US11574929B2 (en) | 2020-05-28 | 2023-02-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D ferroelectric memory |
DE102020132926A1 (de) * | 2020-05-28 | 2021-12-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | 3d ferroelektrischer speicher |
US11716856B2 (en) | 2021-03-05 | 2023-08-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Three-dimensional memory device and method |
JP2023092644A (ja) * | 2021-12-22 | 2023-07-04 | キオクシア株式会社 | 半導体装置 |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2006132158A1 (ja) * | 2005-06-10 | 2006-12-14 | Sharp Kabushiki Kaisha | 不揮発性半導体記憶装置およびその製造方法 |
JP2007005814A (ja) * | 2005-06-24 | 2007-01-11 | Samsung Electronics Co Ltd | 半導体装置及びその製造方法 |
JP2007123415A (ja) * | 2005-10-26 | 2007-05-17 | Sharp Corp | 半導体装置およびその製造方法 |
JP2007294595A (ja) * | 2006-04-24 | 2007-11-08 | Toshiba Corp | 不揮発性半導体メモリ |
JP2008159804A (ja) * | 2006-12-22 | 2008-07-10 | Toshiba Corp | 不揮発性半導体メモリ |
JP2010004020A (ja) * | 2008-05-19 | 2010-01-07 | Toshiba Corp | 不揮発性半導体記憶装置およびその製造方法 |
JP2010118539A (ja) * | 2008-11-13 | 2010-05-27 | Toshiba Corp | 不揮発性半導体記憶装置 |
US20100240205A1 (en) * | 2009-03-19 | 2010-09-23 | Samsung Electronics Co., Ltd. | Methods of fabricating three-dimensional nonvolatile memory devices using expansions |
JP2012227326A (ja) * | 2011-04-19 | 2012-11-15 | Toshiba Corp | 不揮発性半導体記憶装置とその製造方法 |
Family Cites Families (66)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58184874A (ja) | 1982-04-22 | 1983-10-28 | Matsushita Electric Ind Co Ltd | 帯域圧縮装置 |
TW390028B (en) | 1998-06-08 | 2000-05-11 | United Microelectronics Corp | A flash memory structure and its manufacturing |
CN100358147C (zh) * | 2000-08-14 | 2007-12-26 | 矩阵半导体公司 | 密集阵列和电荷存储器件及其制造方法 |
US6445029B1 (en) | 2000-10-24 | 2002-09-03 | International Business Machines Corporation | NVRAM array device with enhanced write and erase |
US7132711B2 (en) | 2001-08-30 | 2006-11-07 | Micron Technology, Inc. | Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers |
US6780712B2 (en) * | 2002-10-30 | 2004-08-24 | Taiwan Semiconductor Manufacturing Company | Method for fabricating a flash memory device having finger-like floating gates structure |
US6583009B1 (en) | 2002-06-24 | 2003-06-24 | Advanced Micro Devices, Inc. | Innovative narrow gate formation for floating gate flash technology |
US7045849B2 (en) | 2003-05-21 | 2006-05-16 | Sandisk Corporation | Use of voids between elements in semiconductor structures for isolation |
US7148538B2 (en) | 2003-12-17 | 2006-12-12 | Micron Technology, Inc. | Vertical NAND flash memory array |
US7829938B2 (en) * | 2005-07-14 | 2010-11-09 | Micron Technology, Inc. | High density NAND non-volatile memory device |
KR100781563B1 (ko) * | 2005-08-31 | 2007-12-03 | 삼성전자주식회사 | 비휘발성 메모리 소자 및 그 제조 방법. |
US7342272B2 (en) | 2005-08-31 | 2008-03-11 | Micron Technology, Inc. | Flash memory with recessed floating gate |
KR100801078B1 (ko) | 2006-06-29 | 2008-02-11 | 삼성전자주식회사 | 수직 채널을 갖는 비휘발성 메모리 집적 회로 장치 및 그제조 방법 |
US7667260B2 (en) * | 2006-08-09 | 2010-02-23 | Micron Technology, Inc. | Nanoscale floating gate and methods of formation |
JP4768557B2 (ja) | 2006-09-15 | 2011-09-07 | 株式会社東芝 | 不揮発性半導体記憶装置及びその製造方法 |
JP4772656B2 (ja) | 2006-12-21 | 2011-09-14 | 株式会社東芝 | 不揮発性半導体メモリ |
JP4445514B2 (ja) | 2007-04-11 | 2010-04-07 | 株式会社東芝 | 半導体記憶装置 |
KR100866966B1 (ko) | 2007-05-10 | 2008-11-06 | 삼성전자주식회사 | 비휘발성 메모리 소자, 그 제조 방법 및 반도체 패키지 |
TWI340431B (en) | 2007-06-11 | 2011-04-11 | Nanya Technology Corp | Memory structure and method of making the same |
US7910446B2 (en) | 2007-07-16 | 2011-03-22 | Applied Materials, Inc. | Integrated scheme for forming inter-poly dielectrics for non-volatile memory devices |
US7795673B2 (en) | 2007-07-23 | 2010-09-14 | Macronix International Co., Ltd. | Vertical non-volatile memory |
US20090039410A1 (en) | 2007-08-06 | 2009-02-12 | Xian Liu | Split Gate Non-Volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing |
KR101226685B1 (ko) | 2007-11-08 | 2013-01-25 | 삼성전자주식회사 | 수직형 반도체 소자 및 그 제조 방법. |
US8394683B2 (en) * | 2008-01-15 | 2013-03-12 | Micron Technology, Inc. | Methods of forming semiconductor constructions, and methods of forming NAND unit cells |
KR20090079694A (ko) | 2008-01-18 | 2009-07-22 | 삼성전자주식회사 | 비휘발성 메모리 소자 및 그 제조 방법 |
JP2009277770A (ja) | 2008-05-13 | 2009-11-26 | Toshiba Corp | 不揮発性半導体記憶装置及びその製造方法 |
JP5230274B2 (ja) | 2008-06-02 | 2013-07-10 | 株式会社東芝 | 不揮発性半導体記憶装置 |
KR101052921B1 (ko) | 2008-07-07 | 2011-07-29 | 주식회사 하이닉스반도체 | 버티컬 플로팅 게이트를 구비하는 플래시 메모리소자의제조방법 |
KR101551901B1 (ko) | 2008-12-31 | 2015-09-09 | 삼성전자주식회사 | 반도체 기억 소자 및 그 형성 방법 |
JP5388600B2 (ja) | 2009-01-22 | 2014-01-15 | 株式会社東芝 | 不揮発性半導体記憶装置の製造方法 |
JP5576400B2 (ja) * | 2009-01-29 | 2014-08-20 | インターナショナル・ビジネス・マシーンズ・コーポレーション | フラッシュ・メモリ・デバイスおよびその製造方法 |
KR101573697B1 (ko) | 2009-02-11 | 2015-12-02 | 삼성전자주식회사 | 수직 폴딩 구조의 비휘발성 메모리 소자 및 그 제조 방법 |
JP2011003722A (ja) | 2009-06-18 | 2011-01-06 | Toshiba Corp | 半導体装置の製造方法 |
US8258034B2 (en) | 2009-08-26 | 2012-09-04 | Micron Technology, Inc. | Charge-trap based memory |
KR101698193B1 (ko) * | 2009-09-15 | 2017-01-19 | 삼성전자주식회사 | 3차원 반도체 메모리 장치 및 그 제조 방법 |
JP2011166061A (ja) | 2010-02-15 | 2011-08-25 | Toshiba Corp | 半導体装置の製造方法 |
JP2011187794A (ja) | 2010-03-10 | 2011-09-22 | Toshiba Corp | 半導体記憶装置及びその製造方法 |
US8357970B2 (en) | 2010-04-09 | 2013-01-22 | Micron Technology, Inc. | Multi-level charge storage transistors and associated methods |
KR20110120661A (ko) * | 2010-04-29 | 2011-11-04 | 주식회사 하이닉스반도체 | 비휘발성 메모리 장치 및 그의 제조 방법 |
KR101738533B1 (ko) | 2010-05-24 | 2017-05-23 | 삼성전자 주식회사 | 적층 메모리 장치 및 그 제조 방법 |
KR101623546B1 (ko) | 2010-05-28 | 2016-05-23 | 삼성전자주식회사 | 3차원 반도체 메모리 장치 및 그 제조 방법 |
US8803214B2 (en) | 2010-06-28 | 2014-08-12 | Micron Technology, Inc. | Three dimensional memory and methods of forming the same |
US8198672B2 (en) | 2010-06-30 | 2012-06-12 | SanDisk Technologies, Inc. | Ultrahigh density vertical NAND memory device |
US8187936B2 (en) | 2010-06-30 | 2012-05-29 | SanDisk Technologies, Inc. | Ultrahigh density vertical NAND memory device and method of making thereof |
US8349681B2 (en) | 2010-06-30 | 2013-01-08 | Sandisk Technologies Inc. | Ultrahigh density monolithic, three dimensional vertical NAND memory device |
US8237213B2 (en) * | 2010-07-15 | 2012-08-07 | Micron Technology, Inc. | Memory arrays having substantially vertical, adjacent semiconductor structures and the formation thereof |
KR101660262B1 (ko) | 2010-09-07 | 2016-09-27 | 삼성전자주식회사 | 수직형 반도체 소자의 제조 방법 |
KR101094523B1 (ko) * | 2010-10-13 | 2011-12-19 | 주식회사 하이닉스반도체 | 3차원 구조의 비휘발성 메모리 소자 및 그 제조 방법 |
KR101792778B1 (ko) | 2010-10-26 | 2017-11-01 | 삼성전자주식회사 | 비휘발성 메모리 장치 및 그 형성 방법 |
JP2012094694A (ja) | 2010-10-27 | 2012-05-17 | Toshiba Corp | 不揮発性半導体記憶装置 |
JP2012119445A (ja) * | 2010-11-30 | 2012-06-21 | Toshiba Corp | 半導体記憶装置および半導体記憶装置の製造方法 |
JP2012146773A (ja) | 2011-01-11 | 2012-08-02 | Hitachi Kokusai Electric Inc | 不揮発性半導体記憶装置およびその製造方法 |
US8681555B2 (en) * | 2011-01-14 | 2014-03-25 | Micron Technology, Inc. | Strings of memory cells having string select gates, memory devices incorporating such strings, and methods of accessing and forming the same |
US8759895B2 (en) | 2011-02-25 | 2014-06-24 | Micron Technology, Inc. | Semiconductor charge storage apparatus and methods |
KR101206508B1 (ko) * | 2011-03-07 | 2012-11-29 | 에스케이하이닉스 주식회사 | 3차원 구조를 갖는 비휘발성 메모리 장치 제조방법 |
US8445347B2 (en) * | 2011-04-11 | 2013-05-21 | Sandisk Technologies Inc. | 3D vertical NAND and method of making thereof by front and back side processing |
US8722525B2 (en) | 2011-06-21 | 2014-05-13 | Micron Technology, Inc. | Multi-tiered semiconductor devices and associated methods |
US8912589B2 (en) | 2011-08-31 | 2014-12-16 | Micron Technology, Inc. | Methods and apparatuses including strings of memory cells formed along levels of semiconductor material |
KR20130024303A (ko) | 2011-08-31 | 2013-03-08 | 에스케이하이닉스 주식회사 | 반도체 소자 및 그 제조방법 |
KR101906406B1 (ko) | 2011-12-30 | 2018-12-10 | 삼성전자주식회사 | 수직 구조의 비휘발성 메모리 소자 및 그 제조방법 |
US20130256777A1 (en) | 2012-03-30 | 2013-10-03 | Seagate Technology Llc | Three dimensional floating gate nand memory |
US9178077B2 (en) | 2012-11-13 | 2015-11-03 | Micron Technology, Inc. | Semiconductor constructions |
US8946807B2 (en) | 2013-01-24 | 2015-02-03 | Micron Technology, Inc. | 3D memory |
US9184175B2 (en) | 2013-03-15 | 2015-11-10 | Micron Technology, Inc. | Floating gate memory cells in vertical memory |
US9412753B2 (en) | 2014-09-30 | 2016-08-09 | Sandisk Technologies Llc | Multiheight electrically conductive via contacts for a multilevel interconnect structure |
US9608000B2 (en) | 2015-05-27 | 2017-03-28 | Micron Technology, Inc. | Devices and methods including an etch stop protection material |
-
2013
- 2013-03-15 US US13/838,297 patent/US9184175B2/en active Active
-
2014
- 2014-03-05 EP EP14770149.4A patent/EP2973710B1/en active Active
- 2014-03-05 JP JP2016500651A patent/JP5965091B2/ja active Active
- 2014-03-05 EP EP20205517.4A patent/EP3792972A1/en active Pending
- 2014-03-05 CN CN201480024450.2A patent/CN105164808B/zh active Active
- 2014-03-05 KR KR1020177021238A patent/KR101821943B1/ko active IP Right Grant
- 2014-03-05 KR KR1020157029545A patent/KR101764626B1/ko active IP Right Grant
- 2014-03-05 CN CN201810309077.5A patent/CN108461500B/zh active Active
- 2014-03-05 WO PCT/US2014/020658 patent/WO2014149740A1/en active Application Filing
- 2014-03-14 TW TW107111763A patent/TWI655782B/zh active
- 2014-03-14 TW TW103109314A patent/TWI624069B/zh active
-
2015
- 2015-10-28 US US14/925,589 patent/US9793282B2/en active Active
-
2017
- 2017-08-30 US US15/691,477 patent/US9991273B2/en active Active
-
2018
- 2018-05-15 US US15/980,503 patent/US10355008B2/en active Active
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2006132158A1 (ja) * | 2005-06-10 | 2006-12-14 | Sharp Kabushiki Kaisha | 不揮発性半導体記憶装置およびその製造方法 |
JP2007005814A (ja) * | 2005-06-24 | 2007-01-11 | Samsung Electronics Co Ltd | 半導体装置及びその製造方法 |
JP2007123415A (ja) * | 2005-10-26 | 2007-05-17 | Sharp Corp | 半導体装置およびその製造方法 |
JP2007294595A (ja) * | 2006-04-24 | 2007-11-08 | Toshiba Corp | 不揮発性半導体メモリ |
JP2008159804A (ja) * | 2006-12-22 | 2008-07-10 | Toshiba Corp | 不揮発性半導体メモリ |
JP2010004020A (ja) * | 2008-05-19 | 2010-01-07 | Toshiba Corp | 不揮発性半導体記憶装置およびその製造方法 |
JP2010118539A (ja) * | 2008-11-13 | 2010-05-27 | Toshiba Corp | 不揮発性半導体記憶装置 |
US20100240205A1 (en) * | 2009-03-19 | 2010-09-23 | Samsung Electronics Co., Ltd. | Methods of fabricating three-dimensional nonvolatile memory devices using expansions |
JP2012227326A (ja) * | 2011-04-19 | 2012-11-15 | Toshiba Corp | 不揮発性半導体記憶装置とその製造方法 |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10170639B2 (en) | 2013-01-24 | 2019-01-01 | Micron Technology, Inc. | 3D memory |
US9793282B2 (en) | 2013-03-15 | 2017-10-17 | Micron Technology, Inc. | Floating gate memory cells in vertical memory |
US9991273B2 (en) | 2013-03-15 | 2018-06-05 | Micron Technology, Inc. | Floating gate memory cells in vertical memory |
US10217799B2 (en) | 2013-03-15 | 2019-02-26 | Micron Technology, Inc. | Cell pillar structures and integrated flows |
US10355008B2 (en) | 2013-03-15 | 2019-07-16 | Micron Technology, Inc. | Floating gate memory cells in vertical memory |
US10529776B2 (en) | 2013-03-15 | 2020-01-07 | Micron Technology, Inc. | Cell pillar structures and integrated flows |
US10847527B2 (en) | 2013-03-15 | 2020-11-24 | Micron Technology, Inc. | Memory including blocking dielectric in etch stop tier |
US11043534B2 (en) | 2013-03-15 | 2021-06-22 | Micron Technology, Inc. | Cell pillar structures and integrated flows |
US11665893B2 (en) | 2013-11-01 | 2023-05-30 | Micron Technology, Inc. | Methods and apparatuses having strings of memory cells including a metal source |
US10141322B2 (en) | 2013-12-17 | 2018-11-27 | Intel Corporation | Metal floating gate composite 3D NAND memory devices and associated methods |
JP2017163044A (ja) * | 2016-03-10 | 2017-09-14 | 東芝メモリ株式会社 | 半導体装置およびその製造方法 |
US10923487B2 (en) | 2018-09-18 | 2021-02-16 | Toshiba Memory Corporation | Semiconductor memory device |
Also Published As
Publication number | Publication date |
---|---|
JP5965091B2 (ja) | 2016-08-03 |
KR20150132470A (ko) | 2015-11-25 |
US20170365615A1 (en) | 2017-12-21 |
EP2973710A1 (en) | 2016-01-20 |
US9991273B2 (en) | 2018-06-05 |
TWI655782B (zh) | 2019-04-01 |
CN108461500B (zh) | 2022-04-29 |
CN108461500A (zh) | 2018-08-28 |
TWI624069B (zh) | 2018-05-11 |
CN105164808A (zh) | 2015-12-16 |
US20160049417A1 (en) | 2016-02-18 |
TW201507168A (zh) | 2015-02-16 |
US10355008B2 (en) | 2019-07-16 |
US9184175B2 (en) | 2015-11-10 |
TW201826547A (zh) | 2018-07-16 |
KR20170091764A (ko) | 2017-08-09 |
KR101764626B1 (ko) | 2017-08-03 |
US9793282B2 (en) | 2017-10-17 |
CN105164808B (zh) | 2018-05-04 |
US20140264532A1 (en) | 2014-09-18 |
WO2014149740A1 (en) | 2014-09-25 |
EP2973710A4 (en) | 2016-12-28 |
KR101821943B1 (ko) | 2018-01-25 |
EP2973710B1 (en) | 2020-11-04 |
US20180350827A1 (en) | 2018-12-06 |
EP3792972A1 (en) | 2021-03-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5965091B2 (ja) | 縦型メモリの浮遊ゲートメモリセル | |
TWI606583B (zh) | Non-volatile memory device method | |
US7049189B2 (en) | Method of fabricating non-volatile memory cell adapted for integration of devices and for multiple read/write operations | |
JP6461003B2 (ja) | 不揮発性メモリを有する集積回路及び製造方法 | |
CN106024889B (zh) | 半导体器件及其制造方法 | |
KR20080102030A (ko) | 플래시 메모리 소자, 그 제조 방법 및 동작 방법 | |
TW200522339A (en) | Non-volatile memory cell and manufacturing method thereof | |
JP2019117913A (ja) | 半導体装置およびその製造方法 | |
US11444208B2 (en) | Non-volatile memory device having low-k dielectric layer on sidewall of control gate electrode | |
US6956254B2 (en) | Multilayered dual bit memory device with improved write/erase characteristics and method of manufacturing | |
WO2011091707A1 (zh) | 电荷俘获非挥发半导体存储器及其制造方法 | |
KR20090021974A (ko) | 비휘발성 메모리 소자 및 이를 제조하는 방법 | |
US7718491B2 (en) | Method for making a NAND Memory device with inversion bit lines | |
JP2016500479A (ja) | ディスポーザブルゲートキャップを使用したトランジスタ及びスプリットゲート電荷トラップメモリセルの形成 | |
JP5363004B2 (ja) | 半導体装置の製造方法 | |
KR20060079693A (ko) | 2-비트 불휘발성 메모리 장치 및 이를 제조하는 방법 | |
US8411506B2 (en) | Non-volatile memory and operating method of memory cell |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A975 | Report on accelerated examination |
Free format text: JAPANESE INTERMEDIATE CODE: A971005 Effective date: 20160226 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20160301 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20160520 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20160614 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20160630 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5965091 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |