JP2016029697A - 配線基板、半導体装置及び配線基板の製造方法 - Google Patents
配線基板、半導体装置及び配線基板の製造方法 Download PDFInfo
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- JP2016029697A JP2016029697A JP2014228803A JP2014228803A JP2016029697A JP 2016029697 A JP2016029697 A JP 2016029697A JP 2014228803 A JP2014228803 A JP 2014228803A JP 2014228803 A JP2014228803 A JP 2014228803A JP 2016029697 A JP2016029697 A JP 2016029697A
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Classifications
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
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- H05K1/111—Pads for surface mounting, e.g. lay-out
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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- H05K1/00—Printed circuits
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- H05K1/115—Via connections; Lands around holes or via connections
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
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- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
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- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
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- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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Abstract
【解決手段】配線基板10は、配線層22と、配線層22を被覆する絶縁層31と、絶縁層31を厚さ方向に貫通する貫通孔31Xを充填し、絶縁層31から露出された上端面32Aを有し、配線層22と電気的に接続されたビア配線32と、を有する配線構造11を有する。配線基板10は、絶縁層31の上面31A及びビア配線32の上端面32Aに形成され、表面の一部が粗化面53R,54Rに形成された配線層50と、絶縁層31上に積層され、配線層50を被覆する絶縁層61と、を有する配線構造12を有する。配線構造12の配線密度は、配線構造11の配線密度よりも高い。また、粗化面53R,54Rの表面粗度は、配線層22の表面粗度よりも小さい。
【選択図】図2
Description
以下、図1〜図16に従って第1実施形態を説明する。
図1に示すように、配線基板10は、配線構造11と、配線構造11の一方の側(ここでは、上側)に積層された配線構造12と、配線構造11の他方の側(ここでは、下側)に積層されたソルダレジスト層13とを有している。配線基板10の平面形状は、任意の形状及び任意の大きさとすることができる。例えば、配線基板10の平面形状は、20mm×20mm〜40mm×40mm程度の正方形状とすることができる。
配線構造11は、配線構造12よりも配線密度の低い配線層が形成された低密度配線層である。この配線構造11は、コア基板20と、コア基板20の上面20Aに積層された絶縁層31と、コア基板20の下面20Bに積層された絶縁層41とを有している。
絶縁層31は、配線層22を被覆するように、コア基板20の上面20Aに積層されている。絶縁層31の厚さは、例えば、コア基板20よりも薄く設定されている。例えば、絶縁層31の厚さは40〜75μm程度とすることができる。絶縁層31は、例えば、補強材入りの絶縁層であって、機械的強度(剛性や硬度等)の高い絶縁層である。また、絶縁層31の材料としては、例えば、補強材が含有されていない熱硬化性樹脂を主成分とする非感光性の絶縁性樹脂を用いることもできる。
配線構造12は、配線構造11の最上層に形成された絶縁層31の上面31Aに積層された配線構造である。配線構造12は、配線構造11よりも配線密度の高い配線層が形成された高密度配線層である。
配線層50は、例えば、同一平面上に、配線パターン50A〜50Cを有している。配線パターン50Aでは、金属層54の表面(上面及び側面)全面が粗化面54Rに形成され、金属膜53の側面全面が粗化面53Rに形成されている。これら粗化面53R,54Rの直下に形成された金属膜52は、その外縁部が粗化面53R,54Rよりも外側に突出するように形成されている。すなわち、配線パターン50Aの金属膜52は、粗化面53R,54Rよりも外側に突出して形成された突出部52Tを有している。この突出部52Tの上面は、粗化面53R,54Rから露出されている。なお、突出部52Tの幅(つまり、金属膜52の外縁部における突出量)は、例えば、0.1〜0.5μm程度とすることができる。
半導体装置100は、配線基板10と、一つ又は複数の半導体チップ101と、アンダーフィル樹脂105と、外部接続端子106とを有している。
次に、図6(a)に示す工程では、絶縁層31の上面31A全面及びビア配線32の上端面32A全面を被覆するようにシード層51を形成する。このシード層51は、例えば、スパッタ法により形成することができる。例えば、本工程では、絶縁層31の上面31Aが平滑面であるため、その上面31Aに対してスパッタ法によりシード層51を均一に形成することができ、シード層51の上面を平滑に形成することができる。このため、粗化面に対してスパッタ法によりシード層51を形成する場合に比べて、シード層51を薄く形成することができる。また、絶縁層31の上面31Aが平坦な面であるため、その上面31A上に微細な(高配線密度な)配線層を容易に形成することができる。
次いで、図11(a)及び図11(b)に示す工程では、絶縁層31の上面31A上に、配線層50の上面の一部を露出する貫通孔61Xを有する絶縁層61を形成する。このとき、図11(b)に示すように、配線層50の表面の一部に粗化面54R,53Rが形成されているため、配線層50の表面全面が平滑面である場合に比べて、絶縁層61と配線層50との密着性を向上させることができる。
次に、図15に示す工程では、配線構造11の最下層の配線層42の所要箇所に画定される外部接続用パッドP2を露出させるための開口部13Xを有するソルダレジスト層13を、絶縁層41の下面41Bに積層する。このとき、ソルダレジスト層13の厚さ(絶縁層41の下面41Bからソルダレジスト層13の下面までの厚さ)は、配線構造12の厚さ(絶縁層31の上面31Aから絶縁層65の上面までの厚さ)と等しい、又は配線構造12の厚さよりも厚く設定されている。ソルダレジスト層13は、感光性のフェノール系樹脂やポリイミド系樹脂からなる。このソルダレジスト層13は、例えば、感光性のソルダレジストフィルムをラミネートし、又は液状のソルダレジストを塗布し、当該レジストを所要の形状にパターニングすることにより形成することができる。これにより、ソルダレジスト層13の開口部13Xから配線層42の一部が外部接続用パッドP2として露出される。
次に、図15に示した構造体を、スライサー等を用いて切断線A2に沿って切断することにより、個片化された複数の配線基板10を得る。
図16に示す工程では、外部接続用パッドP2上に外部接続端子106を形成する。例えば、外部接続用パッドP2上に、適宜フラックスを塗布した後、外部接続端子106(ここでは、はんだボール)を搭載し、240〜260℃程度の温度でリフローして固定する。その後、表面を洗浄してフラックスを除去する。
(1)高密度配線構造である配線構造12内の配線層50,70,80の表面の一部を粗化面に形成した。これにより、配線層50,70,80の表面全面が平滑面である場合に比べて、配線層50,70,80と絶縁層61,63,65との密着性を向上させることができる。その一方で、粗化面を含む配線層50,70,80の表面の粗度を、低密度配線構造である配線構造11内の配線層22,23,42の表面の粗度よりも小さく設定した。これにより、粗化処理に起因して配線層50,70,80の抵抗が上昇することを好適に抑制できる。さらに、粗化処理を行った場合であっても、配線層50,70,80の平面形状を所望の形状に維持することができる。
以下、図17〜図19に従って第2実施形態について説明する。この実施形態では、配線構造12の製造方法が上記第1実施形態と異なっている。以下、第1実施形態との相違点を中心に説明する。先の図1〜図16に示した部材と同一の部材にはそれぞれ同一の符号を付して示し、それら各要素についての詳細な説明は省略する。
(7)貫通孔60X,61Xを充填して階段状の段差が形成されたビア配線を有する配線層70を形成するようにした。これにより、配線層70(ビア配線)と絶縁層60,61との接触面積を増加させることができるため、配線層70(ビア配線)と絶縁層60,61との密着性を向上させることができる。
・上記第2実施形態における2段構造の絶縁層60,61では、貫通孔61Xを貫通孔60Xの平面形状よりも大きく形成することにより、貫通孔60X,61X内に階段状の段差を形成するようにしたが、絶縁層60,61による2段構造はこれに限定されない。
(第3実施形態)
以下、図21〜図23に従って第3実施形態について説明する。この実施形態では、配線構造12の製造方法が上記第1実施形態と異なっている。以下、第1実施形態との相違点を中心に説明する。先の図1〜図20に示した部材と同一の部材にはそれぞれ同一の符号を付して示し、それら各要素についての詳細な説明は省略する。
(8)配線層50,70,80を、金属膜52,72,82の外縁部に突出部52T,72T,82Tが形成された配線パターンのみから構成するようにした。これにより、配線層50,70,80にエレクトロマイグレーションが発生することを好適に抑制することができる。
(第4実施形態)
以下、図25〜図28に従って第4実施形態について説明する。この実施形態では、配線構造12の製造方法が上記第1実施形態と異なっている。以下、第1実施形態との相違点を中心に説明する。先の図1〜図24に示した部材と同一の部材にはそれぞれ同一の符号を付して示し、それら各要素についての詳細な説明は省略する。
続いて、図27(b)に示す工程では、絶縁層31の上面31A上に、配線層50の上面の一部を露出する貫通孔61Xを有する絶縁層61を形成する。このとき、配線層50の表面の一部に粗化面54R,53Rが形成されているため、配線層50の表面全面が平滑面である場合に比べて、絶縁層61と配線層50との密着性を向上させることができる。
以上説明した実施形態によれば、第1実施形態の(1)〜(6)の効果に加えて以下の効果を奏することができる。
なお、上記第1〜第4実施形態は、これを適宜変更した以下の態様にて実施することもできる。
例えば図31(a)に示すように、配線層50が有する粗化面54R,53Rを被覆するように保護膜55を形成してもよい。この場合の保護膜55の表面(上面及び側面)は、粗化面54R,53Rの凹凸に倣って粗化面55Rに形成されている。このため、粗化面55Rの粗度は、例えば粗化面54R,53Rの粗度と同様に、100〜150nm程度となる。このような保護膜55を形成することにより、絶縁層61と配線層50との密着性を向上させることができる。以下に、粗化面54R,53R上に保護膜55としてAl2O3膜を形成した場合の製造方法について説明する。
以下、図34に従って第5実施形態について説明する。この実施形態の配線基板10Aは、配線構造11が配線構造11Aに置換された点が上記第1実施形態と異なっている。以下、第1実施形態との相違点を中心に説明する。先の図1〜図32に示した部材と同一の部材にはそれぞれ同一の符号を付して示し、それら各要素についての詳細な説明は省略する。
(第6実施形態)
以下、図35に従って第6実施形態を説明する。この実施形態の配線基板10Bは、配線構造11が配線構造11Bに置換され、配線構造12が配線構造12Bに置換された点が上記第1実施形態と異なっている。以下、第1実施形態との相違点を中心に説明する。なお、先の図1〜図34に示した部材と同一の部材にはそれぞれ同一の符号を付して示し、それら各要素についての詳細な説明は省略する。
以下、図36に従って第7実施形態を説明する。この実施形態の配線基板10Cは、最上層の配線層の構造が上記第5実施形態と異なっている。以下、第5実施形態との相違点を中心に説明する。なお、先の図1〜図35に示した部材と同一の部材にはそれぞれ同一の符号を付して示し、それら各要素についての詳細な説明は省略する。
次に、図37〜図39に従って、配線基板10Cの適用例について説明する。
まず、図37に従って、配線基板10Cに他の半導体パッケージ200を搭載した半導体装置120について説明する。
半導体パッケージ200は、配線基板210と、その配線基板210に実装された一つ又は複数の半導体チップ220と、配線基板210と半導体チップ220との間に形成されたアンダーフィル樹脂225とを有している。
半導体チップ220は、以上説明した配線基板210にフリップチップ実装されている。すなわち、半導体チップ220の回路形成面(図37では、下面)に配設されたバンプ221をパッドP5に接合することにより、半導体チップ220は、バンプ221を介して配線層214と電気的に接続されている。このようにフリップチップ接合された配線基板210と半導体チップ220との隙間には、アンダーフィル樹脂225が形成されている。
次に、図38に従って、配線基板10Cを電子部品内蔵基板121に適用した場合について説明する。
(適用例3)
次に、図39に従って、電子部品内蔵基板121に、他の半導体パッケージ300を搭載した半導体装置122について説明する。
半導体パッケージ300は、配線基板310と、その配線基板310に実装された一つ又は複数の半導体チップ320と、配線基板310と半導体チップ320との間に形成されたアンダーフィル樹脂325とを有している。
半導体チップ320は、以上説明した配線基板310にフリップチップ実装されている。すなわち、半導体チップ320の回路形成面(図39では、下面)に配設されたバンプ321をパッドP7に接合することにより、半導体チップ320は、バンプ321を介して配線層314と電気的に接続されている。このようにフリップチップ接合された配線基板310と半導体チップ320との隙間には、アンダーフィル樹脂325が形成されている。
なお、上記各実施形態は、これを適宜変更した以下の態様にて実施することもできる。
・上記各実施形態及び上記各変形例を適宜組み合わせるようにしてもよい。例えば、第5実施形態の配線構造11A上に、第2〜第4実施形態の製造方法で製造された配線構造12を積層するようにしてもよい。また、上記第1〜第4実施形態及びそれら変形例の配線基板10、又は第6実施形態の配線基板10Bにおける最上層の配線層に、第7実施形態の配線基板10Cと同様に、接続パッドP3を設けるようにしてもよい。
・上記各実施形態及び上記各変形例における配線構造12,12Bにおける配線層50,70,80,90及び絶縁層60〜65の層数や配線の取り回しなどは様々に変形・変更することが可能である。
11,11A,11B 配線構造
12,12B 配線構造
13 ソルダレジスト層
20 コア基板
22,23,34,36,42,44,46,48 配線層
31,33,35,37,41,43,45,47 絶縁層
31A 上面
31X 貫通孔
32 ビア配線
32A 上端面
50,70,80,90,95 配線層
50A〜50C,70A〜70C,80A〜80C 配線パターン
51,71,81,91 シード層
52,72,82,92 金属膜(金属バリア膜)
53,73,83,93 金属膜
54,74,84,94 金属層
53R,54R,73R,74R,83R,84R 粗化面
53S,54S,73S,74S,83S,84S 平滑面
55,75,85 保護膜
61,63,65 絶縁層
60,62,64 絶縁層
61X,63X,65X 貫通孔
60X,62X,64X 貫通孔
100,120,122 半導体装置
101 半導体チップ
110 導電層
112 レジスト層
112X 開口パターン
Claims (12)
- 第1配線層と、前記第1配線層を被覆する第1絶縁層と、前記第1絶縁層を厚さ方向に貫通して前記第1配線層の上面を露出する第1貫通孔を充填し、前記第1絶縁層から露出された上端面を有するビア配線と、を含む第1配線構造と、
前記第1絶縁層の上面及び前記ビア配線の上端面に形成され、表面の一部が粗化面に形成された第2配線層と、前記第1絶縁層上に積層され、前記第2配線層を被覆する第2絶縁層と、を含む第2配線構造と、を有し、
前記第2配線構造の配線密度は、前記第1配線構造の配線密度よりも高く、
前記粗化面の表面粗度は、前記第1配線層の表面粗度よりも小さいことを特徴とする配線基板。 - 前記第2配線層は、前記第1絶縁層の上面に形成された金属バリア膜と前記金属バリア膜上に形成された金属膜と含むシード層と、前記シード層上に形成された金属層とを有し、
前記第2配線層は、
前記金属膜及び前記金属層の側面が、前記粗化面よりも表面粗度の小さい平滑面に形成され、前記金属バリア膜の側面が、前記平滑面と面一となるように、又は前記平滑面よりも内側に後退するように形成された第1配線パターンを有することを特徴とする請求項1に記載の配線基板。 - 前記第1配線パターンの平滑面上に保護膜が形成されていることを特徴とする請求項2に記載の配線基板。
- 前記第2配線層は、
前記金属膜及び前記金属層の側面が前記粗化面に形成され、前記金属バリア膜の外縁部が前記金属膜及び前記金属層の側面よりも外側に突出された第2配線パターンを有することを特徴とする請求項2又は3に記載の配線基板。 - 前記第2配線層は、
前記金属膜の側面及び前記金属層の表面が前記粗化面と前記平滑面との双方を有する第3配線パターンを有することを特徴とする請求項2〜4のいずれか一項に記載の配線基板。 - 前記第2配線層は、前記第1絶縁層の上面に形成された金属バリア膜と前記金属バリア膜上に形成された金属膜と含むシード層と、前記シード層上に形成された金属層とを有し、
前記第2配線層は、前記金属膜の側面全面及び前記金属層の表面全面が前記粗化面に形成され、前記金属バリア膜の外縁部が前記金属膜及び前記金属層の側面よりも外側に突出された配線パターンのみを有することを特徴とする請求項1に記載の配線基板。 - 前記第2配線構造は、
前記第1絶縁層上に前記第2配線層を被覆するように積層され、前記第2配線層の一部を露出する第2貫通孔を有する第3絶縁層と、
前記第1絶縁層上に前記第3絶縁層及び前記第2配線層を被覆するように積層され、前記第2貫通孔と平面視で重なる位置に前記第2貫通孔よりも平面形状の大きい第3貫通孔が形成された前記第2絶縁層と、
前記第2貫通孔及び前記第3貫通孔を充填するビア配線を有し、前記第2配線層と電気的に接続され、前記第2絶縁層上に積層された第3配線層と、を有することを特徴とする請求項1〜6のいずれか一項に記載の配線基板。 - 前記第1絶縁層は、熱硬化性樹脂を主成分とする非感光性の絶縁性樹脂からなる絶縁層であり、
前記第2絶縁層は、感光性樹脂を主成分とする絶縁層であって、前記第1絶縁層よりも薄い絶縁層であることを特徴とする請求項1〜7の何れか一項に記載の配線基板。 - 請求項1〜8の何れか一項に記載の配線基板と、
前記第2配線構造の最上層の配線層にフリップチップ実装された半導体チップと、
を有することを特徴とする半導体装置。 - 第1配線構造を形成する工程と、
前記第1配線構造の上面に、前記第1配線構造よりも配線密度の高い第2配線構造を積層する工程と、を有し、
前記第1配線構造を形成する工程は、
第1配線層を被覆する第1絶縁層を形成する工程と、
前記第1絶縁層を厚さ方向に貫通し、前記第1配線層の上面を露出する第1貫通孔を形成する工程と、
前記第1貫通孔を充填するとともに、前記第1絶縁層の上面を被覆する導電層を形成する工程と、
前記導電層と前記第1絶縁層の上面とを研磨することにより、前記第1絶縁層の上面を平滑化するとともに、前記第1絶縁層から露出する上端面を有するビア配線を形成する工程と、を有し、
前記第2配線構造を積層する工程は、
前記第1絶縁層の上面及び前記ビア配線の上端面に、金属バリア膜と、金属膜と、金属層とが順に積層された第2配線層を形成する工程と、
前記金属バリア膜に対して前記金属膜及び前記金属層の表面を選択的に粗化する粗化工程と、
前記第1絶縁層の上面に、前記第2配線層を被覆する第2絶縁層を形成する工程と、を有し、
前記粗化工程では、前記金属膜及び前記金属層の表面の粗度が、前記第1配線層の表面の粗度よりも小さくなる範囲内で粗化が行われることを特徴とする配線基板の製造方法。 - 前記粗化工程は、
前記第2配線層のうち、ランド及びベタパターンを含む領域における第2配線層を露出する開口パターンを有するレジスト層を前記第1絶縁層上に形成する工程と、
前記開口パターンから露出された前記金属膜及び前記金属層の表面を粗化する工程と、
前記レジスト層を除去する工程と、を有することを特徴とする請求項10に記載の配線基板の製造方法。 - 前記粗化工程は、
前記第2配線層のうち、ランド及びベタパターンを含む領域における第2配線層を露出する第2貫通孔を有する第3絶縁層を前記第1絶縁層上に形成する工程と、
前記第2貫通孔から露出された前記金属膜及び前記金属層の表面を粗化する工程と、を有し、
前記第2絶縁層を形成する工程では、前記第3絶縁層及び前記第2配線層を被覆し、前記第2貫通孔と平面視で重なる位置に前記第2貫通孔よりも平面形状の大きい第3貫通孔を有する前記第2絶縁層を前記第1絶縁層上に形成し、
前記第2絶縁層を形成する工程の後に、前記第2貫通孔及び前記第3貫通孔を充填するビア配線を有し、前記第2配線層と電気的に接続される第3配線層を形成する工程を有することを特徴とする請求項10に記載の配線基板の製造方法。
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JP7430481B2 (ja) | 2018-05-31 | 2024-02-13 | 新光電気工業株式会社 | 配線基板、半導体装置及び配線基板の製造方法 |
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US9875957B2 (en) | 2018-01-23 |
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US10366949B2 (en) | 2019-07-30 |
US20160020163A1 (en) | 2016-01-21 |
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