JP2016025294A - 半導体パッケージ - Google Patents
半導体パッケージ Download PDFInfo
- Publication number
- JP2016025294A JP2016025294A JP2014150374A JP2014150374A JP2016025294A JP 2016025294 A JP2016025294 A JP 2016025294A JP 2014150374 A JP2014150374 A JP 2014150374A JP 2014150374 A JP2014150374 A JP 2014150374A JP 2016025294 A JP2016025294 A JP 2016025294A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor package
- circuit board
- conductive material
- semiconductor element
- stacked
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0203—Cooling of mounted components
- H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
- H05K1/0206—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate by printed thermal vias
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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- H05K1/14—Structural association of two or more printed circuits
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- H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
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- H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
- H05K2203/1305—Moulding and encapsulation
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Abstract
【解決手段】本発明の一実施形態に係る積層型半導体パッケージは、第1の回路基板と第1の回路基板に実装された第1の半導体素子を含む第1の半導体パッケージと、第2の回路基板と第2の回路基板に実装された第2の半導体素子を含み第1の半導体パッケージに積層された第2の半導体パッケージと、第1の半導体素子上及び第1の半導体素子の周辺の第1の回路基板上に配置される熱伝導材料と、を有する。
【選択図】図1
Description
本発明の実施形態1に係る積層型半導体パッケージ100の概要について、図1乃至図3を参照しながら、詳細に説明する。
図1は、本発明の実施形態1に係る積層型半導体パッケージ100のA−A’(図2参照)断面図を示したものである。図1を参照すると、第1の半導体パッケージ10と第2の半導体パッケージ20が半田ボール31を介して接合され、第1の半導体パッケージ10の上に第2の半導体パッケージ20が積層されていることがわかる。
本発明の実施形態1に係る積層型半導体パッケージ100では、第1の半導体素子12上及び第1の半導体素子12の周辺の第1の回路基板11の一部に、熱伝導材料14が配置される。また、第1の回路基板11にはサーマルビア15が配置され、熱伝導材料14はサーマルビア15と直接又は電極を介して接続される。
本発明の実施形態1に係る積層型半導体パッケージ100では、第1の半導体素子12上及びその周辺の前記第1の回路基板11上に熱伝導材料14が配置されることによって、第1の半導体素子12の上面の発熱を、第1の回路基板11に積極的に伝熱することができる。これによって、第1の半導体素子12から、第1の半導体パッケージ10の上側に配置される第2の半導体パッケージ20の第2の半導体素子22への伝熱を低減することができ、第2の半導体素子22の動作不良を抑制することが可能となる。
本発明の実施形態1に係る積層型半導体パッケージ100の変形例1を、図3を参照しながら詳細に説明する。
本発明の実施形態1に係る積層型半導体パッケージ100の変形例2を、図4を参照しながら詳細に説明する。
本発明の実施形態1に係る積層型半導体パッケージ100の変形例3を、図5を参照しながら詳細に説明する。
本発明の実施形態2に係る積層型半導体パッケージ100の概要について、図6及び図7を参照しながら詳細に説明する。
本発明の実施形態3に係る積層型半導体パッケージ100の概要について、図8を参照しながら詳細に説明する。
本発明の実施形態4に係る積層型半導体パッケージ100の概要について、図9を参照しながら説明する。
本発明の実施形態5に係る積層型半導体パッケージ100の概要について、図10乃至図12を参照しながら説明する。
本発明の実施形態5に係る積層型半導体パッケージ100の変形例を、図12を参照しながら説明する。
本発明の実施形態6に係る積層型半導体パッケージ100の概要について、図13及び図14を参照しながら説明する。
図14は、本発明の実施形態6の変形例に係る積層型半導体パッケージ100の断面図を示したものである。図14を参照すると、第1の半導体パッケージ10の上部に封止樹脂13が充填されており、熱伝導材料14上に積層された低熱伝導層16上に、封止樹脂13が形成されていることがわかる。熱伝導材料14上に低熱伝導層16を形成し、さらに封止樹脂13も形成されるので、図14で示した本発明の実施形態6の変形例に係る積層型半導体パッケージ100は、実施形態6の図13で示した構成よりも、より第1の半導体素子12から第2の半導体素子22への伝熱を低減することが可能となる。
本発明の実施形態7に係る積層型半導体パッケージ100の概要について、図15及び図16を参照しながら説明する。
実施形態7は、実施形態1乃至6のいずれか一つの構成と併用することが可能である。図16は、本発明の実施形態7の変形例に係る積層型半導体パッケージ100の断面図を示したものであり、実施形態1と実施形態7とを組み合わせた構成となっている。すなわち、第1の半導体パッケージ10の上側の面には、第1の半導体素子12及びその周辺の第1の回路基板11上に熱伝導材料14が形成され、第2の半導体パッケージ20の下側の面全体に熱伝導材料14が形成される。
11:第1の回路基板
12:第1の半導体素子
13、23:封止樹脂
14、24:熱伝導材料
15:サーマルビア
16:低熱伝導層
17:接合用電極端子
18:配線
19:導電部材
20:第2の半導体パッケージ
21:第2の回路基板
22:第2の半導体素子
31、35:半田ボール
34:ボンディングワイヤ
100:積層型半導体パッケージ
Claims (9)
- 第1の回路基板と、前記第1の回路基板に実装された第1の半導体素子を含む第1の半導体パッケージと、
第2の回路基板と、前記第2の回路基板に実装された第2の半導体素子を含み、前記第1の半導体パッケージに積層された第2の半導体パッケージと、
前記第1の半導体素子上及び前記第1の半導体素子の周辺の前記第1の回路基板上に配置される熱伝導材料と、
を有する積層型半導体パッケージ。 - 前記第1の半導体パッケージは、前記第2の半導体パッケージと接合し前記第1の半導体素子の周辺に配置される複数の接合用電極端子を有し、
前記熱伝導材料は、前記複数の接合用電極端子の内側に配置される、
ことを特徴とする請求項1に記載の積層型半導体パッケージ。 - 前記第1の回路基板はサーマルビアを有し、
前記熱伝導材料は前記サーマルビアと接する、
ことを特徴とする請求項1に記載の積層型半導体パッケージ。 - 前記サーマルビアは、前記第1の回路基板の電源プレーン又はグランドプレーンと接することを特徴とする、請求項3に記載の積層型半導体パッケージ。
- 前記熱伝導材料は、面方向の熱伝導率が厚さ方向の熱伝導率よりも大きいことを特徴とする、請求項1に記載の積層型半導体パッケージ。
- 前記熱伝導材料は、炭素繊維プリプレグ、炭素繊維シート又はカーボングラファイトシートのうちの何れか一つであることを特徴とする、請求項5に記載の積層型半導体パッケージ。
- 前記熱伝導材料上に、前記熱伝導材料の厚さ方向の熱伝導率よりも熱伝導率が低い層を配置したことを特徴とする、請求項1乃至6の何れか一項に記載の積層型半導体パッケージ。
- 前記熱伝導材料は、平面視において切れ込みを有することを特徴とする、請求項1乃至7の何れか一項に記載の積層型半導体パッケージ。
- 第1の回路基板と、前記第1の回路基板に実装された第1の半導体素子を含む第1の半導体パッケージと、
第2の回路基板と、前記第2の回路基板に実装された第2の半導体素子を含み、前記第1の半導体パッケージに積層された第2の半導体パッケージと、
前記第2の半導体パッケージの前記第1の半導体パッケージと対向する面に配置される熱伝導材料と、
を有する積層型半導体パッケージ。
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JP2014150374A JP6438225B2 (ja) | 2014-07-24 | 2014-07-24 | 半導体パッケージ |
KR1020150099569A KR102098978B1 (ko) | 2014-07-24 | 2015-07-14 | 반도체 패키지 |
CN201510412404.6A CN105304592B (zh) | 2014-07-24 | 2015-07-14 | 半导体封装件 |
TW104122944A TWI681514B (zh) | 2014-07-24 | 2015-07-15 | 半導體封裝 |
US14/803,889 US9635762B2 (en) | 2014-07-24 | 2015-07-20 | Semiconductor package |
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JP2014150374A JP6438225B2 (ja) | 2014-07-24 | 2014-07-24 | 半導体パッケージ |
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