JP5810206B1 - 基板構造およびその製造方法 - Google Patents
基板構造およびその製造方法 Download PDFInfo
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- JP5810206B1 JP5810206B1 JP2014221258A JP2014221258A JP5810206B1 JP 5810206 B1 JP5810206 B1 JP 5810206B1 JP 2014221258 A JP2014221258 A JP 2014221258A JP 2014221258 A JP2014221258 A JP 2014221258A JP 5810206 B1 JP5810206 B1 JP 5810206B1
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- 239000000758 substrate Substances 0.000 title claims abstract description 215
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 44
- 238000004806 packaging method and process Methods 0.000 claims abstract description 65
- 230000002093 peripheral effect Effects 0.000 claims abstract description 32
- 229910052751 metal Inorganic materials 0.000 claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 25
- 239000010410 layer Substances 0.000 claims description 151
- 238000000034 method Methods 0.000 claims description 28
- 229910000679 solder Inorganic materials 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 8
- 239000002356 single layer Substances 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 239000011888 foil Substances 0.000 claims description 4
- 229920001721 polyimide Polymers 0.000 claims description 4
- 238000010030 laminating Methods 0.000 claims description 3
- 230000035515 penetration Effects 0.000 claims 1
- 238000012858 packaging process Methods 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 11
- 238000009423 ventilation Methods 0.000 description 6
- 230000001070 adhesive effect Effects 0.000 description 5
- 239000007788 liquid Substances 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 4
- 230000005855 radiation Effects 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000000191 radiation effect Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/007—Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2457/00—Electrical equipment
- B32B2457/08—PCBs, i.e. printed circuit boards
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
- H01L2224/85005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate being a temporary or sacrificial substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0137—Materials
- H05K2201/0154—Polyimide
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09072—Hole or recess under component or special relationship between hole and component
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0147—Carriers and holders
- H05K2203/0156—Temporary polymeric carrier or foil, e.g. for processing or transferring
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
110、110a 基板
112、112a 貫通孔
114 上面
116 下面
120 キャリア
122 リリース層
124 誘電層
126 金属層
130 パッド
132 ビア
134 回路層
140 パターン化されたはんだマスク(Patterned Solder Mask)
142 開口部
150 表面仕上げ層
160 チップ
162 能動面
164 裏面
170 配線
A1 パッケージング領域
A2 周辺領域
Claims (20)
- リリース層と、金属層と、前記リリース層と前記金属層との間に配置される誘電層とを有するキャリアと、
前記キャリアに配置され、パッケージング領域と複数の貫通孔が設けられた周辺領域とを有する基板とを含み、
前記周辺領域が前記パッケージング領域と連結し、前記パッケージング領域を取り囲み、
前記リリース層が前記基板と前記誘電層との間に位置し、前記基板と前記キャリアとが分離可能なように、前記リリース層と前記誘電層が前記複数の貫通孔に充填される基板構造。 - 前記リリース層の材料はアルミホイル、或いはポリイミド(Polymide)フィルムを含む請求項1に記載の基板構造。
- 前記基板が単層回路基板である請求項1或いは請求項2に記載する基板構造。
- 前記基板が多層回路基板である請求項1或いは請求項2に記載する基板構造。
- 前記基板がさらに複数のパッドとパターン化されたはんだマスクを含み、前記複数のパッドが前記基板の前記パッケージング領域の上面に配置され、前記パターン化されたはんだマスクが前記上面を覆い、前記複数のパッドを露出する請求項1〜請求項4のいずれか1項に記載の基板構造。
- 前記基板が前記パッドを覆う表面仕上げ層を含む請求項5に記載の基板構造。
- パッケージング領域と、前記パッケージング領域と連結し前記パッケージング領域を取り囲む周辺領域とを有する基板を提供する工程と、
前記周辺領域に複数の貫通孔を形成する工程と、
リリース層と、金属層と、前記リリース層と前記金属層との間に配置された誘電層とを有するキャリアを提供する工程と、
前記基板と前記キャリアとが分離可能なように、前記リリース層と前記誘電層を前記複数の貫通孔に充填し、前記基板を前期キャリアの前期リリース層に積層する工程と、
を含む基板構造の製造方法。 - 前記基板が単層回路基板である請求項7に記載の基板構造の製造方法。
- 前記基板が多層回路基板である請求項7に記載の基板構造の製造方法。
- 前記基板を提供する工程が更に、前記基板の前記パッケージング領域の上面に複数のパッドを形成する工程と、
前記複数のパッドを露出するパターン化されたはんだマスクを前記上面に形成する工程と、を含む請求項7〜請求項9のいずれか一項に記載の基板構造の製造方法。 - 前記基板を提供する工程が更に、前記パッドを覆う表面仕上げ層を形成する工程を含む請求項10に記載の基板構造の製造方法。
- リリース層と、金属層と、前記リリース層と前期金属層との間に配置された誘電層とを有するキャリアと、
周辺領域と、複数の貫通孔が設けられたパッケージング領域とを有する、前記キャリアに配置される基板とを含み、
前記周辺領域が前記パッケージング領域と連結し、前記パッケージング領域を取り囲み、
前記リリース層が前記基板と前記誘電層との間に位置し、前記基板と前記キャリアとが分離可能なように、前記リリース層と前記誘電層とが前記パッケージング領域に位置する前記複数の貫通孔に充填される、基板構造。 - 前記基板が複数のパッドとパターン化されたはんだマスクを更に含み、前記複数のパッドが前記基板の前記パッケージング領域の上面の前記複数の貫通孔の周囲に配置され、パターン化されたはんだマスクが前記上面を覆い、前記複数のパッドを露出する、請求項12に記載の基板構造。
- 前記パッケージング領域に配置し、前記複数の貫通孔の一つを覆い、前記リリース層と接触するチップを更に含み、前記チップが複数の配線で電気的に前記パッドと接続する、請求項12或いは請求項13に記載する基板構造。
- 前記リリース層の材料はアルミホイル、或いはポリイミド(Polymide)フィルムを含む、請求項12〜請求項14のいずれか一項に記載の基板構造。
- 前記基板が単層回路基板である、請求項12〜請求項15のいずれか一項に記載の基板構造。
- 前記基板が多層回路基板である、請求項12〜請求項15のいずれか一項に記載の基板構造。
- パッケージング領域と、前記パッケージング領域と連結し、前記パッケージング領域を取り囲む周辺領域とを有する基板を提供する工程と、
前記パッケージング領域に複数の貫通孔を形成する工程と、
リリース層と、金属層と、前記リリース層と前記金属層との間に配置される誘電層と、を有するキャリアを提供する工程と、
前記基板と前記キャリアとが分離可能なように、前記リリース層と前記誘電層を前記複数の貫通孔に充填し、前記基板を前期キャリアの前期リリース層に積層する工程と、
を含む基板構造の製造方法。 - 前記基板を提供する工程が更に、前記基板の前記パッケージング領域内の上面の前記複数の貫通孔の周囲に複数のパッドを形成する工程と、前記複数のパッドを露出する図面化されたはんだマスクを前記上面に形成する工程と、を含む請求項18に記載の基板構造の製造方法。
- チップを前記基板の前記パッケージング領域に配置する工程と、
前記チップを複数の配線で電気的に前記パッドと接続する工程とを更に含み、
前記チップが前記複数の貫通孔の一つを覆い、前記リリース層と接触する、請求項18〜請求項19のいずれかの一項に記載の基板構造の製造方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW103113683A TWI512924B (zh) | 2014-04-15 | 2014-04-15 | 基板結構及其製作方法 |
TW103113683 | 2014-04-15 |
Publications (2)
Publication Number | Publication Date |
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JP5810206B1 true JP5810206B1 (ja) | 2015-11-11 |
JP2015204454A JP2015204454A (ja) | 2015-11-16 |
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JP2014221258A Active JP5810206B1 (ja) | 2014-04-15 | 2014-10-30 | 基板構造およびその製造方法 |
Country Status (4)
Country | Link |
---|---|
US (2) | US20150296618A1 (ja) |
JP (1) | JP5810206B1 (ja) |
CN (1) | CN105023873B (ja) |
TW (1) | TWI512924B (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
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CN204014250U (zh) * | 2014-05-16 | 2014-12-10 | 奥特斯(中国)有限公司 | 用于生产电子元件的连接系统的半成品 |
KR102179165B1 (ko) | 2017-11-28 | 2020-11-16 | 삼성전자주식회사 | 캐리어 기판 및 상기 캐리어 기판을 이용한 반도체 패키지의 제조방법 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW563233B (en) * | 2002-09-11 | 2003-11-21 | Advanced Semiconductor Eng | Process and structure for semiconductor package |
TWI264805B (en) * | 2005-02-14 | 2006-10-21 | Phoenix Prec Technology Corp | Method for fabricating carrier embedded with semiconductor chip |
TWI303146B (en) * | 2006-11-23 | 2008-11-11 | Subtron Technology Co Ltd | Wiring board with high thermal conductivity and process thereof |
TWI394245B (zh) * | 2009-02-05 | 2013-04-21 | Unimicron Technology Corp | 封裝基板及其製法 |
TWI399140B (zh) * | 2009-06-12 | 2013-06-11 | Unimicron Technology Corp | 內埋式封裝結構的製作方法 |
CN102376677B (zh) * | 2010-08-20 | 2013-07-10 | 旭德科技股份有限公司 | 半导体封装结构及半导体封装结构的制作方法 |
CN205028884U (zh) * | 2014-02-13 | 2016-02-10 | 群成科技股份有限公司 | 电子封装件与封装载板 |
-
2014
- 2014-04-15 TW TW103113683A patent/TWI512924B/zh not_active IP Right Cessation
- 2014-05-26 US US14/287,071 patent/US20150296618A1/en not_active Abandoned
- 2014-06-18 CN CN201410272685.5A patent/CN105023873B/zh active Active
- 2014-10-30 JP JP2014221258A patent/JP5810206B1/ja active Active
-
2017
- 2017-07-13 US US15/648,465 patent/US9883594B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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CN105023873A (zh) | 2015-11-04 |
TWI512924B (zh) | 2015-12-11 |
US20150296618A1 (en) | 2015-10-15 |
TW201539682A (zh) | 2015-10-16 |
US9883594B2 (en) | 2018-01-30 |
CN105023873B (zh) | 2018-02-02 |
US20170311450A1 (en) | 2017-10-26 |
JP2015204454A (ja) | 2015-11-16 |
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