1303146 21369twf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種線路板及其製程，且特別是有關 於一種具有高導熱性之線路板及其製程。 【先前技術】 在電子裝置中，晶片所產生的廢熱必須即時地移除， 否則這些廢熱將使得晶片之溫度提高，因而導致晶片暫時 或永久喪失其功能。因此，為了迅速地將晶片所產生之廢 熱移除，以降低晶片之溫度，外加之散熱器及風扇已經常 用來解決這樣的問題。 然而，對於積體電路（1C)晶片而言，在某些空間的 限制之下，散熱器亦可能無法直接安裝在IC晶片上來移除 1C晶片所產生的廢熱。在這樣的情況下，IC晶片之廢熱僅 月b夠透過其底部之晶片承載器或線路板來加以導出。 此外，對於發光二極體（led)晶片而言，由於lED 晶片之功能是絲《光線，所以無法將餘器直接安裝 在LED晶 >；之上方’否職絲會擋住LED晶片所發出 之光線。、因此’ LED晶片之廢_能約透過其底部之晶片 承載器或線路板來加以導出。 接安裝ΐ熱器之IC晶片或上方必須淨空的 =遞之功能以外，其對於晶片=的基= ΐ熱==統的印刷線路板或封裝基板内的絕緣層之 1303146 21369twf.doc/n 【發明内容】 線路ΐ發明提供—種線路難程，以製作具有高導熱性之 j明提供—種線路板，其具有 鑽孔及鍍銅的製作成本。 低成本製作而不需要機械 馬違上述或是其他目的， 程，包括：將-接著層、-離形層發月路板Ϊ :介電層及-導電板依序重疊在一支撐mi 接著層、另—離形層、另二气面第並 介電層及另一暮恭祐俨皮舌晶矣 冷私層、另一弟一 -第二面，甘士Γ ) @在支撐板之相對於第一面的 一導電θ*，·、母個導電板之朝向支撐板的部分構成一第 導電板融化這些接著層及這些介電層，同時對這些 分及==!施壓’使得這些第-導電層之部 得融化_此第一=別Γ入融化之這些接著層，並使 案之备μ二弟”電層之邛分分別填入這些第一導電圖 固化間中；在融化這些接著層及這些介電層之後， 每個導㈣及這些介電層；_化這些導電板，使得 案；脸'f之對應第一導電圖案的部分形成一第二導電圖 板之丄第—介電層及—第二導電層依序重疊在這些導電 ’並將另-第二介電層及另—第二導電層依序重 UUJ146 21369twf.doc/n 疊在這些導電板之另〜 化的這些第二介電層 j化這些第二介電層，使得融 負片空間中；固化這些別填入這些第二導電圖案之 層分別物理性地剝離一介電層；以及將這些第一導電 在本發明之-貧心= 一面以前，將導電板之朝 在重豐導電板在支撐板之第 形成第一導線圖案。 σ 撐板的部分以半蝕刻的方式 在本發明之一實施例中 這些第一導電層之突屮’線路板製程更可包括··移除 分、這歧第—介刀、這些第一介電層之突出部 二 層之突出部分及這此第- 部分，以暴露出這4b第—道二弟一 V電層之犬出 圖案之部分。上述=除及這些第二導電 化施财，魏板製程更可包括：圖案 化心弟4電層及這些第二導電層。此外，線路板製程 更可Ο括·將防銲罩幕覆蓋在第—導電層上；以及將另 Ρ方銲罩幕覆蓋在第二導電層上。另外，這些防銲罩幕之 一具有反光性，或者這些防銲罩幕之一的表面呈現白色。 在本發明之一實施例中，第一導電圖案可構成一接合 墊，線路板製程更可包括：將一金屬保護層覆蓋接合墊所 暴露出的表面。此外，第二導電圖案構成一接合墊，線路 板製程更包括：將一金屬保護層覆蓋接合墊所暴露出的表 面 在本發明之一實施例中，線路板製程更可包括：形成 至少一導電通孔，其貫穿第一介電層及第二介電層，用以 1303146 21369twf.doc/n 電性導電層及第二導電層。 在本發明之—告 屬，例如銅、銷戈汽也 撐板之材質可為膠片或金 這些接著層可為膠片。 這些導電板之材質可為金 這些導電板之厚度範圍可為BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a circuit board and a process thereof, and more particularly to a circuit board having high thermal conductivity and a process therefor. [Prior Art] In an electronic device, the waste heat generated by the wafer must be removed instantaneously, otherwise the waste heat will increase the temperature of the wafer, thereby causing the wafer to temporarily or permanently lose its function. Therefore, in order to quickly remove the waste heat generated by the wafer to lower the temperature of the wafer, additional heat sinks and fans have often been used to solve such problems. However, for integrated circuit (1C) wafers, under certain space constraints, the heat sink may not be directly mounted on the IC wafer to remove the waste heat generated by the 1C wafer. In such a case, the waste heat of the IC wafer can be derived only through the wafer carrier or circuit board at the bottom thereof. In addition, for a light-emitting diode (LED) wafer, since the function of the lED wafer is silk "light, it is impossible to mount the residual device directly on the LED crystal"; above the 'nothing wire' will block the LED chip Light. Therefore, the waste of the LED chip can be derived from the wafer carrier or circuit board at the bottom. In addition to the function of the IC chip on which the heater is mounted or the upper surface that must be cleaned, it is 1303146 21369 twf.doc/n of the insulating layer in the printed circuit board or package substrate for the wafer = base = = = = = SUMMARY OF THE INVENTION The circuit ΐ invention provides a kind of circuit difficulty to produce a circuit board with high thermal conductivity, which has the manufacturing cost of drilling and copper plating. Low-cost production without the need for mechanical horses to violate these or other purposes, including: the lining layer, the delamination layer, the dielectric layer and the conductive plate are sequentially superimposed on a support mi. , another - the release layer, the other two gas surface and the dielectric layer and another 暮 俨 俨 俨 俨 舌 舌 、 、 、 、 、 、 、 、 、 、 、 、 、 另一 另一 另一 另一 另一 另一 另一 另一 另一 另一 另一 另一 另一 另一 另一 另一 另一 另一a conductive θ* of the first surface, a portion of the mother conductive plate facing the support plate constitutes a first conductive plate to melt the adhesive layers and the dielectric layers, and simultaneously presses these points and ==! - the part of the conductive layer is melted _ this first = do not break into these melted layers, and make the 二 弟 ” ” ” ” ” ” ” ” 电 电 电 电 填 填 填 填 填 这些 这些 这些 这些 这些After the layer and the dielectric layers, each of the conductive layers (four) and the dielectric layers; _ these conductive plates, so that the portion of the face corresponding to the first conductive pattern forms a second conductive pattern - The dielectric layer and the second conductive layer are sequentially overlapped on the conductive layers and the other second dielectric layer and the other second conductive Substituting UUJ146 21369twf.doc/n these second dielectric layers stacked on the conductive plates to form the second dielectric layers so that they are melted into the negative space; curing these other conductive patterns The layers are physically stripped of a dielectric layer, respectively; and the first conductive is formed in the first conductive pattern toward the heavy conductive plate at the first of the support plates before the one side of the present invention. The portion of the σ strut in a half-etched manner in an embodiment of the present invention, the abrupt 'circuit board process of the first conductive layer may further include · removing points, the dislocation - the first knives, the first a protruding portion of the second layer of the protruding portion of the electric layer and the first portion thereof to expose a portion of the dog-out pattern of the 4b-second two-one electric layer. The above = except for the second conductive wealth, The Weiban process can further include: patterning the fourth electrical layer and the second conductive layer. In addition, the circuit board process can further include: covering the solder mask on the first conductive layer; and welding another square The mask is covered on the second conductive layer. In addition, these solder masks In one embodiment of the present invention, the first conductive pattern may constitute a bonding pad, and the circuit board process may further include: covering a metal protective layer. The exposed surface of the bonding pad. In addition, the second conductive pattern constitutes a bonding pad, and the circuit board process further comprises: covering a surface of the bonding pad with a metal protective layer. In an embodiment of the invention, the circuit board process The method further includes: forming at least one conductive via extending through the first dielectric layer and the second dielectric layer for the 1303146 21369 twf.doc/n electrically conductive layer and the second conductive layer. For example, the material of the copper, the pin and the steam can also be film or gold. The adhesive layer can be film. The material of the conductive plate can be gold. The thickness of the conductive plate can be
Kb 一實施例中 屬例如銅、知4 鍩或不鏽鋼。 Q25i=k—實施例中 〇·25至1釐米。In one embodiment, Kb is, for example, copper, bismuth or stainless steel. Q25i = k - in the examples 〇 25 to 1 cm.
在本發明> _ L 第一導電層之相些第—介電層之一及這些 片。 料所構成的合成材财為-覆飼樹脂 第二實施例中’這些第二介電層之-及這些 片。當這4 =所構成的合成材料可為-覆銅樹脂 構成的合itr層之—及這些第二導電層之相鄰者所 導電層:=:覆:樹脂片時’在第二介電層及第二 露出對應之第少，’其暴 施例f，第二_案可包括依序重 為達上述或是其他目的，本發明更提出一種線路板， 包括·-導電板，包括―第—導電圖案及—第二導電圖案， 其依序重疊；一第一介電層，位於第一導電圖案之負片空 間中；一第二介電層，位於第二導電圖案之負片空間中了 一圖案化之第一導電層，配置於第一介電層及第一導電圖 9 1303146 21369twf.doc/n 案之表面；以及一圖案化之第二導電層，配置於第二介電 層及第二導電圖案之表面。 在本發明之一實施例中，線路板可為平面柵格陣列基 板、四方扁平無接腳基板、球柵格陣列基板或發光二極體 晶片載板。 在本發明之一實施例中，這些導電板之材質可為金 屬，例如銅、鋁或不鏽鋼。 在本發明之一實施例中，第一導電圖案可具有至少一 接合墊。接合墊可為一晶片接合墊、一導線接合墊或一覆 晶接合墊。線路板更可包括一金屬保護層，覆蓋接合墊所 暴路出的表面。 在本發明之一實施例中，第二導電圖案可具有至少一 ，合墊。接合墊可為一晶片接合墊、一導線接合墊或一覆 曰曰接合墊。線路板更可包括一金屬保護層，覆蓋接合墊所 暴路出的表面。 在本發明之一實施例中，線路板更可包括：一防銲罩 幕，覆蓋第一導電層；以及另一防銲罩幕，覆蓋第二導電 層。廷些防銲罩幕之一具有反光性，或者這些防銲罩幕之 一的表面呈現白色。 在本發明之一實施例中，線路板更可包括：至少一導 電通孔，貫穿第一介電層及第二介電層，用以電性連接第 一導電層及第二導電層。 本發明之線路板製程除可製作出具有導電核心之線 路板之外’還可歷經單一製程週期後製作兩片線路板，因 1303146 21369twf.doc/n 而降低線路板製作成本。此外，本發明之線路板可藉由導 電板來提高導熱性，故可應用於承載高熱功率之晶片，例 如LED晶片。 為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉一實施例，並配合所附圖式，作詳細說明 如下。 【實施方式】 B 圖1A至圖1J繪示本發明之一實施例之一種線路板製 程。请參考圖1A，首先將一接著層（adhesive layer) 102、 一離形層（release layer) 104、一第一導電層 106、一第一 介電層108及一導電板（conductive panel) 110依序重叠 在一支撐板100之一第一面l〇〇a，並將另一接著層102、 另一離形層104、另一第一導電層106、另一第一介電層 108及另一導電板11〇依序重疊在支撐板100之相對於第 一面100a的一第二面i〇〇b。 • 上述支撐板100可提供暫時的支撐。支撐板100之材 質可為膠片或金屬，例如銅、紹或不鐘鋼等。此外，這些 接著層102可於融化後變形接著再固化。這些接著層102 例如是膠片（prepreg)。另外，這些接著層104可提供暫 時性的結合介面，並在製程結束後，以利將這些接著層102 上之這些第一導電層106分別從這些接著層102上物理性 地剝離（physically peel)。 在本實施例中，這些第一導電層106可構成線路板之 11 1303146 21369twf.doc/n 線路，而這些第一導電層106之材質例如為銅。此外，這 些第一介電層108可於融化後變形接著再固化，並構成線 路板之介電層，而這些第一介電層108之材質可為樹脂。 值付庄思的是’ 一覆銅樹脂片（Resin Coated Copper，RCC ) 可應用作為一包括第一導電層1〇6及第一介電層1〇8之複 合層（compound layer) 109。 母個導電板110之朝向支撐板100的部分構成一第一 導電圖案（conductive pattern) 110a，其可構成多個接合墊 111a及111b’其中這些接合塾ηia及1 ία可作為晶片接 合塾（die bonding pad)、導線接合墊（wire b〇nding pad) 或覆晶接合塾（flip chip bonding pad)。在本實施例中， 可採用半钱刻（half-etching)的方式將這些第一導電圖案 ll〇a分別形成在這些導電板11〇上，這部分將於下文配合 圖式作更清楚的說明。此外，這些導電板11〇之厚度範圍 例如為0.125至1釐米。 凊參考圖1B，融化這些接著層1〇2及這些介電層 108,同時對這些導電板11〇朝向支撐板1〇()之方向施壓， 使得這些第一導電層106之部分及這些第一導電圖案110a 分別陷入融化的這些接著層1〇2,並使得融化的這些第一 介電層108之部分分別填入這些第一導電圖案11〇a之負片 空間中。此處所指的負片空間是相對於這些第一導電圖案 110a為正片圖案而言。在本實施例中，融化這些接著層1〇2 及這些介電層108可採用加熱或其他方式。 請同樣參考圖1B，在融化這些接著層1〇2及這些介 12 1303146 21369twf.doc/n 電層108之後，固化這些接著層1〇2及這些 在本實施例中’固化這些接著層1〇2及 日 可採用加誠其财式。 ~ I H 108亦 請參考圖1C，圖案化這些導雷無 板110之對應第-導電圖案咖的 成使^每，導電 案1勘。每個第二導電圖案110b ^成一弟二導電圖 及與其相疊之另-次導電_ 11Gb，，額案贈 圖案110b，可構成線路板之導電核心=中較内側之導電 案贿，則可構成多個接合整叫及’1較外歉導電圖 墊Ilia及111b可作為晶片接入參 其_這些接合 合墊。在本實施例中St ^導線接合墊或覆晶接 二導電圖案u〇b分別形成在這方式將這些第 請參考圖m，將一第二介電 114依序重疊在這些導電板11〇之— 帛-導電層 層112及另一第二導電声114 並將另一第二介電 之另一。 曰 、序重豐在這些導電板110 在本實施例中，這些第二介 =著再固化，並構成線路板之介化後變形 112之材質可為樹月旨。此外 ：，二弟二介電層 成線路板之線路， Q f二¥電層114則可構 銅。值得注音的是導電層106之材質例如為 包，介二應用作2 當第二導電圖案11〇 ^之複口層U5。 的接合墊llla日士/、 久蛉電圖案110b，，之部分構成 ^可在複合層115上預先形成_ = 13 1303146 21369twf.doc/n 115a。因此，當這些複合層115分別重疊在對應之導電板 110上時，這些開口 115a將分別暴露出對應之第二導電圖 案110b之次導電圖案ll〇b”的接合墊111a。值得注意的 是，在其他實施例中，複合層亦可不預先形成開口 H5a 而直接重疊在對應之導電板110上。舉例而言，複合層115 直接重疊在次導電圖案110b”的接合墊lllb上。 請參考圖1E，融化這些第二介電層112，使得融化的 這些第二介電層112之部分分別填入這些第二導電圖案 110b之負片空間中。此處所指的負片空間是相對於這些第 一導電圖案ii〇b為正片圖案而言。當第二導電圖案n〇b 具有這些次導電圖案110b’及110b，，時，此處所指的負片空 間則是相對於這些次導電圖案ll〇b，及ll〇b”為正片圖案 而言。在本實施例中，融化這些第二介電層1丨2可採用加 熱或其他方式。 請同樣參考圖1E，在融化這些第二介電層112之後， 固化這些苐—介電層112。在本實施例中，固化這些第二 ► 介電層112亦可採用加熱或其他方式。 ★ 請參考圖1F，將這些第一導電層1〇6分別物理性地剝 離（peel)自這些離形層1〇4。至此，出現線路板5〇之雛 其包括第一導電層106、第一介電層108、導電板11〇、 第—介電層112及第二導電層114。 明參考圖1G，在圖1B及圖1E之多次融化及固化的 /驟之後’移除第_導電層觸之突出部分、第一介電層 8之犬出部分、第二介電層112之突出部分及第二導電 1303146 21369twf.doc/n 層114之突出部分，以暴露出這些接合墊111a、111b、 111a及111b 。在本實施例中，上述移除步驟可採用研 磨（polishing) ’ 例如帶磨法（beit_san(jing)。In the present invention < _ L one of the first dielectric layers of the first conductive layer and the sheets. The composite material composed of the material is - the resin-coated resin in the second embodiment - and these sheets. When the 4 = synthetic material can be composed of a copper-clad resin composed of the itr layer - and the adjacent conductive layer of the second conductive layer: =: coating: resin sheet 'on the second dielectric layer And the second exposure corresponding to the first, 'the violent application f, the second _ case may include the sequential weight for the above or other purposes, the present invention further proposes a circuit board, including · - conductive plate, including - a conductive pattern and a second conductive pattern, which are sequentially overlapped; a first dielectric layer is located in the negative space of the first conductive pattern; and a second dielectric layer is located in the negative space of the second conductive pattern a patterned first conductive layer disposed on the surface of the first dielectric layer and the first conductive pattern 9 1303146 21369 twf.doc/n; and a patterned second conductive layer disposed on the second dielectric layer and The surface of the two conductive patterns. In an embodiment of the invention, the circuit board may be a planar grid array substrate, a quad flat no-substrate substrate, a ball grid array substrate or a light-emitting diode wafer carrier. In one embodiment of the invention, the conductive plates may be of a metal such as copper, aluminum or stainless steel. In an embodiment of the invention, the first conductive pattern may have at least one bond pad. The bond pad can be a die bond pad, a wire bond pad or a flip bond pad. The circuit board may further include a metal protective layer covering the surface from which the bonding pad is exposed. In an embodiment of the invention, the second conductive pattern may have at least one pad. The bond pad can be a die bond pad, a wire bond pad or a bond pad. The circuit board may further include a metal protective layer covering the surface from which the bonding pad is exposed. In an embodiment of the invention, the circuit board may further include: a solder mask to cover the first conductive layer; and another solder mask to cover the second conductive layer. One of the solder masks is reflective, or the surface of one of these solder masks is white. In an embodiment of the invention, the circuit board further includes: at least one conductive via extending through the first dielectric layer and the second dielectric layer for electrically connecting the first conductive layer and the second conductive layer. The circuit board process of the present invention can produce two circuit boards after a single process cycle, except that a circuit board having a conductive core can be fabricated. The circuit board manufacturing cost is reduced by 1303146 21369 twf.doc/n. Further, the wiring board of the present invention can be used for carrying a high thermal power wafer such as an LED wafer by a conductive plate for improving thermal conductivity. The above and other objects, features, and advantages of the present invention will become more apparent from the understanding of the appended claims. [Embodiment] FIG. 1A to FIG. 1J illustrate a circuit board process according to an embodiment of the present invention. Referring to FIG. 1A, an adhesive layer 102, a release layer 104, a first conductive layer 106, a first dielectric layer 108, and a conductive panel 110 are first placed. The sequence overlaps one of the first faces 10a of the support plate 100, and the other subsequent layer 102, the other release layer 104, the other first conductive layer 106, the other first dielectric layer 108, and the other A conductive plate 11 is sequentially overlapped on a second surface i 〇〇 b of the support plate 100 with respect to the first surface 100a. • The above support plate 100 provides temporary support. The material of the support plate 100 may be film or metal, such as copper, shovel or stainless steel. In addition, these subsequent layers 102 can be deformed after melting and then cured. These adhesive layers 102 are, for example, prepregs. In addition, these bonding layers 104 may provide a temporary bonding interface and, after the end of the process, facilitate the physical peeling of the first conductive layers 106 on the bonding layers 102 from the bonding layers 102, respectively. . In this embodiment, the first conductive layers 106 may constitute 11 1303146 21369 twf.doc/n lines of the circuit board, and the materials of the first conductive layers 106 are, for example, copper. In addition, the first dielectric layer 108 may be deformed and then cured after being melted, and constitute a dielectric layer of the circuit board, and the material of the first dielectric layer 108 may be a resin. The value of the singularity is that a Resin Coated Copper (RCC) can be applied as a compound layer 109 including a first conductive layer 1〇6 and a first dielectric layer 1〇8. The portion of the mother conductive plate 110 facing the support plate 100 constitutes a first conductive pattern 110a, which may constitute a plurality of bond pads 111a and 111b', wherein the joints 塾η and ία may serve as wafer bonding pads (die) Bonding pad), wire b〇nding pad or flip chip bonding pad. In this embodiment, the first conductive patterns 11〇a may be formed on the conductive plates 11〇 in a half-etching manner, which will be more clearly explained below with reference to the drawings. . Further, the thickness of these conductive plates 11 is, for example, 0.125 to 1 cm. Referring to FIG. 1B, the bonding layers 1 and 2 and the dielectric layers 108 are melted while pressing the conductive plates 11A toward the support plate 1 to make portions of the first conductive layers 106 and the first portions. A conductive pattern 110a is respectively trapped in the melted subsequent layers 1〇2, and portions of the melted first dielectric layers 108 are respectively filled in the negative spaces of the first conductive patterns 11〇a. The negative space referred to herein is a positive pattern with respect to these first conductive patterns 110a. In this embodiment, the subsequent layers 1 〇 2 and the dielectric layers 108 may be melted or otherwise. Referring also to FIG. 1B, after the subsequent layers 1 and 2 and the dielectric layers 108 are melted, the subsequent layers 1 and 2 are cured and these are cured in the present embodiment. 2 and the day can be used to increase their wealth. ~ I H 108 Please also refer to FIG. 1C to pattern the corresponding conductive and conductive patterns of the conductive conductive plateless plates 110. Each of the second conductive patterns 110b is formed into a second conductive pattern and a second-order conductive_11Gb stacked thereon, and the case-sending pattern 110b may constitute a conductive core of the circuit board = a conductive one in the inner side of the circuit board. A plurality of joint splicing and "1" apology conductive pads Ilia and 111b can be used as wafer bonding electrodes. In this embodiment, the St-wire bonding pad or the flip-chip bonding conductive pattern u〇b are respectively formed in this manner. Referring to the above-mentioned reference drawing m, a second dielectric 114 is sequentially superposed on the conductive plates 11 — 帛-conductive layer 112 and another second conductive sound 114 and the other second dielectric. In the present embodiment, the second dielectric material is re-cured, and the material of the dielectric deformation 112 which constitutes the wiring board can be a tree. In addition: the second brother and the second dielectric layer are connected to the circuit board, and the Q f 2 electric layer 114 can form copper. It is worth noting that the material of the conductive layer 106 is, for example, a package, and the second layer is used as the double layer U5 of the second conductive pattern 11〇. The bonding pad 111a//, the long-lasting electric pattern 110b, the part of the composition ^ can be formed on the composite layer 115 in advance _ = 13 1303146 21369twf.doc/n 115a. Therefore, when the composite layers 115 are respectively overlapped on the corresponding conductive plates 110, the openings 115a will respectively expose the bonding pads 111a of the corresponding conductive patterns 11b" of the corresponding second conductive patterns 110b. It is worth noting that In other embodiments, the composite layer may also be directly overlaid on the corresponding conductive plate 110 without previously forming the opening H5a. For example, the composite layer 115 directly overlaps the bonding pad 111b of the secondary conductive pattern 110b". Referring to FIG. 1E, the second dielectric layers 112 are melted such that portions of the melted second dielectric layers 112 are filled into the negative spaces of the second conductive patterns 110b, respectively. The negative space referred to herein is a positive pattern with respect to these first conductive patterns ii 〇 b. When the second conductive pattern n〇b has the sub-conductive patterns 110b' and 110b, the negative space referred to herein is relative to the sub-conductive patterns 11b, and ll〇b" is a positive pattern. In this embodiment, the second dielectric layer 1 2 may be melted or otherwise heated. Referring also to FIG. 1E, after the second dielectric layer 112 is melted, the germanium-dielectric layer 112 is cured. In this embodiment, the second ► dielectric layer 112 may be cured by heating or other means. Referring to FIG. 1F, the first conductive layers 1〇6 are physically peeled from the release layers. 1〇 4. At this point, the circuit board 5 includes a first conductive layer 106, a first dielectric layer 108, a conductive plate 11A, a first dielectric layer 112, and a second conductive layer 114. Referring to FIG. 1G Removing the protruding portion of the first conductive layer, the canine portion of the first dielectric layer 8, the protruding portion of the second dielectric layer 112, and after the plurality of melting and curing/steps of FIG. 1B and FIG. 1E a second conductive portion 1303146 21369 twf.doc/n protruding portion of layer 114 to expose the bonding pads 11 1a, 111b, 111a and 111b. In the present embodiment, the above removal step may employ a polishing method such as a belt grinding method (beit_san (jing).
請參考圖1H，圖案化（pattern)第一導電層1〇6及第 二導電層114,以構成線路板5〇之線路於其相對兩面。在 本實施例中，圖案化之步驟可包括微影（photolithography) 及蝕刻（etching)。除了第一導電圖案n〇a及第二導電圖 案ll〇b之次導電圖案麗，，可構成這些接合墊uia、 lllb、llla及lilb’以外，在其他實施例中已圖案化 之第二導電層1G6及第二導電層114亦可包括多個接合塾。 々:，考圖II為了保護已圖案化之第一導電層1Q6及 第-導電層114所構成的線路，更可將—防銲罩幕（祕er mask)★覆蓋116在第一導電層1〇6上，並將另一防銲罩 116覆蓋在第二導電層114上。Referring to FIG. 1H, the first conductive layer 1〇6 and the second conductive layer 114 are patterned to form lines of the circuit board 5〇 on opposite sides thereof. In this embodiment, the step of patterning may include photolithography and etching. In addition to the second conductive pattern n〇a and the second conductive pattern 11b, the second conductive pattern may be patterned in other embodiments, in addition to the bonding pads uia, 111b, 111a, and lilb'. The layer 1G6 and the second conductive layer 114 may also include a plurality of bonding pads. 々: In order to protect the circuit formed by the patterned first conductive layer 1Q6 and the first conductive layer 114, a solder mask can be covered 116 in the first conductive layer 1 On the crucible 6, another solder mask 116 is overlaid on the second conductive layer 114.
"月參考圖U’為了保護這些接合塾11 la、11 lb、11 ia, flnb，所暴露出之表面，更可將多個金屬保護層（metal flmsh)118覆蓋這些接合墊ma、出b、llla，及lllb， 所暴露出的表面。在本實闕巾， 些金屬保護層118形成在這些接合墊ma、 ίΓΓ層繼崎®。這蝴簡118例如為鎳 在，路板50完成製作之後，還可依照需 i:11)、線路板50成為多個個別的線路板單元3 早片化之步驟可為切斷（eut)或衝斷（pug)等。上迷 15 1303146 21369twf.doc/n 線路板50可作為平面栅格陣列（LGA)基板、四方 扁平無接腳（QFN)基板、球柵格陣列（BGA)基板或發 光二極體晶片載板。當線路板50應用作為一發光二極體晶 片載板時，為了提高光線的利用率，可讓與發光二極體晶 片（未繪示）位於線路板50之同一面的防銲罩幕116具有 反光性，或使得防銲罩幕116之表面呈現白色。 圖2A至圖2D繪示圖1A之導電板以半蝕刻方式形成 導電圖案的過程。如圖2A所示，首先提供一完整的導電 板110，其材質可為金屬，例如是銅、I呂或不鏽鋼。接著， 如圖2B所示，將蝕刻罩幕202及蝕刻罩幕2〇4分別形成 在導電板110之兩面，其中蝕刻罩幕202可為一已圖案化 之光阻層或一層抗钱刻油墨圖案。之後，如圖2C所示， 蝕刻上述導電板11〇，因而移除導電板110之未受蝕刻罩 幕202所遮蓋的部分，而留下導電板no之钕刻罩幕202"month reference figure U', in order to protect the exposed surfaces of the joints 11 la, 11 lb, 11 ia, flnb, a plurality of metal fluffs 118 may be covered by these metal mats , llla, and lllb, the exposed surface. In this real scarf, some metal protective layers 118 are formed on these bonding pads ma, ΓΓ layer jizaki®. The butterfly 118 is, for example, nickel. After the road board 50 is completed, the circuit board 50 can be made into a plurality of individual circuit board units 3 according to the requirement i: 11). The step of pre-processing can be cut (eut) or Punch (pug) and so on. The circuit board 50 can be used as a planar grid array (LGA) substrate, a quad flat no-pin (QFN) substrate, a ball grid array (BGA) substrate, or a light-emitting diode wafer carrier. When the circuit board 50 is applied as a light-emitting diode wafer carrier, in order to improve the utilization of light, the solder mask 116 having the same surface as the light-emitting diode wafer (not shown) on the circuit board 50 may be provided. Reflective, or make the surface of the solder mask 116 appear white. 2A to 2D illustrate a process in which the conductive plate of FIG. 1A is formed into a conductive pattern in a half etching manner. As shown in Fig. 2A, a complete conductive plate 110 is first provided, which may be made of a metal such as copper, Ilu or stainless steel. Next, as shown in FIG. 2B, an etching mask 202 and an etching mask 2〇4 are respectively formed on both sides of the conductive plate 110, wherein the etching mask 202 can be a patterned photoresist layer or an ink-resistant ink. pattern. Thereafter, as shown in Fig. 2C, the above-mentioned conductive plate 11 is etched, thereby removing the portion of the conductive plate 110 that is not covered by the etched mask 202, leaving the etch mask 202 of the conductive plate no.
所遮蓋的部分，以形成第一導電圖案110a。最後，如圖2D 所示，移除蝕刻罩幕202及蝕刻罩幕204，而暴露出導電 板110之兩面。 综上所述，本發明之線路板製程除可製作出具有導電^ 核心之線路板之外，還可歷經單一製程週期後製作兩片線 路板，因而降低線路板製作成本。此外，本發明之線路板 可藉由導電板來提高導熱性，故可應用於承載高熱功率之 晶片，例如LED晶片。 ^雖然本發明已以一實施例揭露如上，然其並非用以限 定本發明’任何所屬技術領域中具有通常知識者，在不脫 1303146 21369twf.doc/n 離本發明之精神和範圍内，當可作些許之更動與潤飾，因 此本發明之保護範圍當視後附之申請專利範圍所界定者為 準。 【圖式簡單說明】 圖1A至圖1J繪示本發明之一實施例之一種線路板製 程。 圖2A至圖2D繪示圖1A之導電板以半蝕刻方式形成 導電圖案的過程。 【主要元件符號說明】 50 ··線路板 100 :支撐板 100a :第一面 100b ··第二面 102 :接著層 104 :離形層 106 :第一導電層 108 :第一介電層 109 :複合層 110 :導電板 110a :第一導電圖案 110b :第二導電圖案 110b’ ··次導電圖案 17 1303146 21369twf.doc/n 110b” ：次導電圖案 111a :接合墊 111a’ ：接合墊 111b :接合墊 111b’ ：接合墊 112 :第二介電層 114 :第二導電層The covered portion forms the first conductive pattern 110a. Finally, as shown in Figure 2D, the etch mask 202 and the etch mask 204 are removed to expose both sides of the conductive plate 110. In summary, the circuit board process of the present invention can produce two circuit boards after a single process cycle, in addition to the circuit board having the conductive core, thereby reducing the manufacturing cost of the circuit board. Further, the wiring board of the present invention can be used for carrying a high thermal power wafer such as an LED wafer by a conductive plate for improving thermal conductivity. Although the present invention has been disclosed in an embodiment of the present invention, it is not intended to limit the present invention to any one of ordinary skill in the art, without departing from the spirit and scope of the present invention. A number of changes and modifications may be made, and the scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1J illustrate a circuit board process according to an embodiment of the present invention. 2A to 2D illustrate a process in which the conductive plate of FIG. 1A is formed into a conductive pattern in a half etching manner. [Description of main component symbols] 50··PCB 100: support plate 100a: first surface 100b · second surface 102: adhesive layer 104: release layer 106: first conductive layer 108: first dielectric layer 109: Composite layer 110: conductive plate 110a: first conductive pattern 110b: second conductive pattern 110b'.. secondary conductive pattern 17 1303146 21369twf.doc/n 110b": secondary conductive pattern 111a: bonding pad 111a': bonding pad 111b: bonding Pad 111b': bonding pad 112: second dielectric layer 114: second conductive layer
115 :複合層 115a :開口 116 :防銲罩幕 118 :金屬保護層 120 :導電通孔 120a ··貫孔 120b :導電壁115 : composite layer 115a : opening 116 : solder mask NO 118 : metal protective layer 120 : conductive via 120a · · through hole 120b : conductive wall