TWI581394B - Carrier substrate - Google Patents
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- TWI581394B TWI581394B TW105133845A TW105133845A TWI581394B TW I581394 B TWI581394 B TW I581394B TW 105133845 A TW105133845 A TW 105133845A TW 105133845 A TW105133845 A TW 105133845A TW I581394 B TWI581394 B TW I581394B
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本發明是有關於一種載板，且特別是有關於一種具有具非線性邊緣輪廓（edge profile）的虛擬圖案（dummy pattern）的載板。This invention relates to a carrier board, and more particularly to a carrier board having a dummy pattern having a non-linear edge profile.
近年來，隨著電子技術的快速進展以及高科技電子產業的繁榮發展，更多具有更好功能的使用者友善電子產品出現並且朝向輕、薄、短和小的趨勢演變。所述電子產品通常包括多個半導體封裝結構。一般來說，可藉由將多個晶片堆疊在載板上而形成半導體封裝結構。因此，半導體封裝結構中的載板的開發在增強電子產品的性能方面扮演重要的角色。In recent years, with the rapid advancement of electronic technology and the prosperity of the high-tech electronics industry, more user-friendly electronic products with better functions have emerged and are evolving toward light, thin, short and small trends. The electronic product typically includes a plurality of semiconductor package structures. In general, a semiconductor package structure can be formed by stacking a plurality of wafers on a carrier. Therefore, the development of carrier boards in semiconductor package structures plays an important role in enhancing the performance of electronic products.
本發明提供一種載板，其能夠緩解組裝過程期間所產生的斷裂問題，藉此改善使用所述載板的半導體封裝（semiconductor package）和電子產品的可靠性。The present invention provides a carrier plate that can alleviate the cracking problem generated during the assembly process, thereby improving the reliability of a semiconductor package and an electronic product using the carrier.
本發明提供一種載板，其包括絕緣密封體、多個第一導電圖案、多個第二導電圖案、至少一第一虛擬圖案以及至少一第二虛擬圖案。載板具有第一佈線區以及第二佈線區。第一導電圖案位於第一佈線區中，且第二導電圖案位於第二佈線區中。第一導電圖案以及第二導電圖案嵌入於絕緣密封體中。絕緣密封體暴露出第一導電圖案以及第二導電圖案的頂表面。第一虛擬圖案位於第一佈線區中，且第二虛擬圖案位於第二佈線區中。第一虛擬圖案以及第二虛擬圖案與第一導電圖案以及第二導電圖案絕緣。第一虛擬圖案以及第二虛擬圖案嵌入於絕緣密封體中。絕緣密封體暴露出第一虛擬圖案以及第二虛擬圖案的頂表面。第一虛擬圖案面向第二虛擬圖案的邊緣輪廓包括矩形鋸齒形形狀、V形鋸齒形形狀、半圓形鋸齒形形狀、波浪形狀或其組合。The present invention provides a carrier board including an insulating sealing body, a plurality of first conductive patterns, a plurality of second conductive patterns, at least one first dummy pattern, and at least one second dummy pattern. The carrier board has a first wiring area and a second wiring area. The first conductive pattern is located in the first wiring region, and the second conductive pattern is located in the second wiring region. The first conductive pattern and the second conductive pattern are embedded in the insulating sealing body. The insulating sealing body exposes the first conductive pattern and the top surface of the second conductive pattern. The first dummy pattern is located in the first wiring region, and the second dummy pattern is located in the second wiring region. The first dummy pattern and the second dummy pattern are insulated from the first conductive pattern and the second conductive pattern. The first dummy pattern and the second dummy pattern are embedded in the insulating sealing body. The insulating sealing body exposes the first dummy pattern and the top surface of the second dummy pattern. The edge contour of the first dummy pattern facing the second dummy pattern includes a rectangular zigzag shape, a V-shaped zigzag shape, a semi-circular zigzag shape, a wave shape, or a combination thereof.
基於上述，藉由改變載板中的虛擬圖案的邊緣輪廓，可充分地消除虛擬圖案、導電圖案以及絕緣密封體之間的斷裂，故能夠由此改善使用載板的半導體封裝和電子產品的可靠性。此外，藉由增加虛擬圖案的某些部分的厚度，可以增大虛擬圖案與絕緣密封體之間的接觸面積。因此，可減少發生斷裂的情形，並且可進一步確保半導體封裝和電子產品的可靠性。Based on the above, by changing the edge profile of the dummy pattern in the carrier, the break between the dummy pattern, the conductive pattern, and the insulating sealing body can be sufficiently eliminated, thereby improving the reliability of the semiconductor package and the electronic product using the carrier. Sex. Furthermore, by increasing the thickness of certain portions of the dummy pattern, the contact area between the dummy pattern and the insulating sealing body can be increased. Therefore, the occurrence of breakage can be reduced, and the reliability of the semiconductor package and the electronic product can be further ensured.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the invention will be apparent from the following description.
現將詳細地參考本發明的示範性實施例，示範性實施例的實例說明於附圖中。只要有可能，相同元件符號在圖式和描述中用來表示相同或相似部分。Reference will now be made in detail to the exemplary embodiments embodiments Wherever possible, the same element symbols are used in the drawings and the description
圖1是根據本發明的一些實施例的載板（carrier substrate）10的示意性俯視圖。請參照圖1，載板10包括第一佈線區（layout region）R1以及相鄰於一佈線區R1的第二佈線區R2。第一佈線區R1與第二佈線區R2分別包括核心區CR以及周邊區PR。如圖1所示，在一些實施例中，周邊區PR圍繞核心區CR。第一佈線區R1的核心區CR包括多個第一導電圖案101，且第二佈線區R2的核心區CR包括多個第二導電圖案201。在一些實施例中，第一佈線區R1的周邊區PR包括第一虛擬圖案103，且第二佈線區R2的周邊區PR包括第二虛擬圖案203。在一些實施例中，由於周邊區PR圍繞核心區CR，因此第一虛擬圖案103圍繞第一導電圖案101，且第二虛擬圖案203圍繞第二導電圖案201。1 is a schematic top plan view of a carrier substrate 10 in accordance with some embodiments of the present invention. Referring to FIG. 1, the carrier 10 includes a first layout region R1 and a second routing region R2 adjacent to a routing region R1. The first wiring region R1 and the second wiring region R2 respectively include a core region CR and a peripheral region PR. As shown in FIG. 1, in some embodiments, the perimeter region PR surrounds the core region CR. The core region CR of the first wiring region R1 includes a plurality of first conductive patterns 101, and the core region CR of the second wiring region R2 includes a plurality of second conductive patterns 201. In some embodiments, the peripheral region PR of the first wiring region R1 includes the first dummy pattern 103, and the peripheral region PR of the second wiring region R2 includes the second dummy pattern 203. In some embodiments, since the peripheral region PR surrounds the core region CR, the first dummy pattern 103 surrounds the first conductive pattern 101, and the second dummy pattern 203 surrounds the second conductive pattern 201.
第一導電圖案101以及第二導電圖案201是用於訊號傳輸。舉例來說，第一導電圖案101以及第二導電圖案201可為由銅、鋁、金、銀、鎳、鈀或其組合製成的金屬走線（metallic trace）。部分的第一導電圖案101可彼此互連。類似地，部分的第二導電圖案201可彼此互連。由於位於核心區CR中的第一導電圖案101以及第二導電圖案201是用於訊號傳輸，因此核心區CR可稱為主動區（active region）。The first conductive pattern 101 and the second conductive pattern 201 are for signal transmission. For example, the first conductive pattern 101 and the second conductive pattern 201 may be metal traces made of copper, aluminum, gold, silver, nickel, palladium, or a combination thereof. Portions of the first conductive patterns 101 may be interconnected to each other. Similarly, portions of the second conductive patterns 201 may be interconnected to each other. Since the first conductive pattern 101 and the second conductive pattern 201 located in the core region CR are for signal transmission, the core region CR may be referred to as an active region.
第一虛擬圖案103以及第二虛擬圖案203與第一導電圖案101以及第二導電圖案201電性絕緣。不同於第一導電圖案101以及第二導電圖案201，第一虛擬圖案103以及第二虛擬圖案203不用於訊號傳輸。在一些實施例中，第一虛擬圖案103以及第二虛擬圖案203可連接到接地（ground）或可連接到電源（未繪示）。可施加接地偏壓（ground bias）或電源偏壓（power bias）至第一虛擬圖案103以及第二虛擬圖案203。換言之，恆定電壓（constant voltage）施加至第一虛擬圖案103以及第二虛擬圖案203。然而，本發明不限於此。第一虛擬圖案103以及第二虛擬圖案203還可以基於電路設計而具有其它功能。舉例來說，在一些替代實施例中，第一虛擬圖案103以及第二虛擬圖案203可以為電性浮置。換言之，並無電壓施加至第一虛擬圖案103以及第二虛擬圖案203。在一些實施例中，第一虛擬圖案103以及第二虛擬圖案203為網狀結構（mesh structure），如圖1所繪示。The first dummy pattern 103 and the second dummy pattern 203 are electrically insulated from the first conductive pattern 101 and the second conductive pattern 201. Unlike the first conductive pattern 101 and the second conductive pattern 201, the first dummy pattern 103 and the second dummy pattern 203 are not used for signal transmission. In some embodiments, the first dummy pattern 103 and the second dummy pattern 203 may be connected to a ground or may be connected to a power source (not shown). A ground bias or a power bias may be applied to the first dummy pattern 103 and the second dummy pattern 203. In other words, a constant voltage is applied to the first dummy pattern 103 and the second dummy pattern 203. However, the invention is not limited thereto. The first dummy pattern 103 and the second dummy pattern 203 may also have other functions based on circuit design. For example, in some alternative embodiments, the first dummy pattern 103 and the second dummy pattern 203 may be electrically floating. In other words, no voltage is applied to the first dummy pattern 103 and the second dummy pattern 203. In some embodiments, the first dummy pattern 103 and the second dummy pattern 203 are mesh structures, as illustrated in FIG. 1 .
在一些實施例中，第一導電圖案101、第二導電圖案201、第一虛擬圖案103以及第二虛擬圖案203可藉由相同製程形成。舉例來說，第一導電圖案101、第二導電圖案201、第一虛擬圖案103以及第二虛擬圖案203可藉由電鍍製程形成於不銹鋼板（未繪示）上，但本發明不限於此。其它合適方法可適於形成第一導電圖案101、第二導電圖案201、第一虛擬圖案103以及第二虛擬圖案203。在載板10的形成製程完成之後，可移除不銹鋼板。In some embodiments, the first conductive pattern 101, the second conductive pattern 201, the first dummy pattern 103, and the second dummy pattern 203 may be formed by the same process. For example, the first conductive pattern 101, the second conductive pattern 201, the first dummy pattern 103, and the second dummy pattern 203 may be formed on a stainless steel plate (not shown) by an electroplating process, but the invention is not limited thereto. Other suitable methods may be suitable for forming the first conductive pattern 101, the second conductive pattern 201, the first dummy pattern 103, and the second dummy pattern 203. After the forming process of the carrier 10 is completed, the stainless steel plate can be removed.
圖2A為圖1中的區域100的示意性放大視圖。圖3為根據本發明的一些實施例的沿著圖2A的剖線A-A'截取的示意性剖面圖。請同時參照圖2A以及圖3，載板10包括絕緣密封體102，且第一導電圖案101、第二導電圖案201、第一虛擬圖案103以及第二虛擬圖案203嵌入於絕緣密封體102中。絕緣密封體102暴露出第一導電圖案101、第二導電圖案201、第一虛擬圖案103以及第二虛擬圖案203的頂表面，以使得這些元件可經由其頂表面連接到其它電子元件（electrical component）。儘管圖3中所繪示出的第一導電圖案101、第二導電圖案201、第一虛擬圖案103以及第二虛擬圖案203的頂表面低於絕緣密封體102的頂表面，但本發明不限於此。在一些替代實施例中，第一導電圖案101、第二導電圖案201、第一虛擬圖案103以及第二虛擬圖案203的頂表面可以與絕緣密封體102的頂表面共平面（coplanar）。2A is a schematic enlarged view of the area 100 of FIG. 1. 3 is a schematic cross-sectional view taken along line AA' of FIG. 2A, in accordance with some embodiments of the present invention. Referring to FIG. 2A and FIG. 3 simultaneously, the carrier 10 includes an insulating sealing body 102, and the first conductive pattern 101, the second conductive pattern 201, the first dummy pattern 103, and the second dummy pattern 203 are embedded in the insulating sealing body 102. The insulating sealing body 102 exposes the top surfaces of the first conductive pattern 101, the second conductive pattern 201, the first dummy pattern 103, and the second dummy pattern 203 such that these elements can be connected to other electronic components via their top surfaces (electrical components) ). Although the top surfaces of the first conductive pattern 101, the second conductive pattern 201, the first dummy pattern 103, and the second dummy pattern 203 illustrated in FIG. 3 are lower than the top surface of the insulating sealing body 102, the present invention is not limited thereto. this. In some alternative embodiments, the top surfaces of the first conductive pattern 101, the second conductive pattern 201, the first dummy pattern 103, and the second dummy pattern 203 may be coplanar with the top surface of the insulating sealing body 102.
絕緣密封體102密封第一導電圖案101、第二導電圖案201、第一虛擬圖案103以及第二虛擬圖案203，以使得第一導電圖案101與第一虛擬圖案103電性絕緣並且使得第二導電圖案201與第二虛擬圖案203電性絕緣。絕緣密封體102的材料包括（但不限於）味之素堆積薄膜（Ajinomoto build-up film；ABF）樹脂、聚合材料（polymer material）或環氧樹脂。在一些實施例中，絕緣密封體102可由苯並環丁烯（benzocyclo-butene；BCB）、液晶聚合物（liquid crystal polymer；LCP）、聚醯亞胺（polyimide）、聚苯醚（polyphenylene ether；PPE）、FR4、FR5、芳族聚醯胺（aramide或aramid）、模製化合物（molding compound）、與環氧樹脂混合的玻璃纖維或其組合製成。在一些實施例中，密封材料層（未繪示）可經由例如模製製程（molding process）的技術形成以覆蓋第一導電圖案101、第二導電圖案201、第一虛擬圖案103以及第二虛擬圖案203。隨後，移除密封材料層的一部分以暴露出第一導電圖案101、第二導電圖案201、第一虛擬圖案103以及第二虛擬圖案203的頂表面，以形成絕緣密封體102。密封材料層的一部分可經由蝕刻製程或化學機械研磨（chemical mechanical polishing，CMP）製程移除。The insulating sealing body 102 seals the first conductive pattern 101, the second conductive pattern 201, the first dummy pattern 103, and the second dummy pattern 203 such that the first conductive pattern 101 is electrically insulated from the first dummy pattern 103 and makes the second conductive The pattern 201 is electrically insulated from the second dummy pattern 203. The material of the insulating sealing body 102 includes, but is not limited to, an Ajinomoto build-up film (ABF) resin, a polymer material or an epoxy resin. In some embodiments, the insulating sealing body 102 may be composed of benzocyclo-butene (BCB), liquid crystal polymer (LCP), polyimide, polyphenylene ether (polyphenylene ether); PPE), FR4, FR5, aromatic aramide or aramid, molding compound, glass fiber mixed with epoxy resin or a combination thereof. In some embodiments, a sealing material layer (not shown) may be formed via a technique such as a molding process to cover the first conductive pattern 101, the second conductive pattern 201, the first dummy pattern 103, and the second dummy. Pattern 203. Subsequently, a portion of the sealing material layer is removed to expose the top surfaces of the first conductive pattern 101, the second conductive pattern 201, the first dummy pattern 103, and the second dummy pattern 203 to form the insulating sealing body 102. A portion of the layer of sealing material can be removed via an etching process or a chemical mechanical polishing (CMP) process.
請參照圖2A，第一虛擬圖案103包括第一主體部103a以及朝向第二虛擬圖案203橫向突出的多個第一突起部103b。類似地，第二虛擬圖案203包括第二主體部203a以及朝向第一虛擬圖案103橫向突出的多個第二突起部203b。換言之，第一虛擬圖案103具有位於其邊緣上的多個第一突起部103b，且第二虛擬圖案203具有位於其邊緣上的多個第二突起部203b。因此，如圖2A所繪示的俯視圖所示，第一虛擬圖案103面向第二虛擬圖案203的邊緣輪廓（edge profile）為非線性（non-linear）的。類似地，第二虛擬圖案203面向第一虛擬圖案103的邊緣輪廓也是非線性的。換言之，佈線區具有週期性（規律的）波浪或鋸齒形邊界，且第一虛擬圖案103與第二虛擬圖案203沿著週期性（規律的）波浪或鋸齒形邊界共形（conformal）地配置。邊界的形狀不限於具有均勻形狀的波浪狀。邊界的形狀可根據在半導體封裝製程期間接收較高壓力的區域而加以調整。舉例來說，載板10的特定區域（高壓力區域；未繪示）在後續半導體封裝製程期間可能經受較高壓力。在一些實施例中，第一突起部103b以及第二突起部203b可特定地配置在載板10被施加壓力的區域中。壓力區域通常經受8 MPa到10 MPa的機械壓力（machine pressure）或350 g/cm 2到400 g/cm 2的彎曲壓力（bending pressure）。在一些實施例中，第一虛擬圖案103的邊緣輪廓與第二虛擬圖案203的邊緣輪廓鏡像對稱。然而，本發明不限於此。在一些替代實施例中，第一虛擬圖案103與第二虛擬圖案203的邊緣輪廓可以不對稱。如圖2A所示，第一突起部103b以及第二突起部203b可為矩形柱形狀，因此第一虛擬圖案103以及第二虛擬圖案203的邊緣輪廓呈現矩形鋸齒形形狀。然而，本發明不限於此。如稍後將在圖2B至圖2D的實施例中所描述，第一突起部103b以及第二突起部203b可以具有其他形狀，只要第一虛擬圖案103的邊緣輪廓以及第二突起部203b的邊緣輪廓形成週期性鋸齒形或波浪輪廓即可。在一些實施例中，僅第一虛擬圖案103面向第二虛擬圖案203的邊緣為非線性的。然而，此種配置方式僅為示範性說明，且本發明不限於此。在一些替代實施例中，第一虛擬圖案103的整個邊緣（所有四個側）以及第二虛擬圖案203的整個邊緣為非線性的。 Referring to FIG. 2A, the first dummy pattern 103 includes a first body portion 103a and a plurality of first protrusions 103b that protrude laterally toward the second dummy pattern 203. Similarly, the second dummy pattern 203 includes a second body portion 203a and a plurality of second protrusions 203b that laterally protrude toward the first dummy pattern 103. In other words, the first dummy pattern 103 has a plurality of first protrusions 103b on its edge, and the second dummy pattern 203 has a plurality of second protrusions 203b on its edges. Therefore, as shown in the top view of FIG. 2A, the edge profile of the first dummy pattern 103 facing the second dummy pattern 203 is non-linear. Similarly, the edge contour of the second dummy pattern 203 facing the first dummy pattern 103 is also non-linear. In other words, the wiring region has a periodic (regular) wave or zigzag boundary, and the first dummy pattern 103 and the second dummy pattern 203 are conformally arranged along a periodic (regular) wave or zigzag boundary. The shape of the boundary is not limited to a wave shape having a uniform shape. The shape of the boundary can be adjusted based on the area that receives higher pressure during the semiconductor packaging process. For example, certain regions of the carrier 10 (high pressure regions; not shown) may experience higher pressures during subsequent semiconductor packaging processes. In some embodiments, the first protrusion 103b and the second protrusion 203b may be specifically disposed in a region where the carrier 10 is pressurized. The pressure zone is typically subjected to a machine pressure of 8 MPa to 10 MPa or a bending pressure of 350 g/cm 2 to 400 g/cm 2 . In some embodiments, the edge contour of the first dummy pattern 103 is mirror-symmetrical to the edge contour of the second dummy pattern 203. However, the invention is not limited thereto. In some alternative embodiments, the edge contours of the first dummy pattern 103 and the second dummy pattern 203 may be asymmetric. As shown in FIG. 2A, the first protrusion portion 103b and the second protrusion portion 203b may have a rectangular column shape, and thus the edge contours of the first dummy pattern 103 and the second dummy pattern 203 assume a rectangular zigzag shape. However, the invention is not limited thereto. As will be described later in the embodiment of FIGS. 2B to 2D, the first protrusion 103b and the second protrusion 203b may have other shapes as long as the edge contour of the first dummy pattern 103 and the edge of the second protrusion 203b The contour forms a periodic zigzag or wavy profile. In some embodiments, only the edge of the first dummy pattern 103 facing the second dummy pattern 203 is non-linear. However, such an arrangement is merely an exemplary illustration, and the invention is not limited thereto. In some alternative embodiments, the entire edge (all four sides) of the first dummy pattern 103 and the entire edge of the second dummy pattern 203 are non-linear.
由於第一虛擬圖案103以及第二虛擬圖案203的邊緣輪廓為非線性的，因此第一虛擬圖案103、第二虛擬圖案203以及絕緣密封體102之間的接觸面積可以增大。因此，這些元件之間的附著力（adhesion）得以被恰當地增強。據此，可充分地消除導電圖案（例如，第一導電圖案101、第二導電圖案201、第一虛擬圖案103以及第二虛擬圖案203）與絕緣密封體102之間的斷裂，藉此改善使用載板10的半導體封裝以及電子產品的可靠性。Since the edge contours of the first dummy pattern 103 and the second dummy pattern 203 are non-linear, the contact area between the first dummy pattern 103, the second dummy pattern 203, and the insulating sealing body 102 can be increased. Therefore, the adhesion between these elements is appropriately enhanced. According to this, the breakage between the conductive pattern (for example, the first conductive pattern 101, the second conductive pattern 201, the first dummy pattern 103, and the second dummy pattern 203) and the insulating sealing body 102 can be sufficiently eliminated, thereby improving the use. The semiconductor package of the carrier 10 and the reliability of the electronic product.
圖2B為圖1中的區域100a的示意性放大視圖。請參照圖2B，圖2B的實施例類似於圖2A的實施例，因此類似元件由相同的標號表示，且本文中不重複對這些類似元件描述。圖2B的實施例與圖2A的實施例之間的差異在於，在圖2B中，第一突起部103b以及第二突起部203b為梯形柱形狀以形成V形鋸齒形邊緣輪廓。類似於圖2A的實施例，圖2B的非線性邊緣輪廓可增大第一虛擬圖案103、第二虛擬圖案203以及絕緣密封體102之間的接觸面積。因此，可充分地消除導電圖案（例如，第一導電圖案101、第二導電圖案201、第一虛擬圖案103以及第二虛擬圖案203）與絕緣密封體102之間的斷裂，藉此改善使用載板10的半導體封裝以及電子產品的可靠性。FIG. 2B is a schematic enlarged view of the area 100a of FIG. 1. Referring to FIG. 2B, the embodiment of FIG. 2B is similar to the embodiment of FIG. 2A, and thus similar elements are denoted by the same reference numerals, and the description of these similar elements is not repeated herein. The difference between the embodiment of FIG. 2B and the embodiment of FIG. 2A is that in FIG. 2B, the first protrusion 103b and the second protrusion 203b are trapezoidal column shapes to form a V-shaped zigzag edge profile. Similar to the embodiment of FIG. 2A, the non-linear edge profile of FIG. 2B can increase the contact area between the first dummy pattern 103, the second dummy pattern 203, and the insulating sealing body 102. Therefore, the breakage between the conductive patterns (for example, the first conductive pattern 101, the second conductive pattern 201, the first dummy pattern 103, and the second dummy pattern 203) and the insulating sealing body 102 can be sufficiently eliminated, thereby improving the use load. The semiconductor package of the board 10 and the reliability of the electronic product.
圖2C為圖1中的區域100b的示意性放大視圖。請參照圖2C，圖2C的實施例類似於圖2A的實施例，因此類似元件由相同的標號表示，且本文中不重複對這些類似元件描述。圖2C的實施例與圖2A的實施例之間的差異在於，在圖2C中，第一突起部103b以及第二突起部203b為具有彎曲支腿（leg）的梯形柱形狀以形成半圓形鋸齒形邊緣輪廓。類似於圖2A的實施例，圖2C的非線性邊緣輪廓可增大第一虛擬圖案103、第二虛擬圖案203以及絕緣密封體102之間的接觸面積。因此，可充分地消除導電圖案（例如，第一導電圖案101、第二導電圖案201、第一虛擬圖案103以及第二虛擬圖案203）與絕緣密封體102之間的斷裂，藉此改善使用載板10的半導體封裝以及電子產品的可靠性。2C is a schematic enlarged view of the region 100b of FIG. 1. Referring to FIG. 2C, the embodiment of FIG. 2C is similar to the embodiment of FIG. 2A, and thus similar elements are denoted by the same reference numerals, and the description of these similar elements is not repeated herein. The difference between the embodiment of Fig. 2C and the embodiment of Fig. 2A is that, in Fig. 2C, the first protrusion 103b and the second protrusion 203b are trapezoidal column shapes having curved legs to form a semicircle Zigzag edge contour. Similar to the embodiment of FIG. 2A, the non-linear edge profile of FIG. 2C can increase the contact area between the first dummy pattern 103, the second dummy pattern 203, and the insulating sealing body 102. Therefore, the breakage between the conductive patterns (for example, the first conductive pattern 101, the second conductive pattern 201, the first dummy pattern 103, and the second dummy pattern 203) and the insulating sealing body 102 can be sufficiently eliminated, thereby improving the use load. The semiconductor package of the board 10 and the reliability of the electronic product.
圖2D為圖1中的區域100c的示意性放大視圖。請參照圖2D，圖2D的實施例類似於圖2A的實施例，因此類似元件由相同的標號表示，且本文中不重複對這些類似元件描述。圖2D的實施例與圖2A的實施例之間的差異在於，在圖2D中，第一突起部103b以及第二突起部203b為半圓形柱形狀以形成波浪形邊緣輪廓。類似於圖2A的實施例，圖2D的非線性邊緣輪廓可增大第一虛擬圖案103、第二虛擬圖案203以及絕緣密封體102之間的接觸面積。因此，可充分地消除導電圖案（例如，第一導電圖案101、第二導電圖案201、第一虛擬圖案103以及第二虛擬圖案203）與絕緣密封體102之間的斷裂，藉此改善使用載板10的半導體封裝以及電子產品的可靠性。FIG. 2D is a schematic enlarged view of the area 100c of FIG. 1. Referring to FIG. 2D, the embodiment of FIG. 2D is similar to the embodiment of FIG. 2A, and thus similar elements are denoted by the same reference numerals, and the description of these similar elements is not repeated herein. The difference between the embodiment of Fig. 2D and the embodiment of Fig. 2A is that in Fig. 2D, the first protrusion 103b and the second protrusion 203b are semicircular column shapes to form a wavy edge profile. Similar to the embodiment of FIG. 2A, the non-linear edge profile of FIG. 2D can increase the contact area between the first dummy pattern 103, the second dummy pattern 203, and the insulating sealing body 102. Therefore, the breakage between the conductive patterns (for example, the first conductive pattern 101, the second conductive pattern 201, the first dummy pattern 103, and the second dummy pattern 203) and the insulating sealing body 102 can be sufficiently eliminated, thereby improving the use load. The semiconductor package of the board 10 and the reliability of the electronic product.
圖4為根據本發明的一些替代實施例的沿著圖2A的剖線A-A'截取的示意性剖面圖。請參照圖4，圖4的實施例類似於圖3的實施例，因此類似元件由相同的標號表示，且本文中不重複對這些類似元件描述。圖4的實施例與圖3的實施例之間的差異在於，在圖4中，第一突起部103b以及第二突起部203b的厚度w1大於第一主體部103a以及第二主體部203a的厚度w2。換言之，第一突起部103b不僅橫向突出，而且縱向突出。舉例來說，第一主體部103a以及第二主體部203a可為導電線層（conductive line layer）。另一方面，除了導電線層以外，第一突起部103b以及第二突起部203b可進一步包括位於導電線層下方的導電柱（conductive post）。據此，第一虛擬圖案103以及第二虛擬圖案203在其邊緣處的厚度能被增大。由於第一突起部103b以及第二突起部203b的厚度w1大於第一主體部103a以及第二主體部203a的厚度w2，因此可增大第一虛擬圖案103、第二虛擬圖案203以及絕緣密封體102之間的接觸面積。因此，這些元件之間的附著力得以被恰當地增強。據此，可充分地消除導電圖案（例如，第一導電圖案101、第二導電圖案201、第一虛擬圖案103以及第二虛擬圖案203）與絕緣密封體102之間的斷裂，藉此改善使用載板10的半導體封裝以及電子產品的可靠性。4 is a schematic cross-sectional view taken along line AA' of FIG. 2A, in accordance with some alternative embodiments of the present invention. Referring to FIG. 4, the embodiment of FIG. 4 is similar to the embodiment of FIG. 3, and thus similar elements are denoted by the same reference numerals, and the description of these similar elements is not repeated herein. The difference between the embodiment of FIG. 4 and the embodiment of FIG. 3 is that, in FIG. 4, the thickness w1 of the first protrusion portion 103b and the second protrusion portion 203b is greater than the thickness of the first body portion 103a and the second body portion 203a. W2. In other words, the first protrusions 103b not only protrude laterally but also protrude longitudinally. For example, the first body portion 103a and the second body portion 203a may be a conductive line layer. On the other hand, in addition to the conductive layer, the first protrusion 103b and the second protrusion 203b may further include a conductive post under the conductive layer. According to this, the thickness of the first dummy pattern 103 and the second dummy pattern 203 at the edges thereof can be increased. Since the thickness w1 of the first protrusion portion 103b and the second protrusion portion 203b is larger than the thickness w2 of the first body portion 103a and the second body portion 203a, the first dummy pattern 103, the second dummy pattern 203, and the insulating sealing body can be enlarged. Contact area between 102. Therefore, the adhesion between these elements is appropriately enhanced. According to this, the breakage between the conductive pattern (for example, the first conductive pattern 101, the second conductive pattern 201, the first dummy pattern 103, and the second dummy pattern 203) and the insulating sealing body 102 can be sufficiently eliminated, thereby improving the use. The semiconductor package of the carrier 10 and the reliability of the electronic product.
圖5為根據本發明的一些替代實施例的載板10a的示意性俯視圖。請參照圖5，圖5的實施例類似於圖1的實施例，因此類似元件由相同的標號表示，且本文中不重複對這些類似元件描述。圖5的實施例與圖1的實施例之間的差異在於，在圖5中，第一虛擬圖案103的至少一部分位於兩相鄰的第一導電圖案101之間，且第二虛擬圖案203的至少一部分位於兩相鄰的第二導電圖案201之間。換言之，在圖5的實施例中不存在周邊區，且第一虛擬圖案103以及第二虛擬圖案203配置在核心區CR中。類似於圖1的實施例，第一虛擬圖案103面向第二虛擬圖案203的邊緣輪廓以及第二虛擬圖案203面向第一虛擬圖案103的邊緣輪廓為非線性的。因此，可增大第一虛擬圖案103、第二虛擬圖案203以及絕緣密封體102之間的接觸面積。據此，可充分地消除導電圖案（例如，第一導電圖案101、第二導電圖案201、第一虛擬圖案103以及第二虛擬圖案203）與絕緣密封體102之間的斷裂，藉此改善使用載板10的半導體封裝和電子產品的可靠性。Figure 5 is a schematic top plan view of a carrier 10a in accordance with some alternative embodiments of the present invention. Referring to FIG. 5, the embodiment of FIG. 5 is similar to the embodiment of FIG. 1, and thus like elements are denoted by the same reference numerals, and the description of the similar elements is not repeated herein. The difference between the embodiment of FIG. 5 and the embodiment of FIG. 1 is that, in FIG. 5, at least a portion of the first dummy pattern 103 is located between two adjacent first conductive patterns 101, and the second dummy pattern 203 is At least a portion is located between two adjacent second conductive patterns 201. In other words, there is no peripheral area in the embodiment of FIG. 5, and the first dummy pattern 103 and the second dummy pattern 203 are disposed in the core area CR. Similar to the embodiment of FIG. 1, the edge contour of the first dummy pattern 103 facing the second dummy pattern 203 and the edge contour of the second dummy pattern 203 facing the first dummy pattern 103 are non-linear. Therefore, the contact area between the first dummy pattern 103, the second dummy pattern 203, and the insulating sealing body 102 can be increased. According to this, the breakage between the conductive pattern (for example, the first conductive pattern 101, the second conductive pattern 201, the first dummy pattern 103, and the second dummy pattern 203) and the insulating sealing body 102 can be sufficiently eliminated, thereby improving the use. The reliability of the semiconductor package and electronic product of the carrier 10.
綜上所述，藉由改變載板中的虛擬圖案的邊緣輪廓，可充分地消除虛擬圖案、導電圖案以及絕緣密封體之間的斷裂，故能夠改善使用載板的半導體封裝和電子產品的可靠性。此外，藉由增加虛擬圖案的某些部分的厚度，可以增大虛擬圖案與絕緣密封體之間的接觸面積。虛擬圖案的厚度增加的部分還可以戰略性地放置於半導體封裝的製造過程期間與其它區域相比被施加增大壓力的區域中。因此，可減少發生斷裂的情形，並且可進一步確保半導體封裝和電子產品的可靠性。In summary, by changing the edge contour of the dummy pattern in the carrier, the break between the dummy pattern, the conductive pattern, and the insulating sealing body can be sufficiently eliminated, thereby improving the reliability of the semiconductor package and the electronic product using the carrier. Sex. Furthermore, by increasing the thickness of certain portions of the dummy pattern, the contact area between the dummy pattern and the insulating sealing body can be increased. The increased thickness portion of the dummy pattern can also be strategically placed in the region where the increased pressure is applied during the manufacturing process of the semiconductor package compared to other regions. Therefore, the occurrence of breakage can be reduced, and the reliability of the semiconductor package and the electronic product can be further ensured.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
10、10a：載板 100、100a、100b、100c：區域 101：第一導電圖案 102：絕緣密封體 103：第一虛擬圖案 103a：第一主體部 103b：第一突起部 201：第二導電圖案 203：第二虛擬圖案 203a：第二主體部 203b：第二突起部 CR：核心區 PR：周邊區 R1：第一佈線區 R2：第二佈線區 w1、w2：厚度10, 10a: carrier board 100, 100a, 100b, 100c: region 101: first conductive pattern 102: insulating sealing body 103: first dummy pattern 103a: first body portion 103b: first protrusion portion 201: second conductive pattern 203: second dummy pattern 203a: second body portion 203b: second protrusion portion CR: core region PR: peripheral region R1: first wiring region R2: second wiring region w1, w2: thickness
圖1為根據本發明的一些實施例的載板的示意性俯視圖。 圖2A到圖2D分別為圖1中的區域的示意性放大視圖。 圖3為根據本發明的一些實施例的沿著圖2A的剖線A-A'截取的示意性剖面圖。 圖4為根據本發明的一些替代實施例的沿著圖2A的剖線A-A'截取的示意性剖面圖。 圖5為根據本發明的一些替代實施例的載板的示意性俯視圖。1 is a schematic top plan view of a carrier plate in accordance with some embodiments of the present invention. 2A to 2D are schematic enlarged views of the area in Fig. 1, respectively. 3 is a schematic cross-sectional view taken along line AA' of FIG. 2A, in accordance with some embodiments of the present invention. 4 is a schematic cross-sectional view taken along line AA' of FIG. 2A, in accordance with some alternative embodiments of the present invention. Figure 5 is a schematic top plan view of a carrier plate in accordance with some alternative embodiments of the present invention.
10：載板 100：區域 101：第一導電圖案 201：第二導電圖案 103：第一虛擬圖案 203：第二虛擬圖案 R1：第一佈線區 R2：第二佈線區 CR：核心區 PR：周邊區10: carrier 100: region 101: first conductive pattern 201: second conductive pattern 103: first dummy pattern 203: second dummy pattern R1: first wiring region R2: second wiring region CR: core region PR: periphery Area
Claims (10)
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510683085 | 2015-10-20 |
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| TWI581394B true TWI581394B (en) | 2017-05-01 |
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| TW (1) | TWI581394B (en) |
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| CN114582832A (en) * | 2022-03-04 | 2022-06-03 | 东芯半导体股份有限公司 | Semiconductor device with a plurality of transistors |
| CN114864640A (en) * | 2022-04-20 | 2022-08-05 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
Citations (6)
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|---|---|---|---|---|
| TW200527592A (en) * | 2004-02-13 | 2005-08-16 | Via Tech Inc | Circuit carrier process |
| TW200824519A (en) * | 2006-11-23 | 2008-06-01 | Subtron Technology Co Ltd | Wiring board with high thermal conductivity and process thereof |
| TW201143015A (en) * | 2010-05-20 | 2011-12-01 | Advanced Semiconductor Eng | Semiconductor package structure |
| TW201230260A (en) * | 2011-01-14 | 2012-07-16 | Subtron Technology Co Ltd | Package carrier and manufacturing method thereof |
| TW201426958A (en) * | 2012-12-19 | 2014-07-01 | Advanced Semiconductor Eng | Stacked package device and manufacturing method thereof |
| TW201613435A (en) * | 2014-09-30 | 2016-04-01 | Au Optronics Corp | Display device and fabricating method thereof |
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| JP5893287B2 (en) * | 2011-08-10 | 2016-03-23 | ルネサスエレクトロニクス株式会社 | Semiconductor device and substrate |
| CN203895433U (en) * | 2014-06-19 | 2014-10-22 | 中芯国际集成电路制造(北京)有限公司 | Sealing ring structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200527592A (en) * | 2004-02-13 | 2005-08-16 | Via Tech Inc | Circuit carrier process |
| TW200824519A (en) * | 2006-11-23 | 2008-06-01 | Subtron Technology Co Ltd | Wiring board with high thermal conductivity and process thereof |
| TW201143015A (en) * | 2010-05-20 | 2011-12-01 | Advanced Semiconductor Eng | Semiconductor package structure |
| TW201230260A (en) * | 2011-01-14 | 2012-07-16 | Subtron Technology Co Ltd | Package carrier and manufacturing method thereof |
| TW201426958A (en) * | 2012-12-19 | 2014-07-01 | Advanced Semiconductor Eng | Stacked package device and manufacturing method thereof |
| TW201613435A (en) * | 2014-09-30 | 2016-04-01 | Au Optronics Corp | Display device and fabricating method thereof |
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| CN106601712B (en) | 2019-03-05 |
| CN106601712A (en) | 2017-04-26 |
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