TW201715680A - Carrier substrate - Google Patents

Abstract

A carrier substrate includes an insulation encapsulation, first conductive patterns, second conductive patterns, at least one first dummy pattern, and at least one second dummy pattern. The carrier substrate has a first layout region and a second layout region. The first conductive patterns and the first dummy pattern are located in the first layout region. The second conductive patterns and the second dummy pattern are located in the second layout region. The first and second conductive patterns and the first and second dummy patterns are embedded in the insulation encapsulation. The insulation encapsulation exposes top surfaces of the first and second conductive patterns and the first and second dummy patterns. The first dummy pattern and the second dummy pattern are insulated from the first conductive patterns and the second conductive patterns. An edge profile of the first dummy pattern facing the second dummy pattern is non-linear.

Description

Carrier board

This invention relates to a carrier board, and more particularly to a carrier board having a dummy pattern having a non-linear edge profile.

In recent years, with the rapid advancement of electronic technology and the prosperity of the high-tech electronics industry, more user-friendly electronic products with better functions have emerged and are evolving toward light, thin, short and small trends. The electronic product typically includes a plurality of semiconductor package structures. In general, a semiconductor package structure can be formed by stacking a plurality of wafers on a carrier. Therefore, the development of carrier boards in semiconductor package structures plays an important role in enhancing the performance of electronic products.

The present invention provides a carrier plate that can alleviate the cracking problem generated during the assembly process, thereby improving the reliability of a semiconductor package and an electronic product using the carrier.

The present invention provides a carrier board including an insulating sealing body, a plurality of first conductive patterns, a plurality of second conductive patterns, at least one first dummy pattern, and at least one second dummy pattern. The carrier board has a first wiring area and a second wiring area. The first conductive pattern is located in the first wiring region, and the second conductive pattern is located in the second wiring region. The first conductive pattern and the second conductive pattern are embedded in the insulating sealing body. The insulating sealing body exposes the first conductive pattern and the top surface of the second conductive pattern. The first dummy pattern is located in the first wiring region, and the second dummy pattern is located in the second wiring region. The first dummy pattern and the second dummy pattern are insulated from the first conductive pattern and the second conductive pattern. The first dummy pattern and the second dummy pattern are embedded in the insulating sealing body. The insulating sealing body exposes the first dummy pattern and the top surface of the second dummy pattern. The edge contour of the first dummy pattern facing the second dummy pattern includes a rectangular zigzag shape, a V-shaped zigzag shape, a semi-circular zigzag shape, a wave shape, or a combination thereof.

Based on the above, by changing the edge profile of the dummy pattern in the carrier, the break between the dummy pattern, the conductive pattern, and the insulating sealing body can be sufficiently eliminated, thereby improving the reliability of the semiconductor package and the electronic product using the carrier. Sex. Furthermore, by increasing the thickness of certain portions of the dummy pattern, the contact area between the dummy pattern and the insulating sealing body can be increased. Therefore, the occurrence of breakage can be reduced, and the reliability of the semiconductor package and the electronic product can be further ensured.

The above described features and advantages of the invention will be apparent from the following description.

Reference will now be made in detail to the exemplary embodiments embodiments Wherever possible, the same element symbols are used in the drawings and the description

1 is a schematic top plan view of a carrier substrate 10 in accordance with some embodiments of the present invention. Referring to FIG. 1, the carrier 10 includes a first layout region R1 and a second routing region R2 adjacent to a routing region R1. The first wiring region R1 and the second wiring region R2 respectively include a core region CR and a peripheral region PR. As shown in FIG. 1, in some embodiments, the perimeter region PR surrounds the core region CR. The core region CR of the first wiring region R1 includes a plurality of first conductive patterns 101, and the core region CR of the second wiring region R2 includes a plurality of second conductive patterns 201. In some embodiments, the peripheral region PR of the first wiring region R1 includes the first dummy pattern 103, and the peripheral region PR of the second wiring region R2 includes the second dummy pattern 203. In some embodiments, since the peripheral region PR surrounds the core region CR, the first dummy pattern 103 surrounds the first conductive pattern 101, and the second dummy pattern 203 surrounds the second conductive pattern 201.

The first conductive pattern 101 and the second conductive pattern 201 are for signal transmission. For example, the first conductive pattern 101 and the second conductive pattern 201 may be metal traces made of copper, aluminum, gold, silver, nickel, palladium, or a combination thereof. Portions of the first conductive patterns 101 may be interconnected to each other. Similarly, portions of the second conductive patterns 201 may be interconnected to each other. Since the first conductive pattern 101 and the second conductive pattern 201 located in the core region CR are for signal transmission, the core region CR may be referred to as an active region.

The first dummy pattern 103 and the second dummy pattern 203 are electrically insulated from the first conductive pattern 101 and the second conductive pattern 201. Unlike the first conductive pattern 101 and the second conductive pattern 201, the first dummy pattern 103 and the second dummy pattern 203 are not used for signal transmission. In some embodiments, the first dummy pattern 103 and the second dummy pattern 203 may be connected to a ground or may be connected to a power source (not shown). A ground bias or a power bias may be applied to the first dummy pattern 103 and the second dummy pattern 203. In other words, a constant voltage is applied to the first dummy pattern 103 and the second dummy pattern 203. However, the invention is not limited thereto. The first dummy pattern 103 and the second dummy pattern 203 may also have other functions based on circuit design. For example, in some alternative embodiments, the first dummy pattern 103 and the second dummy pattern 203 may be electrically floating. In other words, no voltage is applied to the first dummy pattern 103 and the second dummy pattern 203. In some embodiments, the first dummy pattern 103 and the second dummy pattern 203 are mesh structures, as illustrated in FIG. 1 .

In some embodiments, the first conductive pattern 101, the second conductive pattern 201, the first dummy pattern 103, and the second dummy pattern 203 may be formed by the same process. For example, the first conductive pattern 101, the second conductive pattern 201, the first dummy pattern 103, and the second dummy pattern 203 may be formed on a stainless steel plate (not shown) by an electroplating process, but the invention is not limited thereto. Other suitable methods may be suitable for forming the first conductive pattern 101, the second conductive pattern 201, the first dummy pattern 103, and the second dummy pattern 203. After the forming process of the carrier 10 is completed, the stainless steel plate can be removed.

2A is a schematic enlarged view of the area 100 of FIG. 1. 3 is a schematic cross-sectional view taken along line AA' of FIG. 2A, in accordance with some embodiments of the present invention. Referring to FIG. 2A and FIG. 3 simultaneously, the carrier 10 includes an insulating sealing body 102, and the first conductive pattern 101, the second conductive pattern 201, the first dummy pattern 103, and the second dummy pattern 203 are embedded in the insulating sealing body 102. The insulating sealing body 102 exposes the top surfaces of the first conductive pattern 101, the second conductive pattern 201, the first dummy pattern 103, and the second dummy pattern 203 such that these elements can be connected to other electronic components via their top surfaces (electrical components) ). Although the top surfaces of the first conductive pattern 101, the second conductive pattern 201, the first dummy pattern 103, and the second dummy pattern 203 illustrated in FIG. 3 are lower than the top surface of the insulating sealing body 102, the present invention is not limited thereto. this. In some alternative embodiments, the top surfaces of the first conductive pattern 101, the second conductive pattern 201, the first dummy pattern 103, and the second dummy pattern 203 may be coplanar with the top surface of the insulating sealing body 102.

The insulating sealing body 102 seals the first conductive pattern 101, the second conductive pattern 201, the first dummy pattern 103, and the second dummy pattern 203 such that the first conductive pattern 101 is electrically insulated from the first dummy pattern 103 and makes the second conductive The pattern 201 is electrically insulated from the second dummy pattern 203. The material of the insulating sealing body 102 includes, but is not limited to, an Ajinomoto build-up film (ABF) resin, a polymer material or an epoxy resin. In some embodiments, the insulating sealing body 102 may be composed of benzocyclo-butene (BCB), liquid crystal polymer (LCP), polyimide, polyphenylene ether (polyphenylene ether); PPE), FR4, FR5, aromatic aramide or aramid, molding compound, glass fiber mixed with epoxy resin or a combination thereof. In some embodiments, a sealing material layer (not shown) may be formed via a technique such as a molding process to cover the first conductive pattern 101, the second conductive pattern 201, the first dummy pattern 103, and the second dummy. Pattern 203. Subsequently, a portion of the sealing material layer is removed to expose the top surfaces of the first conductive pattern 101, the second conductive pattern 201, the first dummy pattern 103, and the second dummy pattern 203 to form the insulating sealing body 102. A portion of the layer of sealing material can be removed via an etching process or a chemical mechanical polishing (CMP) process.

Referring to FIG. 2A, the first dummy pattern 103 includes a first body portion 103a and a plurality of first protrusions 103b that protrude laterally toward the second dummy pattern 203. Similarly, the second dummy pattern 203 includes a second body portion 203a and a plurality of second protrusions 203b that laterally protrude toward the first dummy pattern 103. In other words, the first dummy pattern 103 has a plurality of first protrusions 103b on its edge, and the second dummy pattern 203 has a plurality of second protrusions 203b on its edges. Therefore, as shown in the top view of FIG. 2A, the edge profile of the first dummy pattern 103 facing the second dummy pattern 203 is non-linear. Similarly, the edge contour of the second dummy pattern 203 facing the first dummy pattern 103 is also non-linear. In other words, the wiring region has a periodic (regular) wave or zigzag boundary, and the first dummy pattern 103 and the second dummy pattern 203 are conformally arranged along a periodic (regular) wave or zigzag boundary. The shape of the boundary is not limited to a wave shape having a uniform shape. The shape of the boundary can be adjusted based on the area that receives higher pressure during the semiconductor packaging process. For example, certain regions of the carrier 10 (high pressure regions; not shown) may experience higher pressures during subsequent semiconductor packaging processes. In some embodiments, the first protrusion 103b and the second protrusion 203b may be specifically disposed in a region where the carrier 10 is pressurized. The pressure zone is typically subjected to a machine pressure of 8 MPa to 10 MPa or a bending pressure of 350 g/cm ² to 400 g/cm ² . In some embodiments, the edge contour of the first dummy pattern 103 is mirror-symmetrical to the edge contour of the second dummy pattern 203. However, the invention is not limited thereto. In some alternative embodiments, the edge contours of the first dummy pattern 103 and the second dummy pattern 203 may be asymmetric. As shown in FIG. 2A, the first protrusion portion 103b and the second protrusion portion 203b may have a rectangular column shape, and thus the edge contours of the first dummy pattern 103 and the second dummy pattern 203 assume a rectangular zigzag shape. However, the invention is not limited thereto. As will be described later in the embodiment of FIGS. 2B to 2D, the first protrusion 103b and the second protrusion 203b may have other shapes as long as the edge contour of the first dummy pattern 103 and the edge of the second protrusion 203b The contour forms a periodic zigzag or wavy profile. In some embodiments, only the edge of the first dummy pattern 103 facing the second dummy pattern 203 is non-linear. However, such an arrangement is merely an exemplary illustration, and the invention is not limited thereto. In some alternative embodiments, the entire edge (all four sides) of the first dummy pattern 103 and the entire edge of the second dummy pattern 203 are non-linear.

Since the edge contours of the first dummy pattern 103 and the second dummy pattern 203 are non-linear, the contact area between the first dummy pattern 103, the second dummy pattern 203, and the insulating sealing body 102 can be increased. Therefore, the adhesion between these elements is appropriately enhanced. According to this, the breakage between the conductive pattern (for example, the first conductive pattern 101, the second conductive pattern 201, the first dummy pattern 103, and the second dummy pattern 203) and the insulating sealing body 102 can be sufficiently eliminated, thereby improving the use. The semiconductor package of the carrier 10 and the reliability of the electronic product.

FIG. 2B is a schematic enlarged view of the area 100a of FIG. 1. Referring to FIG. 2B, the embodiment of FIG. 2B is similar to the embodiment of FIG. 2A, and thus similar elements are denoted by the same reference numerals, and the description of these similar elements is not repeated herein. The difference between the embodiment of FIG. 2B and the embodiment of FIG. 2A is that in FIG. 2B, the first protrusion 103b and the second protrusion 203b are trapezoidal column shapes to form a V-shaped zigzag edge profile. Similar to the embodiment of FIG. 2A, the non-linear edge profile of FIG. 2B can increase the contact area between the first dummy pattern 103, the second dummy pattern 203, and the insulating sealing body 102. Therefore, the breakage between the conductive patterns (for example, the first conductive pattern 101, the second conductive pattern 201, the first dummy pattern 103, and the second dummy pattern 203) and the insulating sealing body 102 can be sufficiently eliminated, thereby improving the use load. The semiconductor package of the board 10 and the reliability of the electronic product.

2C is a schematic enlarged view of the region 100b of FIG. 1. Referring to FIG. 2C, the embodiment of FIG. 2C is similar to the embodiment of FIG. 2A, and thus similar elements are denoted by the same reference numerals, and the description of these similar elements is not repeated herein. The difference between the embodiment of Fig. 2C and the embodiment of Fig. 2A is that, in Fig. 2C, the first protrusion 103b and the second protrusion 203b are trapezoidal column shapes having curved legs to form a semicircle Zigzag edge contour. Similar to the embodiment of FIG. 2A, the non-linear edge profile of FIG. 2C can increase the contact area between the first dummy pattern 103, the second dummy pattern 203, and the insulating sealing body 102. Therefore, the breakage between the conductive patterns (for example, the first conductive pattern 101, the second conductive pattern 201, the first dummy pattern 103, and the second dummy pattern 203) and the insulating sealing body 102 can be sufficiently eliminated, thereby improving the use load. The semiconductor package of the board 10 and the reliability of the electronic product.

FIG. 2D is a schematic enlarged view of the area 100c of FIG. 1. Referring to FIG. 2D, the embodiment of FIG. 2D is similar to the embodiment of FIG. 2A, and thus similar elements are denoted by the same reference numerals, and the description of these similar elements is not repeated herein. The difference between the embodiment of Fig. 2D and the embodiment of Fig. 2A is that in Fig. 2D, the first protrusion 103b and the second protrusion 203b are semicircular column shapes to form a wavy edge profile. Similar to the embodiment of FIG. 2A, the non-linear edge profile of FIG. 2D can increase the contact area between the first dummy pattern 103, the second dummy pattern 203, and the insulating sealing body 102. Therefore, the breakage between the conductive patterns (for example, the first conductive pattern 101, the second conductive pattern 201, the first dummy pattern 103, and the second dummy pattern 203) and the insulating sealing body 102 can be sufficiently eliminated, thereby improving the use load. The semiconductor package of the board 10 and the reliability of the electronic product.

4 is a schematic cross-sectional view taken along line AA' of FIG. 2A, in accordance with some alternative embodiments of the present invention. Referring to FIG. 4, the embodiment of FIG. 4 is similar to the embodiment of FIG. 3, and thus similar elements are denoted by the same reference numerals, and the description of these similar elements is not repeated herein. The difference between the embodiment of FIG. 4 and the embodiment of FIG. 3 is that, in FIG. 4, the thickness w1 of the first protrusion portion 103b and the second protrusion portion 203b is greater than the thickness of the first body portion 103a and the second body portion 203a. W2. In other words, the first protrusions 103b not only protrude laterally but also protrude longitudinally. For example, the first body portion 103a and the second body portion 203a may be a conductive line layer. On the other hand, in addition to the conductive layer, the first protrusion 103b and the second protrusion 203b may further include a conductive post under the conductive layer. According to this, the thickness of the first dummy pattern 103 and the second dummy pattern 203 at the edges thereof can be increased. Since the thickness w1 of the first protrusion portion 103b and the second protrusion portion 203b is larger than the thickness w2 of the first body portion 103a and the second body portion 203a, the first dummy pattern 103, the second dummy pattern 203, and the insulating sealing body can be enlarged. Contact area between 102. Therefore, the adhesion between these elements is appropriately enhanced. According to this, the breakage between the conductive pattern (for example, the first conductive pattern 101, the second conductive pattern 201, the first dummy pattern 103, and the second dummy pattern 203) and the insulating sealing body 102 can be sufficiently eliminated, thereby improving the use. The semiconductor package of the carrier 10 and the reliability of the electronic product.

Figure 5 is a schematic top plan view of a carrier 10a in accordance with some alternative embodiments of the present invention. Referring to FIG. 5, the embodiment of FIG. 5 is similar to the embodiment of FIG. 1, and thus like elements are denoted by the same reference numerals, and the description of the similar elements is not repeated herein. The difference between the embodiment of FIG. 5 and the embodiment of FIG. 1 is that, in FIG. 5, at least a portion of the first dummy pattern 103 is located between two adjacent first conductive patterns 101, and the second dummy pattern 203 is At least a portion is located between two adjacent second conductive patterns 201. In other words, there is no peripheral area in the embodiment of FIG. 5, and the first dummy pattern 103 and the second dummy pattern 203 are disposed in the core area CR. Similar to the embodiment of FIG. 1, the edge contour of the first dummy pattern 103 facing the second dummy pattern 203 and the edge contour of the second dummy pattern 203 facing the first dummy pattern 103 are non-linear. Therefore, the contact area between the first dummy pattern 103, the second dummy pattern 203, and the insulating sealing body 102 can be increased. According to this, the breakage between the conductive pattern (for example, the first conductive pattern 101, the second conductive pattern 201, the first dummy pattern 103, and the second dummy pattern 203) and the insulating sealing body 102 can be sufficiently eliminated, thereby improving the use. The reliability of the semiconductor package and electronic product of the carrier 10.

In summary, by changing the edge contour of the dummy pattern in the carrier, the break between the dummy pattern, the conductive pattern, and the insulating sealing body can be sufficiently eliminated, thereby improving the reliability of the semiconductor package and the electronic product using the carrier. Sex. Furthermore, by increasing the thickness of certain portions of the dummy pattern, the contact area between the dummy pattern and the insulating sealing body can be increased. The increased thickness portion of the dummy pattern can also be strategically placed in the region where the increased pressure is applied during the manufacturing process of the semiconductor package compared to other regions. Therefore, the occurrence of breakage can be reduced, and the reliability of the semiconductor package and the electronic product can be further ensured.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10, 10a‧‧‧ carrier board
100, 100a, 100b, 100c‧‧‧ areas
101‧‧‧First conductive pattern
102‧‧‧Insulation seal
103‧‧‧First virtual pattern
103a‧‧‧First Main Body
103b‧‧‧First protrusion
201‧‧‧Second conductive pattern
203‧‧‧Second virtual pattern
203a‧‧‧Second main body
203b‧‧‧second protrusion
CR‧‧‧ core area
PR‧‧‧ surrounding area
R1‧‧‧First wiring area
R2‧‧‧Second wiring area
W1, w2‧‧‧ thickness

1 is a schematic top plan view of a carrier plate in accordance with some embodiments of the present invention. 2A to 2D are schematic enlarged views of the area in Fig. 1, respectively. 3 is a schematic cross-sectional view taken along line AA' of FIG. 2A, in accordance with some embodiments of the present invention. 4 is a schematic cross-sectional view taken along line AA' of FIG. 2A, in accordance with some alternative embodiments of the present invention. Figure 5 is a schematic top plan view of a carrier plate in accordance with some alternative embodiments of the present invention.

10‧‧‧ Carrier Board

100‧‧‧ area

101‧‧‧First conductive pattern

201‧‧‧Second conductive pattern

103‧‧‧First virtual pattern

203‧‧‧Second virtual pattern

R1‧‧‧First wiring area

R2‧‧‧Second wiring area

CR‧‧‧ core area

PR‧‧‧ surrounding area

Claims (10)

A carrier board having a first wiring region and a second wiring region, comprising: an insulating sealing body; a plurality of first conductive patterns located in the first wiring region; and a plurality of second portions located in the second wiring region a conductive pattern, wherein the first conductive pattern and the second conductive pattern are embedded in the insulating sealing body, and the insulating sealing body exposes the first conductive pattern and a top surface of the second conductive pattern And at least one first dummy pattern located in the first wiring area and at least one second dummy pattern located in the second wiring area, wherein the first dummy pattern and the second dummy pattern are Insulating the first conductive pattern and the second conductive pattern, the first dummy pattern and the second dummy pattern are embedded in the insulating sealing body, the insulating sealing body exposing the first dummy pattern and a top surface of the second dummy pattern, and an edge contour of the first dummy pattern facing the second dummy pattern includes a rectangular zigzag shape, a V-shaped zigzag shape, and a semi-circular sawtooth Shape, wave shape or a combination thereof. The carrier board of claim 1, wherein the first wiring area and the second wiring area respectively comprise a peripheral area and a core area, and the first dummy pattern and the second dummy pattern are located In the peripheral region, the first dummy pattern surrounds the first conductive pattern, and the second dummy pattern surrounds the second conductive pattern. The carrier board of claim 2, wherein the first dummy pattern and the second dummy pattern are mesh structures. The carrier of claim 1, wherein at least a portion of the first dummy pattern is between two adjacent first conductive patterns, and at least a portion of the second dummy pattern is located adjacent to each other Between the second conductive patterns. The carrier board according to claim 1, wherein the first dummy pattern includes a first body portion and a plurality of first protrusions protruding toward the second dummy pattern, and the first protrusion portion The thickness is greater than the thickness of the first body portion. The carrier board according to claim 5, wherein the second dummy pattern includes a second body portion and a plurality of second protrusions protruding toward the first dummy pattern, and the second protrusion portion The thickness is greater than the thickness of the second body portion. The carrier of claim 5, wherein the first protrusion is located on an edge of the first dummy pattern. The carrier of claim 5, wherein the first protrusion is located in a region where the carrier receives pressure during a semiconductor package process. The carrier board of claim 1, wherein the first dummy pattern and the second dummy pattern are connected to ground, connected to a power source, or electrically floating. The carrier of claim 1, wherein the first conductive pattern, the second conductive pattern, the first dummy pattern, and a top surface of the second dummy pattern and the insulating sealing body The top surface is substantially coplanar.