JP2015149326A - パワーモジュールおよびその製造方法 - Google Patents
パワーモジュールおよびその製造方法 Download PDFInfo
- Publication number
- JP2015149326A JP2015149326A JP2014020022A JP2014020022A JP2015149326A JP 2015149326 A JP2015149326 A JP 2015149326A JP 2014020022 A JP2014020022 A JP 2014020022A JP 2014020022 A JP2014020022 A JP 2014020022A JP 2015149326 A JP2015149326 A JP 2015149326A
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- Prior art keywords
- power module
- lead frame
- buffer layer
- semiconductor device
- stress buffer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- LEONUFNNVUYDNQ-UHFFFAOYSA-N vanadium atom Chemical compound [V] LEONUFNNVUYDNQ-UHFFFAOYSA-N 0.000 description 1
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Abstract
【解決手段】パワーモジュール20は、第1金属回路パターン3と、第1金属回路パターン3上に配置された半導体デバイス1と、半導体デバイス1と電気的に接続されるリードフレーム15と、半導体デバイス1の上面に配置され、半導体デバイス1とリードフレーム15との間の熱膨張係数差を緩衝可能である応力緩衝層14とを備える。リードフレーム15は、応力緩衝層14を介して半導体デバイス1と接続されると共に、応力緩衝層14の熱膨張係数がリードフレーム15の熱膨張係数以下であり、かつ応力緩衝層14の断面形状がL字型である。
【選択図】図12
Description
比較例に係るパワーモジュールにおいて、半導体デバイス1上に配置された応力緩衝層(CuMo電極)254とリードフレーム(Cu)250とを接続する電極接続構造において、レーザ光hνを照射して、レーザ溶接部160を形成する様子を説明する模式的断面構造は、図1に示すように表される。
第1の実施の形態に係るパワーモジュールの製造技術として適用可能なレーザは、例えば、YAGレーザまたはYAGレーザの第2高調波、YLF(YLiF4:Yuttrium Lithium Fluoride)レーザ、YVO4(YVO4:Yuttrium Vanadium Qxide)レーザ、KrFレーザ、CO2レーザ、COレーザのいずれかである。
第1の実施の形態に係るパワーモジュール20の製造方法は、第1金属回路パターン3を形成する工程と、第1金属回路パターン3上に半導体デバイス1を形成する工程と、半導体デバイス1の上面に断面形状がL字型である応力緩衝層14を形成する工程と、半導体デバイス1の上面に垂直な方向の応力緩衝層14のL字側面において、リードフレーム15と応力緩衝層14を接続する工程とを有する。ここで、応力緩衝層14の熱膨張係数がリードフレーム15の熱膨張係数以下であり、応力緩衝層14は、半導体デバイス1とリードフレーム15との間の熱膨張係数差を緩衝可能である。
第1の実施の形態の変形例1に係るパワーモジュール20において、セラミックス基板4/第1金属回路パターン3/チップ下接合層2/半導体デバイス1/チップ上接合層9/L字構造の応力緩衝層14の積層構造の模式的断面構造は、図13(a)に示すように表され、上記の積層構造の厚さの異なる部分の模式的断面構造は、図13(b)に示すように表される。ここで、図13(a)は、図9において、I−I線に沿う模式的断面構造を表す図12(a)に沿う模式的断面構造に対応し、図13(b)は、図9において、II−II線に沿う模式的断面構造を表す図12(b)に沿う模式的断面構造に対応している。
第1の実施の形態の変形例2に係るパワーモジュール20において、セラミックス基板4/第1金属回路パターン3/チップ下接合層2/半導体デバイス1/チップ上接合層9/L字構造の応力緩衝層14の積層構造の模式的断面構造は、図14(a)に示すように表され、上記の積層構造の厚さの異なる部分の模式的断面構造は、図14(b)に示すように表される。ここで、図14(a)は、図9において、I−I線に沿う模式的断面構造を表す図12(a)に沿う模式的断面構造に対応し、図14(b)は、図9において、II−II線に沿う模式的断面構造を表す図12(b)に沿う模式的断面構造に対応している。
第2の実施の形態に係るパワーモジュール20は、図15に示すように、表面に半導体デバイス1を実装し、半導体デバイス1の上面にリードフレーム15を接合してなるパワーモジュールにおいて、半導体デバイス1とリードフレーム15間の熱膨張係数差の応力緩衝層14として、半導体デバイス1とリードフレーム15間に熱膨張係数の低い材料を挟み込む構造を備える。ここで、応力緩衝層14の熱膨張係数がリードフレーム15の熱膨張係数以下であり、かつ応力緩衝層14の形状がU字型である。
第2の実施の形態に係るパワーモジュール20の製造方法は、第1金属回路パターン3を形成する工程と、第1金属回路パターン3上に半導体デバイス1を形成する工程と、半導体デバイス1の上面に断面形状がU字型である応力緩衝層14Rを形成する工程と、半導体デバイス1の上面と離隔され、かつ半導体デバイス1の上面に平行な方向の応力緩衝層14RのU字側面において、リードフレーム15と応力緩衝層14Rを接続する工程とを有する。応力緩衝層14Rの熱膨張係数がリードフレーム15の熱膨張係数以下であり、応力緩衝層14Rは、半導体デバイス1とリードフレーム15との間の熱膨張係数差を緩衝可能である。
第3の実施の形態に係るパワーモジュール200であって、ツーインワンモジュール(2 in 1 Module:ハーフブリッジ内蔵モジュール)において、モールド樹脂層33を形成前の模式的平面パターン構成は図16に示すように表される。ここで、図16において、基板4はセラミックス基板に対応し、基板40は、変形例としての絶縁層基板(図19)に対応する。
第3の実施の形態に係るパワーモジュール200の製造技術として適用可能なレーザは、レーザ照射用窓を介して、溶接部16照射される。レーザ照射用窓は、レーザ光hνが溶接部16に照射可能な空間的なスペースであれば良い。レーザ光hνの照射方向は、図16・図18では、リードフレーム15−1に張り合わされる応力緩衝層14−1のL字の内側面に垂直な方向である。一方、レーザ光hνは応力緩衝層14−1のL字の外側面に張り合わされるリードフレーム15−1に垂直な裏面方向から照射しても良い。
また、第3の実施の形態の変形例に係るパワーモジュール200であって、図16において、IIA−IIA方向から観測した側面図は、図19に示すように表される。また、図19のA部分の拡大図は、図20に示すように表される。また、モールド樹脂層33を形成後の模式的鳥瞰構成は図21と同様に表される。
第4の実施の形態に係るパワーモジュール200であって、ツーインワンモジュール(ハーフブリッジ内蔵モジュール)において、モールド樹脂層を形成前の模式的鳥瞰構成は、図22に示すように表される。第4の実施の形態に係るパワーモジュール200においては、図22に示すように、絶縁回路基板を使用せず、ドレインD4・ソースS1、ソースS4、ドレインD1などに対応する金属箔もしくは金属板(金属フレーム)を利用している。
第4の実施の形態の変形例に係るパワーモジュール200であって、ツーインワンモジュール(ハーフブリッジ内蔵モジュール)において、モールド樹脂層を形成前の模式的鳥瞰構成は、図23に示すように表される。第4の実施の形態の変形例に係るパワーモジュール200は、第4の実施の形態に係るパワーモジュール200と半導体デバイスQ1・DI1・Q4・DI4の配置構成を変更している。その他の構成は、第4の実施の形態と同様である。また、第4の実施の形態の変形例に係るパワーモジュールの製造方法も第1の実施の形態と同様である。
第5の実施の形態に係るパワーモジュール200であって、ツーインワンモジュール(ハーフブリッジ内蔵モジュール)において、モールド樹脂層33を形成前の模式的平面パターン構成は、図24に示すように表され、モールド樹脂層33を形成後の模式的鳥瞰構成は、図21と同様に表される。図24において、IIIA−IIIA方向から観測した側面図は、図25(a)に示すように表され、図25(a)のB部分の拡大図は、図25(b)に示すように表される。第5の実施の形態において、第4実施の形態との違いは、半導体デバイスQ1・DI1・Q4・DI4上に応力緩衝層を接合するのは同様であるが、その形状がL字形状ではなく、U字形状を有していることである。
以下、実施の形態に係るパワーモジュールの具体例を説明する。もちろん、以下に説明するパワーモジュールにおいても、表面に半導体デバイスを実装し、半導体デバイスの上面にリードフレームを接合してなるパワーモジュールにおいて、半導体デバイスとリードフレーム間の熱膨張係数差の応力緩衝層として、半導体デバイスとリードフレーム間に熱膨張係数の低い材料を挟み込む構造を備え、応力緩衝層の熱膨張係数がリードフレームの熱膨張係数以下であり、かつ応力緩衝層の形状がL字型若しくはU字型を備える点は、上記の実施の形態と同様である。リードフレーム構造により小型化・大電流容量化、低コスト化可能で、かつ半導体デバイスを損傷することなく溶接のバラツキを抑制し歩留まりを向上したパワーモジュールおよびその製造方法を提供することができる点も、上記の実施の形態と同様である。
実施の形態に係るパワーモジュールに適用可能な半導体デバイスの例であって、SiC MISFETの模式的断面構造は、図29(a)に示すように表され、IGBTの模式的断面構造は、図29(b)に示すように表される。
実施の形態に係るパワーモジュールに適用可能な半導体デバイス110の例であって、SiC DIMISFETの模式的断面構造は、図32に示すように表される。
実施の形態に係るパワーモジュールに適用可能な半導体デバイス110の例であって、SiC TMISFETの模式的断面構造は、図33に示すように表される。
次に、図35を参照して、半導体デバイスとしてSiC MISFETを適用した実施の形態に係るパワーモジュールを用いて構成した3相交流インバータ140について説明する。
上記のように、本発明を実施の形態によって記載したが、この開示の一部をなす論述および図面は例示的なものであり、この発明を限定するものであると理解すべきではない。この開示から当業者には様々な代替実施の形態、実施例および運用技術が明らかとなろう。
2…チップ下接合層(チップ下半田層、Ag)
3…第1金属回路パターン(表面銅箔、金属フレーム)
4…絶縁基板(セラミックス基板)
51、52…ボンディングワイヤ
6…第2金属回路パターン(表面銅箔、金属フレーム)
7…裏面銅箔
8…絶縁回路基板
9…チップ上接合層(チップ上半田層)
10…応力緩衝層
11…応力緩衝層上接合層
12、15、15−1、15−4…リードフレーム
13…リードフレーム下接合層
14、14−1、14−4…応力緩衝層(L字金具)
14R、14R−1、14R−4…応力緩衝層(U字金具)
16、17…溶接部(レーザ溶接部、スポット溶接部)
20、20A、20T、200…パワーモジュール
33…モールド樹脂層
34…レーザ照射用窓
40…絶縁層基板(有機絶縁樹脂層)
Claims (31)
- 第1金属回路パターンと、
前記第1金属回路パターン上に配置された半導体デバイスと、
前記半導体デバイスと電気的に接続されるリードフレームと、
前記半導体デバイスの上面に配置され、前記半導体デバイスと前記リードフレームとの間の熱膨張係数差を緩衝可能である応力緩衝層と
を備え、前記リードフレームは、前記応力緩衝層を介して前記半導体デバイスと接続されると共に、前記応力緩衝層の熱膨張係数が前記リードフレームの熱膨張係数以下であり、かつ前記応力緩衝層の断面形状がL字型であることを特徴とするパワーモジュール。 - 前記リードフレームと前記応力緩衝層は、前記半導体デバイスの上面に垂直な方向の前記応力緩衝層のL字側面において接続されることを特徴とする請求項1に記載のパワーモジュール。
- 前記リードフレームはレーザ照射用窓を備え、前記レーザ照射用窓を介して前記リードフレームと対向する別のリードフレームへのレーザ照射が可能であることを特徴とする請求項1または2に記載のパワーモジュール。
- 第1金属回路パターンと、
前記第1金属回路パターン上に配置された半導体デバイスと、
前記半導体デバイスと電気的に接続されるリードフレームと、
前記半導体デバイスの上面に配置され、前記半導体デバイスと前記リードフレームとの間の熱膨張係数差を緩衝可能である応力緩衝層と
を備え、前記リードフレームは、前記応力緩衝層を介して前記半導体デバイスと接続されると共に、前記応力緩衝層の熱膨張係数が前記リードフレームの熱膨張係数以下であり、かつ前記応力緩衝層の断面形状がU字型であることを特徴とするパワーモジュール。 - 前記リードフレームと前記応力緩衝層は、前記半導体デバイスの上面と離隔され、かつ前記半導体デバイスの上面に平行な方向の前記応力緩衝層のU字側面において接続されることを特徴とする請求項4に記載のパワーモジュール。
- 前記応力緩衝層と前記リードフレームは、レーザによる溶接で接合されることを特徴とする請求項1〜5のいずれか1項に記載のパワーモジュール。
- 前記応力緩衝層と前記リードフレームは、スポット溶接により接合されることを特徴とする請求項1〜5のいずれか1項に記載のパワーモジュール。
- 前記金属回路パターン表面と前記半導体デバイスとの電気的接合は、焼成銀を用いて実施されることを特徴とする請求項1〜7のいずれか1項に記載のパワーモジュール。
- 前記半導体デバイスと前記応力緩衝層との電気的接合は、焼成銀を用いて実施されることを特徴とする請求項1〜8のいずれか1項に記載のパワーモジュール。
- 前記応力緩衝層は、コバール若しくはインバーであることを特徴とする請求項1〜9のいずれか1項に記載のパワーモジュール。
- 前記応力緩衝層は、Fe―Ni系合金若しくはNi−Mo−Fe系合金であることを特徴とする請求項1〜9のいずれか1項に記載のパワーモジュール。
- 前記リードフレームと接続される第2金属回路パターンを備えることを特徴とする請求項1〜11のいずれか1項に記載のパワーモジュール。
- 前記リードフレームと第2金属回路パターンは、レーザによる溶接で接合されることを特徴とする請求項12に記載のパワーモジュール。
- 前記リードフレームと第2金属回路パターンは、スポット溶接により接合されることを特徴とする請求項12に記載のパワーモジュール。
- 前記レーザは、YAGレーザまたはYAGレーザの第2高調波、YLFレーザ、YVO4レーザ、KrFレーザ、CO2レーザ、COレーザのいずれかであることを特徴とする請求項6または13に記載のパワーモジュール。
- 基板を備え、
前記第1金属回路パターンは、前記基板上に配置されることを特徴とする請求項1〜15のいずれか1項に記載のパワーモジュール。 - 前記基板は、DBC基板、DBA基板若しくはAMB基板のいずれかであることを特徴とする請求項15または16に記載のパワーモジュール。
- 絶縁層基板を備え、
前記第1金属回路パターンは、前記絶縁層基板上に配置されることを特徴とする請求項1〜14のいずれか1項に記載のパワーモジュール。 - 前記絶縁層基板は、有機絶縁樹脂層であることを特徴とする請求項18に記載のパワーモジュール。
- 樹脂層を備え、
前記樹脂層により、トランスファーモールド成型されることを特徴とする請求項1〜19のいずれか1項に記載のパワーモジュール。 - 前記パワーモジュールは、ワンインワン、ツーインワン、フォーインワン、シックスインワンもしくはセブンインワン型のいずれかに形成されることを特徴とする請求項1〜20のいずれか1項に記載のパワーモジュール。
- 前記半導体デバイスは、IGBT、ダイオード、Si系MISFET、SiC系MISFET、GaNFETのいずれかを備えることを特徴とする請求項1〜21のいずれか1項に記載のパワーモジュール。
- 第1金属回路パターンを形成する工程と、
前記第1金属回路パターン上に半導体デバイスを形成する工程と、
前記半導体デバイスの上面に断面形状がL字型である応力緩衝層を形成する工程と、
前記半導体デバイスの上面に垂直な方向の前記応力緩衝層のL字側面において、リードフレームと前記応力緩衝層を接続する工程と
を有し、
前記応力緩衝層の熱膨張係数が前記リードフレームの熱膨張係数以下であり、前記応力緩衝層は、前記半導体デバイスと前記リードフレームとの間の熱膨張係数差を緩衝可能であることを特徴とするパワーモジュールの製造方法。 - 第1金属回路パターンを形成する工程と、
前記第1金属回路パターン上に半導体デバイスを形成する工程と、
前記半導体デバイスの上面に断面形状がU字型である応力緩衝層を形成する工程と、
前記半導体デバイスの上面と離隔され、かつ前記半導体デバイスの上面に平行な方向の前記応力緩衝層のU字側面において、リードフレームと前記応力緩衝層を接続する工程と
を有し、
前記応力緩衝層の熱膨張係数が前記リードフレームの熱膨張係数以下であり、前記応力緩衝層は、前記半導体デバイスと前記リードフレームとの間の熱膨張係数差を緩衝可能であることを特徴とするパワーモジュールの製造方法。 - 前記リードフレームと前記応力緩衝層を接続する工程は、レーザ溶接により実施されることを特徴とする請求項23または24に記載のパワーモジュールの製造方法。
- 前記リードフレームと前記応力緩衝層を接続する工程は、スポット溶接により実施されることを特徴とする請求項23または24に記載のパワーモジュールの製造方法。
- 第2金属回路パターンを形成する工程と、
前記第2金属回路パターンと前記リードフレームを接続する工程と
を有することを特徴とする請求項23または24に記載のパワーモジュールの製造方法。 - 前記第2金属回路パターンと前記リードフレームを接続する工程は、レーザ溶接により実施されることを特徴とする請求項27に記載のパワーモジュールの製造方法。
- 前記第2金属回路パターンと前記リードフレームを接続する工程は、スポット溶接により実施されることを特徴とする請求項27に記載のパワーモジュールの製造方法。
- 基板を準備する工程と、
前記第1金属回路パターンを前記基板上に配置する工程と
を有することを特徴とする請求項23〜26のいずれか1項に記載のパワーモジュールの製造方法。 - 絶縁層基板を準備する工程と、
前記第1金属回路パターンを前記絶縁層基板上に配置する工程と
を有することを特徴とする請求項23〜26のいずれか1項に記載のパワーモジュールの製造方法。
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JP2017098356A (ja) * | 2015-11-20 | 2017-06-01 | 株式会社三社電機製作所 | 半導体モジュール |
DE112018002384T5 (de) | 2017-05-10 | 2020-01-16 | Rohm Co., Ltd. | Leistungshalbleitereinrichtung und Fertigungsverfahren für selbige |
WO2020105476A1 (ja) * | 2018-11-22 | 2020-05-28 | ローム株式会社 | 半導体装置 |
JPWO2020179369A1 (ja) * | 2019-03-05 | 2020-09-10 | ||
JPWO2020255663A1 (ja) * | 2019-06-20 | 2020-12-24 | ||
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US10381244B2 (en) | 2019-08-13 |
US20160343590A1 (en) | 2016-11-24 |
JP6475918B2 (ja) | 2019-02-27 |
US9881812B2 (en) | 2018-01-30 |
WO2015119110A1 (ja) | 2015-08-13 |
DE112015000660T5 (de) | 2016-12-01 |
US20180090338A1 (en) | 2018-03-29 |
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