CN113646887A - 半导体模块 - Google Patents
半导体模块 Download PDFInfo
- Publication number
- CN113646887A CN113646887A CN202080025053.2A CN202080025053A CN113646887A CN 113646887 A CN113646887 A CN 113646887A CN 202080025053 A CN202080025053 A CN 202080025053A CN 113646887 A CN113646887 A CN 113646887A
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- China
- Prior art keywords
- semiconductor module
- semiconductor element
- gate via
- semiconductor
- protrusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 195
- 229910052751 metal Inorganic materials 0.000 claims abstract description 57
- 239000002184 metal Substances 0.000 claims abstract description 57
- 239000000463 material Substances 0.000 claims abstract description 38
- 238000007747 plating Methods 0.000 claims description 35
- 239000000758 substrate Substances 0.000 claims description 20
- 230000008878 coupling Effects 0.000 claims description 15
- 238000010168 coupling process Methods 0.000 claims description 15
- 238000005859 coupling reaction Methods 0.000 claims description 15
- 230000002093 peripheral effect Effects 0.000 claims description 8
- 229910000679 solder Inorganic materials 0.000 abstract description 17
- 230000004048 modification Effects 0.000 description 15
- 238000012986 modification Methods 0.000 description 15
- 230000000694 effects Effects 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 230000000630 rising effect Effects 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910010293 ceramic material Inorganic materials 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 229910000640 Fe alloy Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000004519 grease Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
- 239000000057 synthetic resin Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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Abstract
确保焊料的厚度并且抑制芯片与引线框之间的应力集中。半导体模块(1)包括:半导体元件(3),其在上表面以沿规定方向延伸的方式形成有栅极通路(31);以及金属布线板(4),其配置于半导体元件的上表面。金属布线板具有经由第1接合材料接合于半导体元件的上表面的第1接合部(40)。第1接合部具有朝向半导体元件突出的至少一个第1突起部(45)。第1突起部设于俯视时不与栅极通路重叠的位置。栅极通路与第1突起部分开0.4mm以上。
Description
技术领域
本发明涉及一种半导体模块。
背景技术
半导体装置具有被设置有IGBT(Insulated Gate Bipolar Transistor:绝缘栅双极晶体管)、功率MOSFET(Metal Oxide Semiconductor Field Effect Transistor:金属氧化物半导体场效应晶体管)、FWD(Free Wheeling Diode:续流二极管)等半导体元件的基板,半导体装置被利用于变换器装置等。
例如,在以下所示的专利文献1~3中,提案有一种在功率半导体芯片的发射极电极焊接接合有引线框的构造。
现有技术文献
专利文献
专利文献1:日本特开2001-110957号公报
专利文献2:日本特开2012-142521号公报
专利文献3:日本特开2018-163932号公报
发明内容
发明要解决的问题
在这种半导体模块中,伴随着开关动作,芯片会发热。如上所述,在功率半导体芯片的表面焊接接合有引线框的构造中,由于伴随温度变化所产生的内部应力变动,可能导致接合部分产生应变。
本发明即是鉴于这一点而做成的,其一个目的在于提供一种能够确保焊料的厚度并且抑制芯片与引线框之间的应力集中的半导体模块。
用于解决问题的方案
本发明的一技术方案为一种半导体模块,该半导体模块包括:半导体元件,其在上表面以沿规定方向延伸的方式形成有栅极通路;以及金属布线板,其配置于所述半导体元件的上表面,所述金属布线板具有第1接合部,该第1接合部经由第1接合材料接合于所述半导体元件的上表面,所述第1接合部具有朝向所述半导体元件突出的至少一个第1突起部,所述第1突起部设于俯视时不与所述栅极通路重叠的位置,所述栅极通路与所述第1突起部分开0.4mm以上。
发明的效果
根据本发明,能够确保焊料的厚度并且抑制芯片与引线框之间的应力集中。
附图说明
图1是本实施方式的半导体装置的俯视图。
图2是将图1所示的半导体装置沿着A-A线剖切开的剖视图。
图3是图1的局部放大图。
图4是图2的局部放大图。
图5是变形例的半导体元件的俯视图。
图6是另一变形例的半导体元件的俯视图。
图7是变形例的金属布线板的俯视图。
图8是另一变形例的金属布线板及其周边的俯视图。
图9是另一变形例的金属布线板及其周边的剖视图。
具体实施方式
以下,说明能够应用本发明的半导体装置。图1是本实施方式的半导体装置的俯视图。图2是将图1所示的半导体装置沿着A-A线剖切开的剖视图。此外,以下所示的半导体装置仅为一个例子,并不限定于此,能够适当变更。
另外,在以下的附图中,将半导体装置的长边方向(后述的多个电路板排列的方向)定义为X方向,将短边方向定义为Y方向,将高度方向定义为Z方向。图示的X轴、Y轴、Z轴互相正交,并构成右手系。另外,根据情况,有时将X方向称作左右方向,将Y方向称作前后方向,将Z方向称作上下方向。这些方向(前后左右上下方向)是为了方便说明而使用的用语,根据半导体模块的安装姿势,XYZ方向的各方向之间的对应关系有时会改变。例如,会将半导体装置的散热面侧(冷却器侧)称作下表面侧,将其相反侧称作上表面侧。另外,在本说明书中,俯视是指从Z方向正侧观察半导体模块的上表面的情况。
半导体装置100例如应用于功率模块等电力转换装置。如图1和图2所示,半导体装置100通过在冷却器10的上表面配置半导体模块1而构成。相对于半导体模块1而言,冷却器10为任意的结构。
冷却器10将半导体模块1的热向外部释放,整体具有长方体形状。冷却器10构成为在基底板的下表面侧设置多个散热片,并将这些散热片收容于水冷套,该情况未特别图示。此外,冷却器10并不限定于此,能够适当变更。
半导体模块1通过在壳体11内配置层叠基板2、半导体元件3以及金属布线板4等而构成。
层叠基板2通过层叠金属层和绝缘层而形成,例如由DCB(Direct CopperBonding:直接铜键合)基板、AMB(Active Metal Brazing:活性金属钎焊)基板、或金属基底基板构成。具体而言,层叠基板2具有绝缘板20、配置于绝缘板20的下表面的金属板21、配置于绝缘板20的上表面的多个电路板(后述的第1电路板22a和第2电路板22b)。层叠基板2例如形成为相比于Y方向而在X方向上较长的俯视矩形形状。
绝缘板20形成为在Z方向上具有规定的厚度,并具有上表面和下表面的平板状。绝缘板20例如由氧化铝(Al2O3)、氮化铝(AlN)、氮化硅(Si3N4)等陶瓷材料、环氧等树脂材料、或使用陶瓷材料作为填料的环氧树脂材料等绝缘材料形成。此外,绝缘板20也可以被称作绝缘层或绝缘薄膜。
金属板21形成为在Z方向上具有规定的厚度,并覆盖绝缘板20的大致整个下表面。金属板21例如由铜、铝、或将铜、铝设为母材的合金等导热性良好的金属板形成。金属板21的下表面成为散热面。金属板21经由焊料等接合材料S1接合于冷却器10的上表面。金属板21也可以经由导热脂、导热膏等热传导材料配置于冷却器10的上表面。
在绝缘板20的主表面,多个电路板形成为岛状(互相电绝缘的状态)。在本实施方式中,在绝缘板20的上表面形成有两个电路板(第1电路板22a和第2电路板22b)。利用由铜箔等形成的规定厚度的金属层构成这些电路板。第1电路板22a和第2电路板22b具有俯视矩形形状,在绝缘板20上沿X方向排列配置。在图1中,第1电路板22a位于左侧(X方向负侧),第2电路板22b位于右侧(X方向正侧)。
在第1电路板22a的上表面经由焊料等接合材料S2配置有半导体元件3。半导体元件3由例如硅(Si)、碳化硅(SiC)等的半导体基板形成为俯视方形形状。在本实施方式中,半导体元件3由将IGBT(Insulated Gate Bipolar Transistor)元件和FWD(Free WheelingDiode)元件的功能一体化而成的RC(Reverse Conducting:反向导通)-IGBT元件构成。
此外,半导体元件3并不限定于此,也可以组合IGBT、功率MOSFET(Metal OxideSemiconductor Field Effect Transistor)等开关元件、FWD(Free Wheeling Diode)等二极管而构成。另外,作为半导体元件3也可以使用对反偏压具有充分的耐压的RB(ReverseBlocking:反向阻断)-IGBT等。半导体元件3可以是纵型的开关元件和二极管。另外,半导体元件3的形状、配置数量、配置部位等能够适当变更。
另外,半导体元件3在上表面和下表面分别形成有电极。例如,上表面侧的电极(上表面电极)由发射极电极(源电极)或栅极电极构成,下表面侧的电极(下表面电极)由集电极(漏极电极)构成。另外,在半导体元件3的上表面以分割半导体元件3的中央的方式形成有栅极焊盘30和构成针对该栅极焊盘30的栅极布线的栅极通路31。半导体元件3的表面的详细构造后述说明。
在半导体元件3的上表面配置有金属布线板4。金属布线板4由具有上表面和下表面的板状体构成,例如,由铜原材料、铜合金系原材料、铝合金系原材料、铁合金系原材料等金属原材料形成。金属布线板4例如利用冲压加工形成为规定的形状。此外,以下所示的金属布线板4的形状仅表示一个例子,能够适当变更。另外,金属布线板也可以被称作引线框。
本实施方式的金属布线板4为俯视时以跨过第1电路板22a和第2电路板22b的方式沿X方向延伸的长条体,侧视时具有弯曲多次的曲柄形状。具体而言,金属布线板4构成为包含经由接合材料S3(第1接合材料)接合于半导体元件3的上表面的第1接合部40、经由接合材料S4(第2接合材料)接合于第2电路板22b的上表面的第2接合部41、连结第1接合部40和第2接合部41的连结部42。金属布线板4的Y方向的宽度自第1接合部40到第2接合部41成为一样的大小。另外,第1接合部40、第2接合部41以及连结部42配置为俯视时沿着X方向排成一列。更具体而言,第1接合部40、第2接合部41以及连结部42配置为沿着与栅极通路31的延伸方向(Y方向)垂直的方向(X方向)、即后述的多个第2突起部46排列的方向排成一列。
第1接合部40具有俯视时小于半导体元件3的外形的矩形形状。在第1接合部40的X方向正侧(第2电路板22b侧)的端部形成有以大致直角弯曲并向上方立起的第1弯曲部43。在第1弯曲部43的上端连结有连结部42的一端(左端)。在第1接合部40的下表面形成有朝向半导体元件3突出的第1突起部45,其详细情况后述说明。
第2接合部41具有俯视时小于第2电路板22b的外形的矩形形状。在第2接合部41的X方向负侧(第1电路板22a侧)的端部形成有以大致直角弯曲并向上方立起的第2弯曲部44。在第2弯曲部44的上端连结有连结部42的另一端(右端)。在第2接合部41的下表面形成有朝向第2电路板22b突出的第2突起部46,其详细情况后述说明。
连结部42沿水平方向延伸,如上所述,一端连结于第1弯曲部43,另一端连结于第2弯曲部44。
第1弯曲部43的Z方向的长度比第2弯曲部44短与半导体元件3的厚度对应的量。即,第1接合部40和第2接合部41设于高度不同的位置。更具体而言,第1接合部40设于高于第2接合部41的位置。
如上所述,第1接合部40经由焊料等接合材料S3与半导体元件3的主电极的上表面电接合。另外,第2接合部41经由焊料等接合材料S4与第2电路板22b的上表面电接合。
层叠基板2、半导体元件3以及金属布线板4的周围被壳体11包围。壳体11具有俯视时呈四方环状的筒形状或框形状,例如由合成树脂形成。壳体11的下端经由粘接剂粘接于冷却器10的上表面,上端延伸到充分高于金属布线板4的上表面的位置。即,壳体11划定收容层叠基板2、半导体元件3以及金属布线板4的空间。
如上所述,在由壳体11规定的内部空间填充密封树脂5。密封树脂5可以填充到上表面到达壳体11的上端为止。由此,层叠基板2、半导体元件3以及金属布线板4被密封。此外,密封树脂5能够使用环氧树脂、硅凝胶。
另外,如上所述,在将由硅、碳化硅等的半导体基板制成的半导体元件和由铜等金属制成的金属布线板(引线框)焊接而成的构造中,伴随着半导体元件的开关动作,芯片会发热。伴随着这样的温度变化,在接合部周边,由膨胀和收缩量的不同而可能产生剪切应力(内部应力)。该剪切应力具有在接合部的外缘部分成为最大的倾向。
另外,在大容量的半导体元件中,如上所述,具有以分割半导体元件的中央的方式设有作为栅极布线的栅极通路的情况。因此,半导体元件与金属布线板之间的焊料被栅极通路分割。其结果,在沿栅极通路的边界部分也可能集中剪切应力。
因此,作为缓和剪切应力的对策,增大半导体元件与金属布线板之间的焊料的厚度、扩大弹性模量较大的半导体元件与弹性模量相对较小的金属布线板之间的间隔的方法是有效的。
然而,除半导体元件与金属布线板之间的接合以外,在半导体元件与绝缘基板之间的接合、绝缘基板与冷却器用的基底板之间的接合等焊接接合遍及多层地实施的构造中,难以将焊料的厚度控制在能够得到应力缓和效果的程度。作为确保该焊料厚度的方法,还考虑在金属布线板设置凸台的方法,但凸台自身可能成为应力集中点而引起接合部分的断裂。
于是,本申请发明人们着眼于用于确保焊料厚度的凸台与可能产生应力集中的栅极通路之间的位置关系,想到了本发明。具体而言,在本实施方式中,在半导体元件3的上表面以沿规定方向(本实施方式中为Y方向)延伸的方式形成有栅极通路31。金属布线板4具有经由接合材料S3接合于半导体元件3的上表面的第1接合部40。在第1接合部40的背面侧形成有朝向半导体元件3突出的第1突起部45。第1突起部45设于俯视时不与栅极通路31重叠的位置。第1突起部45可以设为俯视时与栅极通路31分开。而且,发明人们得出以下见解:通过使栅极通路31与第1突起部45分开0.4mm以上,能够确保焊料的厚度,并且抑制半导体元件与金属布线板之间的应力集中。
根据该结构,由于设有第1突起部45,因而能够在第1接合部40与半导体元件3之间确保至少与第1突起部45的高度对应的量的间隙。通过利用接合材料S3填埋该间隙,能够确保接合材料S3的厚度。另外,通过以俯视时不与栅极通路31重叠的方式配置第1突起部45,并确保它们的距离为0.4mm以上,能够充分地确保栅极通路31周边的接合材料S3的厚度,能够抑制应力集中。如此,能够确保焊料的厚度,并且抑制半导体元件与金属布线板之间的应力集中。
另外,还在第2接合部41的背面侧形成有朝向第2电路板22b突出的第2突起部46。由此,能够在第2接合部41与半导体元件3之间确保至少与第2突起部46的高度对应的量的间隙。通过利用接合材料S4填埋该间隙,能够确保接合材料S4的厚度。
接着,参照图3和图4,说明半导体元件的表面的详细构造。图3是图1的局部放大图。图4是图2的局部放大图。此外,半导体元件的表面构造并不限定于以下所示的例子,能够适当变更。
如图3所示,在半导体元件3的上表面,栅极焊盘30配置于Y方向正侧的端部中央。栅极焊盘30构成栅极电极。另外,在半导体元件3的上表面形成有栅极通路31。栅极通路31在X方向上具有规定宽度,并沿Y方向延伸。另外,栅极通路31的一端与栅极焊盘30相连而另一端延伸到半导体元件3的Y方向负侧的端部。利用栅极通路31,将半导体元件3的上表面中央在X方向上分割为两部分。
更详细而言,如图4所示,在半导体元件3的上表面设有规定厚度的上表面电极32。上表面电极32形成于半导体元件3的基板上表面中的规定区域。上述的栅极焊盘30形成于与上表面电极32分离(独立)的区域。上表面电极32例如构成发射极电极。上表面电极32例如由铝、含有铝等金属形成。
在上表面电极32的上表面设有规定厚度的镀层33。镀层33例如由镍、含有镍等金属形成。上述的栅极通路31以贯穿镀层33的方式形成于上表面电极32的上表面。
栅极通路31具有由掺杂有杂质的多晶硅等形成的导电部(未图示)和覆盖该导电部的由聚酰亚胺等形成的绝缘部。绝缘部起到使导电部与上表面电极32、镀层33以及接合材料S3绝缘的作用。栅极通路31(绝缘部)的上表面设于高于镀层33的上表面的位置。即,栅极通路31的厚度设定得大于镀层33的厚度。
另外,栅极通路31的X方向的两侧面以随着朝向上方去而相对间隔(宽度)变窄的方式倾斜。由此,栅极通路31的截面形成梯形形状(参照图4)。相对于此,与栅极通路31的侧面相对的镀层33的侧面以随着朝向上方去而远离栅极通路31的侧面的方式倾斜。即,栅极通路31的侧面与镀层33的侧面之间的相对间隔随着远离上表面电极32而变大。
如此,在半导体元件3的上表面形成有边界部34,上述的栅极通路31、上表面电极32以及镀层33在该边界部34互相集中。在边界部34,栅极通路31、上表面电极32以及镀层33也可以相接近而局部接触或重叠。边界部34形成为沿着栅极通路31的下端部外缘在Y方向上延伸的线状。此外,在图4所示的剖视时,边界部34也可以被称作三重临界点。半导体元件3也可以在其上表面沿镀层33的周围设有保护环35。栅极通路31的端部与保护环35相连。
接着,说明金属布线板4的详细构造。如图3和图4所示,在第1接合部40的下表面设有多个第1突起部45。在本实施方式中,第1突起部45在X方向上各设有两个,在Y方向上各设有三个,合计设有六个。六个第1突起部45沿着第1接合部40的外周缘配置。
例如,第1突起部45在X方向上设于与保护环35分开了规定距离X1、与栅极通路31分开了规定距离X2的位置。另外,在Y方向上,位于最外周侧的位置的第1突起部45设于第1接合部40的在Y方向上与保护环35分开了规定距离Y1、Y2的位置。栅极通路31与第1突起部45之间的距离(X2)在俯视时为0.4mm以上。在X方向上两两排列配置的第1突起部45以俯视时隔着栅极通路31的方式配置。栅极通路31可以配置于成对的两个第1突起部45之间。而且,保护环35与第1突起部45之间的距离(X1、Y1、Y2)也可以为0.4mm以上。
第1突起部45例如具有外径为D1的圆柱形状。另外,第1突起部45自第1接合部40的下表面朝向半导体元件3以突出高度Z1突出。第1突起部45的侧面(圆筒面)相对于第1接合部40的下表面形成为垂直。第1突起部45的外径D1例如为0.4mm~1.5mm,优选可以为0.6mm~1.2mm。若外径D1较大,则第1突起部45与栅极通路31之间的距离减小而设计的自由度下降,若外径D1较小,则作用于上表面电极32的应力集中而并不优选。另外,第1突起部45的突出高度Z1可以为50μm以上且300μm以下,优选可以为100μm~200μm。若突出高度Z1较大,则容易在接合材料S3产生空隙,若突出高度Z1较小,则接合材料S变薄,作用于上表面电极32的应力变大。
另外,如图1和图2所示,在第2接合部41的下表面设有多个第2突起部46。在本实施方式中,在Y方向上排列设置有两个第2突起部46。两个第2突起部46偏向第2接合部41的外周侧地配置。第2突起部46的形状可以与上述的第1突起部45相同,也可以不同。
上述的第1突起部45和第2突起部46的形状、配置以及配置数量并不限定于此,能够适当变更。例如,第1突起部45、第2突起部46并不限定于圆柱形状,也可以是棱柱形状、随着朝向下方去而顶端变细的截头圆锥形状、半球形状。
在这样构成的半导体模块1中,第1突起部45设于俯视时不与栅极通路31重叠的位置(参照图3),栅极通路31和第1突起部45设于分开了规定距离X2的位置(参照图4)。更具体而言,边界部34与第1突起部45的外缘部分开规定距离X2。该情况下,规定距离X2优选为0.4mm以上。
根据该结构,由于第1突起部45不与栅极通路31重叠,因而在栅极通路31的周围,能够在半导体元件3与第1接合部40之间确保与第1突起部45的突出高度Z1对应的接合材料S3的厚度。如上所述,由于边界部34为应力可能集中的部位,因而通过在边界部34的周边确保接合材料S3的厚度,能够提高抑制应力集中的效果。
另外,在第1突起部45的下表面与半导体元件3的上表面之间,接合材料S3的厚度相对变薄。然而,第1突起部45与边界部34分开了规定距离X2,第1突起部45的下表面与镀层33相对。镀层33与边界部34相比刚性较高,不易受到应力集中的影响。因此,即使在接合材料S3的厚度相对较薄的情况下,也不存在问题。
另外,在本实施方式中,优选的是,多个第1突起部45的合计面积为第1接合部40的面积的0.5%以上且25%以下。即,作为更优选的范围,多个第1突起部45与第1接合部40的面积比为1.0%以上且20%以下。具体而言,相对于宽度为7mm的第1接合部40而言,在具有四个0.4mm的第1突起部45的情况下,其面积比为1%。另外,在具有四个1.5mm的第1突起部45的情况下,面积比为20%,在具有六个1.6mm的第1突起部45的情况下,面积比为25%。设定为这样的范围的理由是因为,若第1突起部45过小,则应力集中于第1突起部45附近,导致上表面电极32的破损。另一方面是因为,若第1突起部45过大,则接合材料S的较薄的部分的面积变大,担心在接合材料S的较薄的部分产生裂纹、剥离。
另外,在本实施方式中,多个第1突起部45沿着第1接合部40的外周缘配置于自该外周缘起的规定范围内。因此,能够将矩形形状的第1接合部40稳定地配置于半导体元件3上,能够防止金属布线板4自身的倾倒。同样地,多个第2突起部46偏向第2接合部41的外周侧地配置。因此,能够将矩形形状的第2接合部41稳定地配置于第2电路板22b上。特别是,由于第1接合部40与第2接合部41在Z方向上的高度不同,因此容易倾倒。在本实施方式中,能够利用多个第1突起部45和第2突起部46容易地保持金属布线板4的姿势。
接着,说明变形例。在上述实施方式中,说明了在半导体元件3的上表面中央形成沿Y方向延伸的栅极通路31的情况,但栅极通路的形状并不限定于此,能够适当变更。例如,也可以是图5和图6所示的结构。图5是变形例的半导体元件的俯视图。图6是另一变形例的半导体元件的俯视图。此外,在以下所示的变形例中,由于仅栅极通路的结构与上述实施方式不同,因而主要对不同点进行说明,对共通的结构标注相同的附图标记并适当省略说明。
如图5所示,变形例的栅极通路形成为格栅状。具体而言,栅极通路由沿Y方向延伸的第1引线部31a和沿X方向延伸的第2引线部31b构成。第1引线部31a的一端与栅极焊盘30相连而另一端延伸到半导体元件3的Y方向负侧的端部。利用第1引线部31a将半导体元件3的上表面中央在X方向上分割为两部分。
第2引线部31b以与第1引线部31a交叉的方式自半导体元件3的X方向的一端部延伸到另一端部。沿Y方向排列配置有两个第2引线部31b。利用两个第2引线部31b将半导体元件3的上表面在Y方向上分割为三部分。即,利用格栅状的栅极通路将半导体元件3的上表面(镀层33)分割为六部分。
另外,在被划分成六个的镀层33的外周形成有矩形框状的保护环35。保护环35与第1引线部31a的两端和第2引线部31b的两端相连。
分别在被划分成六个的镀层33的各上表面配置有第1突起部45。即,第1突起部45设于不与栅极通路重叠的位置。此外,并不限定于针对一个镀层33配置一个第1突起部45的情况,也可以在一个镀层33配置多个第1突起部45。第1突起部45在X方向上设于与保护环35分开距离X1、与栅极通路31a分开距离X2的位置。另外,在Y方向上,第1突起部45设于与栅极通路31b分开距离Y1、与保护环35分开距离Y2的位置。栅极通路31a、31b与第1突起部45之间的距离(X2、Y1)俯视时为0.4mm以上。
如图6所示,另一变形例的栅极通路形成为俯视呈字母T形。具体而言,栅极通路由沿Y方向延伸的第1引线部31a和沿X方向延伸的第2引线部31b构成。第1引线部31a的一端与栅极焊盘30相连而另一端与第2引线部31b的中央相连。第2引线部31b自半导体元件3的X方向的一端部延伸到另一端部。利用字母T形的栅极通路,将半导体元件3的上表面(镀层)分割成三部分。
为了方便说明,将被划分成三个的区域中靠Y方向负侧的两个区域设为镀层33a,将靠Y方向正侧的一个区域设为镀层33b。两个镀层33a由第1引线部31a划分开。另外,镀层33b的X方向的宽度对应于两个镀层33a的宽度量。
另外,在被划分成三个的镀层33a、33b的外周形成有矩形框状的保护环35。保护环35与第1引线部31a的一端和第2引线部31b的两端相连。
在被划分成三个的镀层33a、33b的各上表面分别配置有第1突起部45。具体而言,针对一个镀层33a配置有一个第1突起部45,在镀层33b沿X方向排列地配置有两个第1突起部。即,第1突起部45设于不与栅极通路重叠的位置。第1突起部45在X方向上设于与保护环35分开距离X1、与栅极通路31a分开距离X2的位置。另外,在Y方向上,第1突起部45设于与栅极通路31b分开距离Y1、与保护环35分开距离Y2的位置。栅极通路31a、31b与第1突起部45之间的距离(X2、Y1)俯视时为0.4mm以上。如此,在图5和图6所示的结构中,也能够得到与上述实施方式相同的作用效果。如此,在图3、图5、图6所示的例子中,栅极通路31、31a、31b与第1突起部45分开0.4mm以上。而且,保护环35与第1突起部45之间的距离也可以为0.4mm以上。若第1突起部45与保护环35分开0.4mm以上,则可以使第1突起部45对上表面电极32造成的影响减小。而且,第1突起部45以距第1接合部40的外缘部的距离L在0.4mm以上且2.0mm以下的范围的方式设于第1接合部40的内侧,更优选以该距离L在0.8mm以上且1.3mm以下的范围的方式设于第1接合部40的内侧。利用这样的第1突起部45的配置,能够减小金属布线板4的意外倾斜。此外,在自第1接合部40的外缘到第1突起部45的距离未分开一定程度的情况下,应力集中在接合材料S3的外缘部、特别是集中在接合材料S3的圆角部,容易产生裂纹。另外,若自第1接合部40的外缘到第1突起部45的距离过大,则金属布线板4的意外倾斜存在变大的风险。
另外,在上述实施方式中,说明了金属布线板4自第1接合部40到第2接合部41形成为相同的宽度,且俯视时第1接合部40、第2接合部41以及连结部42沿着X方向排成一列地配置的情况,但并不限定于该结构。例如,也可以是图7所示的结构。图7是变形例的金属布线板的俯视图。在图7中,也主要对不同点进行说明,对共通的结构标注相同的附图标记并适当省略说明。
如图7所示,在变形例的金属布线板4中,第1接合部40和第2接合部41以俯视时隔着连结部42倾斜地相对的方式配置。具体而言,连结部42具有俯视时在Y方向上较长的矩形形状。另外,在连结部42形成有沿厚度方向贯穿的两个贯通孔42a。两个贯通孔42a沿Y方向排列配置。贯通孔42a也可以是一个,还可以没有贯通孔42a。
第1接合部40相对于连结部42而言偏向Y方向负侧地配置。在第1接合部40的X方向正侧的端部形成有以大致直角弯曲地向上方立起的第1弯曲部43。第1弯曲部43的Y方向的宽度小于第1接合部40的Y方向的宽度。另外,在第1接合部40形成有将其与第1弯曲部43相连的外缘的一部分切去并向X方向负侧延伸而成的缺口部40a。
缺口部40a作为用于得到第1弯曲部43的弯曲形状的避让部发挥功能。缺口部40a位于比连结部42的Y方向负侧的端部靠Y方向负侧(外侧)的位置。第1弯曲部43连结于连结部42的X方向负侧且是Y方向负侧的端部。即,第1弯曲部43的Y方向的宽度小于连结部42的Y方向的宽度。
在第1接合部40的下表面形成有四个第1突起部45。四个第1突起部45偏向第1接合部40的外周侧地配置。即,在第1接合部40的四角配置有第1突起部45。四个第1突起部45中的靠Y方向负侧的两个第1突起部45配置于比缺口部40a靠Y方向负侧(外侧)的位置。
第2接合部41相对于连结部42而言偏向Y方向正侧地配置。在第2接合部41的X方向负侧的端部形成有第2弯曲部44,该第2弯曲部44以大致直角弯曲地向上方立起。第2弯曲部44的Y方向的宽度小于第2接合部41的Y方向的宽度。另外,在第2接合部41形成有将其与第2弯曲部44相连的外缘的一部分切去并向X方向正侧延伸而成的缺口部41a。
缺口部41a作为用于得到第2弯曲部44的弯曲形状的避让部发挥功能。缺口部41a位于比连结部42的Y方向正侧的端部靠Y方向正侧(外侧)的位置。第2弯曲部44连结于连结部42的X方向正侧且是Y方向正侧的端部。即,第2弯曲部44的Y方向的宽度小于连结部42的Y方向的宽度。
在第2接合部41的下表面形成有两个第2突起部46。两个第2突起部46沿着Y方向排列配置。两个第2突起部46中的位于Y方向正侧的位置的第2突起部46配置于比缺口部41a靠Y方向正侧(外侧)的位置。在图7所示的结构中,也能够得到与上述实施方式相同的作用效果。此外,在图7中,位于缺口部40a的外侧的第1突起部45不需要全部都位于缺口部40a的外侧,只要一部分位于缺口部40a的外侧即可。位于缺口部41a的外侧的第2突起部46也相同。Y方向负侧的两个第1突起部45可以设为俯视时比缺口部40a远离连结部42,Y方向正侧的第2突起部46可以设为俯视时比缺口部41a远离连结部42。另外,第1接合部40、连结部42以及第2接合部41可以作为整体而配置为其外缘成为锯齿状或字母W字形。
另外,在上述实施方式中,说明了第1突起部45具有圆柱形状的情况。该情况下,第1突起部45在俯视时与栅极通路31相对的面具有曲面。例如,在相对的面为平面的情况下,在被第1突起部45和栅极通路31夹在中间的部分,无法缓和应力,应力在该部分集中,可能导致破损。如上所述,由于与栅极通路31相对的面为曲面,因而能够使第1突起部45与栅极通路31之间的应力缓和,并且还能够防止局部应力的产生。
此外,第1突起部45并不限定于圆柱形状,也可以是图8所示的棱柱形状。该情况下,优选在第1突起部45的角部形成有圆角部45a。圆角部45a在俯视时与栅极通路31相对的面具有曲面。在这样的情况下,也能够获得与上述相同的效果。
另外,优选的是,并不限定于俯视,如图9所示,在剖视时第1突起部45也在顶端具有曲面。具体而言,在第1突起部45的下端的角部形成有圆角45b。在剖视时,第1突起部45具有曲面,因而也能够进一步获得应力缓和效果。
另外,在上述实施方式中,半导体元件3的个数和配置部位并不限定于上述结构,能够适当变更。
另外,在上述实施方式中,电路板的个数和布局并不限定于上述结构,能够适当变更。
另外,在上述实施方式中,设为层叠基板2、半导体元件3形成为俯视矩形形状或方形形状的结构,但并不限定于该结构。层叠基板2、半导体元件3也可以形成为上述以外的多边形形状。
另外,在上述实施方式中,说明了接合材料S1~S4由焊料构成的情况,但并不限定于该结构。接合材料例如也可以由烧结材料构成。
另外,在上述实施方式中,说明了由与X方向平行的规定距离X2表示边界部34与第1突起部45之间的距离的情况,但并不限定于该结构。也可以是,表示规定距离X2的起点根据第1突起部45的形状而变化,例如,将边界部34与第1突起部45的外缘之间的最短距离设为规定距离X2。该情况下,不需要用与X方向平行的朝向来限定规定距离X2。
另外,说明了本实施方式以及变形例,但是作为其他实施方式,也可以将上述实施方式以及变形例整体地或者部分地组合。
另外,本实施方式不限定于上述的实施方式以及变形例,也可以在不脱离技术思想的主旨的范围内进行各种变更、替换、变形。另外,若利用技术的进步或者派生出的其他技术而能够将技术思想以其他方式实现,则也可以使用该方法来实施。因此,权利要求书涵盖能够包含于技术思想的范围内的全部的实施方式。
下面整理上述实施方式中的特征点。
上述实施方式中记载的半导体模块包括:半导体元件,其在上表面以沿规定方向延伸的方式形成有栅极通路;以及金属布线板,其配置于所述半导体元件的上表面,所述金属布线板具有第1接合部,该第1接合部经由第1接合材料接合于所述半导体元件的上表面,所述第1接合部具有朝向所述半导体元件突出的多个第1突起部,所述第1突起部设于俯视时与所述栅极通路分开规定距离的位置。
另外,在上述的半导体模块中,多个所述第1突起部的面积为所述第1接合部的面积的0.5%以上且25%以下。
另外,在上述的半导体模块中,所述第1突起部设于与所述第1接合部的外缘部分开规定距离以上的位置。
另外,在上述的半导体模块中,所述第1突起部在俯视时与所述栅极通路相对的面具有曲面。
另外,在上述的半导体模块中,所述第1突起部剖视时在顶端具有曲面。
另外,在上述的半导体模块中,所述第1突起部为圆柱、截头圆锥、或半球形状。
另外,在上述的半导体模块中,多个所述第1突起部以俯视时沿着所述第1接合部的外周缘且隔着所述栅极通路的方式配置。
另外,在上述的半导体模块中,多个所述第1突起部俯视时沿着所述栅极通路的延伸方向排列配置。
另外,在上述的半导体模块中,所述第1突起部俯视时与所述栅极通路分开0.4mm以上。
另外,在上述的半导体模块中,所述第1突起部设于距所述第1接合部的外缘部0.4mm以上且2.0mm以下的内侧的范围内。
另外,在上述的半导体模块中,所述第1突起部的突出高度为50μm以上且300μm以下。
另外,在上述的半导体模块中,所述第1突起部具有圆柱形状或截头圆锥形状,外径为0.4mm以上且1.5mm以下。
另外,在上述的半导体模块中,所述半导体元件具有:上表面电极,其设于所述半导体元件的上表面;以及镀层,其设于所述上表面电极的上表面,所述栅极通路以贯穿所述镀层的方式形成于所述上表面电极的上表面,所述第1突起部与所述栅极通路、所述上表面电极以及所述镀层所集中的边界部分开规定距离。
另外,在上述的半导体模块中,所述栅极通路以将所述半导体元件的上表面分割为多个的方式延伸,分别在所述半导体元件的由所述栅极通路划分出的各上表面配置有多个所述第1突起部。
另外,在上述的半导体模块中,在所述半导体元件的上表面形成为格栅状,分别在所述半导体元件的由格栅状的所述栅极通路划分出的各上表面各配置有一个所述第1突起部,在所述半导体元件的被划分出的各上表面,所述第1突起部的面积为所述第1接合部的面积的0.5%以上且25%以下。
另外,在上述的半导体模块中,所述半导体元件为矩形形状,在一边的中央具备栅极焊盘,在所述半导体元件的上表面,所述栅极通路以自所述栅极焊盘沿与所述一边垂直的方向延伸而在所述一边与所述另一边中间的位置停止并自此处沿与所述一边平行的方向延伸的形式,整体形成为字母T形,分别在所述半导体元件的上表面的由字母T形的所述栅极通路划分出的区域各配置有一个所述第1突起部,在所述另一边侧的一个区域配置有多个所述第1突起部。
另外,在上述的半导体模块中,该半导体模块还具备层叠基板,该层叠基板在绝缘板的上表面配置有第1电路板和第2电路板,所述半导体元件配置于所述第1电路板上,所述金属布线板具有:第2接合部,其经由第2接合材料接合于所述第2电路板上;以及连结部,其连结所述第1接合部和所述第2接合部,所述第2接合部具有朝向所述第2电路板突出的至少一个第2突起部。
另外,在上述的半导体模块中,所述第1接合部、所述第2接合部以及所述连结部俯视时排成一列地配置。
另外,在上述的半导体模块中,所述第1接合部和所述第2接合部以俯视时隔着所述连结部倾斜地相对的方式配置。
另外,在上述的半导体模块中,该半导体模块还具有第1弯曲部,该第1弯曲部自所述第1接合部的端部朝向所述连结部弯曲,连结所述第1接合部和所述连结部,所述第1弯曲部的宽度小于所述第1接合部的宽度,所述第1突起部的至少一部分配置于与第1弯曲部相连的端部的内侧,至少一部分配置于与第1弯曲部相连的端部的外侧。
另外,在上述的半导体模块中,该半导体模块还具有第2弯曲部,该第2弯曲部自所述第2接合部的端部朝向所述连结部弯曲,连结所述第2接合部和所述连结部,所述第2弯曲部的宽度小于所述第2接合部的宽度,所述第2突起部的至少一部分配置于与第2弯曲部相连的端部的内侧,至少一部分配置于与第2弯曲部相连的端部的外侧。
另外,在上述的半导体模块中,所述第1接合部具有将其与所述第1弯曲部相连的外缘的一部分切去而成的缺口部。
另外,在上述的半导体模块中,所述半导体元件还具有设于所述镀层的周围的保护环,所述第1突起部与所述保护环分开规定距离。
产业上的可利用性
如以上说明那样,本发明具有能够确保焊料的厚度并且抑制芯片与引线框之间的应力集中的效果,特别对于半导体模块是有用的。
本申请基于2019年10月15日申请的日本特愿2019-188628。其内容全部包含在本说明书中。
Claims (24)
1.一种半导体模块,其中,
该半导体模块包括:
半导体元件,其在上表面以沿规定方向延伸的方式形成有栅极通路;以及
金属布线板,其配置于所述半导体元件的上表面,
所述金属布线板具有第1接合部,该第1接合部经由第1接合材料接合于所述半导体元件的上表面,
所述第1接合部具有朝向所述半导体元件突出的多个第1突起部,
所述第1突起部设于俯视时与所述栅极通路分开规定距离的位置。
2.根据权利要求1所述的半导体模块,其中,
多个所述第1突起部的面积为所述第1接合部的面积的0.5%以上且25%以下。
3.根据权利要求1或2所述的半导体模块,其中,
所述第1突起部设于与所述第1接合部的外缘部分开规定距离以上的位置。
4.根据权利要求1~3中任一项所述的半导体模块,其中,
所述第1突起部在俯视时与所述栅极通路相对的面具有曲面。
5.根据权利要求1~4中任一项所述的半导体模块,其中,
所述第1突起部剖视时在顶端具有曲面。
6.根据权利要求1~5中任一项所述的半导体模块,其中,
所述第1突起部为圆柱、截头圆锥、或半球形状。
7.根据权利要求1~6中任一项所述的半导体模块,其中,
多个所述第1突起部以俯视时沿着所述第1接合部的外周缘且隔着所述栅极通路的方式配置。
8.根据权利要求1~7中任一项所述的半导体模块,其中,
多个所述第1突起部俯视时沿着所述栅极通路的延伸方向排列配置。
9.根据权利要求1~8中任一项所述的半导体模块,其中,
所述第1突起部俯视时与所述栅极通路分开0.4mm以上。
10.根据权利要求1~9中任一项所述的半导体模块,其中,
所述第1突起部设于距所述第1接合部的外缘部0.4mm以上且2.0mm以下的内侧的范围内。
11.根据权利要求1~10中任一项所述的半导体模块,其中,
所述第1突起部的突出高度为50μm以上且300μm以下。
12.根据权利要求1~11中任一项所述的半导体模块,其中,
所述第1突起部具有圆柱形状或截头圆锥形状,外径为0.4mm以上且1.5mm以下。
13.根据权利要求1~12中任一项所述的半导体模块,其中,
所述半导体元件具有:
上表面电极,其设于所述半导体元件的上表面;以及
镀层,其设于所述上表面电极的上表面,
所述栅极通路以贯穿所述镀层的方式形成于所述上表面电极的上表面,
所述第1突起部与所述栅极通路、所述上表面电极以及所述镀层所集中的边界部分开规定距离。
14.根据权利要求13所述的半导体模块,其中,
所述半导体元件为矩形形状,在一边的中央具备栅极焊盘,
所述栅极通路在所述半导体元件的上表面自所述栅极焊盘沿与所述一边垂直的方向自所述一边延伸到所述另一边,
所述第1突起部以所述栅极通路为中心而线对称地配置。
15.根据权利要求13或14所述的半导体模块,其中,
所述栅极通路以将所述半导体元件的上表面分割为多个的方式延伸,分别在所述半导体元件的由所述栅极通路划分出的各上表面配置有多个所述第1突起部。
16.根据权利要求15所述的半导体模块,其中,
所述栅极通路在所述半导体元件的上表面形成为格栅状,
分别在所述半导体元件的由格栅状的所述栅极通路划分出的各上表面各配置有一个所述第1突起部,在所述半导体元件的被划分出的各上表面,所述第1突起部的面积为所述第1接合部的面积的0.5%以上且25%以下。
17.根据权利要求15所述的半导体模块,其中,
所述半导体元件为矩形形状,在一边的中央具备栅极焊盘,
在所述半导体元件的上表面,所述栅极通路以自所述栅极焊盘沿与所述一边垂直的方向延伸而在所述一边与所述另一边中间的位置停止并自此处沿与所述一边平行的方向延伸的形式,整体形成为字母T形,
分别在所述半导体元件的上表面的由字母T形的所述栅极通路划分出的所述一边侧的两个区域各配置有一个所述第1突起部,在所述另一边侧的一个区域配置有多个所述第1突起部。
18.根据权利要求1~17中任一项所述的半导体模块,其中,
该半导体模块还具备层叠基板,该层叠基板在绝缘板的上表面配置有第1电路板和第2电路板,
所述半导体元件配置于所述第1电路板上,
所述金属布线板具有:第2接合部,其经由第2接合材料接合于所述第2电路板上;以及连结部,其连结所述第1接合部和所述第2接合部,
所述第2接合部具有朝向所述第2电路板突出的至少一个第2突起部。
19.根据权利要求18所述的半导体模块,其中,
所述第1接合部、所述第2接合部以及所述连结部俯视时排成一列地配置。
20.根据权利要求18所述的半导体模块,其中,
所述第1接合部和所述第2接合部以俯视时隔着所述连结部倾斜地相对的方式配置。
21.根据权利要求18~20中任一项所述的半导体模块,其中,
该半导体模块还具有第1弯曲部,该第1弯曲部自所述第1接合部的端部朝向所述连结部弯曲,连结所述第1接合部和所述连结部,
所述第1弯曲部的宽度小于所述第1接合部的宽度,
所述第1突起部的至少一部分配置于与第1弯曲部相连的端部的内侧,至少一部分配置于与第1弯曲部相连的端部的外侧。
22.根据权利要求21所述的半导体模块,其中,
该半导体模块还具有第2弯曲部,该第2弯曲部自所述第2接合部的端部朝向所述连结部弯曲,连结所述第2接合部和所述连结部,
所述第2弯曲部的宽度小于所述第2接合部的宽度,
所述第2突起部的至少一部分配置于与第2弯曲部相连的端部的内侧,至少一部分配置于与第2弯曲部相连的端部的外侧。
23.根据权利要求21或22所述的半导体模块,其中,
所述第1接合部具有将其与所述第1弯曲部相连的外缘的一部分切去而成的缺口部。
24.根据权利要求1~23中任一项所述的半导体模块,其中,
所述半导体元件还具有设于所述镀层的周围的保护环,
所述第1突起部俯视时与所述保护环分开规定距离。
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