JP2014236056A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2014236056A JP2014236056A JP2013115580A JP2013115580A JP2014236056A JP 2014236056 A JP2014236056 A JP 2014236056A JP 2013115580 A JP2013115580 A JP 2013115580A JP 2013115580 A JP2013115580 A JP 2013115580A JP 2014236056 A JP2014236056 A JP 2014236056A
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Abstract
【解決手段】半導体装置PKGは、貫通孔SHを有する絶縁性の基材BSと、基材BSの下面BSbに形成された端子TEと、基材の上面BSa上にフェイスアップで搭載された半導体チップCPとを有している。更に、基材BSの貫通孔SHから露出する端子TEの露出面EXと半導体チップCPのパッドPDとを電気的に接続するワイヤBWなどの導電性部材と、その導電性部材、基材BSの貫通孔SHの内部、および半導体チップCPを封止する封止体MRを有している。基材BSの貫通孔SHから露出する端子TEの露出面EXは、ワイヤBWなどの導電性部材が接合される接合部以外の領域に、アンカー手段が設けられている。
【選択図】図4
Description
<半導体装置の構造について>
図1〜図3は、本実施の形態の半導体装置PKGの平面図であり、図4は、半導体装置のPKGの断面図であり、図5は、半導体装置のPKGの部分拡大断面図であり、図6は、半導体装置のPKGの部分拡大平面図であり、図7は、半導体装置のPKGの部分拡大断面図である。
次に、上記半導体装置PKGを組み込んだIC(Integrated Circuit)カードについて説明する。
次に、本実施の形態の半導体装置PKGの製造工程について説明する。
次に、本実施の形態のICカード1の製造工程について説明する。図45〜図48は、ICカード1の製造工程を示す断面図である。
次に、本発明者の検討について説明する。
本実施の形態の半導体装置PKGは、貫通孔SHを有する絶縁性の基材BSと、基材BSの一方の主面(下面BSb)に形成され、一部が貫通孔SHから露出される端子TE(外部端子)と、基材BSの他方の主面(上面BSa)上に搭載された半導体チップCPとを有している。半導体チップCPは、パッドPDが形成された側とは反対側の裏面CPbが、基材BSの他方の主面(上面BSa)と対向するように、基材BSの他方の主面(上面BSa)上に搭載されている。更に、半導体装置PKGは、端子TEのうちの基材BSの貫通孔SHから露出する露出面EXと半導体チップCPのパッドPDとを電気的に接続する導電性部材(すなわち導電性接続部材、ここではワイヤBW)と、封止体MRとを有しており、封止体MRは、基材BSの貫通孔SHの内部、半導体チップCP、および導電性接続部材(ワイヤBW)を封止している。そして、基材BSの貫通孔SHから露出する端子TEの露出面EXのうち、導電性接続部材(ワイヤBW)が接合される接合部(ボンディング領域)以外の領域(非接合部)に、アンカー手段が設けられている。
次に、本実施の形態1の第1変形例について説明する。
次に、本実施の形態1の第2変形例について説明する。
図54および図55は、本実施の形態2の半導体装置の説明図であり、図54は上記実施の形態1の上記図6に対応するものである。すなわち、図54は、基材BSの貫通孔SHから露出する端子TEの露出面EXとそこに接続されたワイヤBWを示す平面図である。図55は、図54と同じ領域の平面図に対応しているが、図55には、ワイヤBWを端子TEの露出面EXに接続する直前の段階が示されている。
図61および図62は、本実施の形態3の半導体装置の説明図であり、図61は上記実施の形態1の上記6に対応するものである。すなわち、図61は、基材BSの貫通孔SHから露出する端子TEの露出面EXとそこに接続されたワイヤBWを示す平面図である。図62は、図61と同じ領域の平面図に対応しているが、図62には、ワイヤBWを端子TEの露出面EXに接続する直前の段階が示されている。なお、図61および図62は平面図であるが、端子TEの露出面EXにおける領域71と領域72とを判別しやすいように、領域71と領域72とに互いに異なる向きのハッチングを付してある。
上記実施の形態1〜3では、基材BSの下面BSbには端子TEが形成されているが、基材BSの上面BSaには、金属パターン(端子または配線など)が形成されていない基板CBを用いていた。上記実施の形態1〜3(変形例を含む)において、基材BSの下面BSbに端子TEが形成され、基材BSのチップ搭載側の主面である上面BSaにも、金属パターン(端子または配線など)が形成された、所謂、デュアル基板を基板CBとしても用いることもできる。
(項1)以下の工程を含む、半導体装置の製造方法:
(a)第1面および前記第1面とは反対側の第2面を有する絶縁性の基材と、前記基材の前記第2面に形成された外部端子と、前記外部端子の一部を露出するように、前記基材の前記第1面および前記第2面のうちの一方から他方に向かって形成された貫通孔と、を含む基板を準備する工程、
(b)主面、前記主面に形成されたパッド、および前記主面とは反対側の裏面を有する半導体チップを、前記裏面が前記基材の前記第1面と対向するように、前記基材の前記第1面上に搭載する工程、
(c)前記外部端子のうちの前記基材の前記貫通孔から露出する露出面と、前記半導体チップの前記パッドとを、導電性部材を介して電気的に接続する工程と、
(d)前記基材の前記貫通孔の内部、前記半導体チップ、および前記導電性部材を封止する封止体を形成する工程、
ここで、前記露出面のうち、前記導電性部材が接合される接合部以外の領域に、アンカー手段が設けられている。
2 カード本体
2a 表面
2b 裏面
3,3a,3b 凹部(窪み部)
3c,3d 底面
3e,3f 側壁
4 接着材(接着層、接着シート)
4a 接着用フィルム(接着用テープ、接着シート)
5,5a 中空空間
10 基板
10a 上面(チップ搭載面)
10b 下面(端子面、端子形成面)
11 基材(基材層、基板、ベースフィルム、テープ基材)
11a,11b 主面
12 接着材層
13 銅箔(銅層)
13a,13b 主面
14 フォトレジスト層(フォトレジスト膜)
15,15a マスク
16,17,17c めっき膜
17a ニッケルめっき膜
17b 金めっき膜
18 銅箔
19 フォトレジスト層(フォトレジスト膜)
20a デバイス領域
20b 枠部(フレーム部)
20c スプロケットホール(送り孔、貫通孔)
25 キャピラリ
25a クランパ
26 ワイヤ
26a ボール部(ボール状の電極)
30 成形金型
31 上金型(金型)
31a 下面(金型面)
31b キャビティ
32 下金型(金型)
32a 上面(金型面)
51 領域
71,72 領域
73 マスク層
81,81a 凹部(窪み部)
91,91a 金属パターン
91b 端子
BD 接合面(面)
BL ボール部(ボール状の電極)
BP スタッドバンプ(バンプ電極)
BS 基材(基材層、ベースフィルム、基板)
BSa 上面(チップ搭載面)
BSb 下面(端子面、端子形成面)
BW ワイヤ
CB 基板
CBa 上面
CBb 下面
CL 中心線
CLK クロック端子
CN1,CN2,CN3,CN4 コーナ部
CP 半導体チップ
CPa 表面(主面)
CPb 裏面
CT 中心
DB 接合材(ダイボンド材、接着材、接着層)
EX 露出面(露出部、表面、ボンディング面)
GND 基準電位端子
I/O データ端子
L1,L2 距離
L3,L4 寸法
MR 封止体(封止樹脂、封止部、封止樹脂部)
NC1,NC2,NC3 予備端子
PD パッド(ボンディングパッド、パッド電極、電極パッド、端子)
PD1 めっき膜
PKG 半導体装置
PV パッシベーション膜
RG1,RG2,RG3,RG4 領域
RST リセット端子
SB スタッドバンプ(バンプ電極)
SD1,SD2,SD3,SD4 辺
SE 接着層(接着材層)
SH 貫通孔(開口部、ボンディングホール、接続用孔、スルーホール)
TE 端子(電極、外部端子、金属パターン)
TE1 銅層
TE1a 上面
TE1b 下面
TE2,TE3 めっき層(めっき膜)
TE21,TE31 ニッケル層(ニッケルめっき層)
TE22,TE32 金層(金めっき層)
TEa 基材対向面(上面)
TEb 端子面(下面)
TL1 加熱ツール(加熱用治具)
TL2 ツール(治具)
VCC 電源電位端子
YG 矢印
Claims (18)
- 第1面と、前記第1面とは反対側の第2面と、前記第1面および前記第2面のうちの一方から他方に向かって形成された貫通孔と、を有する絶縁性の基材と、
前記基材の前記第2面に形成された外部端子と、
主面、前記主面に形成されたパッド、および前記主面とは反対側の裏面を有し、前記裏面が前記基材の前記第1面と対向するように、前記基材の前記第1面上に搭載された半導体チップと、
前記外部端子のうちの前記基材の前記貫通孔から露出する露出面と、前記半導体チップの前記パッドとを、電気的に接続する導電性部材と、
前記基材の前記貫通孔の内部、前記半導体チップ、および前記導電性部材を封止する封止体と、
を含み、
前記露出面のうち、前記導電性部材が接合される接合部以外の領域に、アンカー手段が設けられている、半導体装置。 - 請求項1記載の半導体装置において、
前記アンカー手段は、前記露出面に形成されたスタッドバンプである、半導体装置。 - 請求項2記載の半導体装置において、
前記露出面の複数箇所にそれぞれ前記スタッドバンプが形成されている、半導体装置。 - 請求項2記載の半導体装置において、
前記スタッドバンプの高さ方向に見たときに、前記スタッドバンプの一部の直下に前記封止体の一部が存在している、半導体装置。 - 請求項2記載の半導体装置において、
前記露出面に、複数の前記スタッドバンプが積み重ねられている、半導体装置。 - 請求項2記載の半導体装置において、
前記露出面における、前記接合部と前記貫通孔の内壁との間の距離よりも、前記スタッドバンプと前記貫通孔の内壁との間の距離の方が小さい、半導体装置。 - 請求項2記載の半導体装置において、
前記導電性部材はワイヤである、半導体装置。 - 請求項7記載の半導体装置において、
前記ワイヤと前記スタッドバンプは、同じ材料により形成されている、半導体装置。 - 請求項1記載の半導体装置において、
前記露出面において、前記接合部は、前記露出面の中心とは重ならない位置にある、半導体装置。 - 請求項1記載の半導体装置において、
前記露出面において、前記接合部の位置は、前記露出面の中心から第1の方向にずれており、
前記第1の方向は、平面視において、前記半導体装置の中心から遠ざかる方向である、半導体装置。 - 請求項1記載の半導体装置において、
前記アンカー手段は、前記露出面に形成された凹部である、半導体装置。 - 請求項1記載の半導体装置において、
前記アンカー手段は、前記露出面に形成された凸部である、半導体装置。 - 請求項1記載の半導体装置において、
前記アンカー手段は、前記露出面における粗面化された領域である、半導体装置。 - 請求項13記載の半導体装置において、
前記露出面は、前記粗面化された領域と、前記粗面化された領域よりも表面粗さが小さい領域とを有し、
前記表面粗さが小さい領域に前記接合部がある、半導体装置。 - 請求項14記載の半導体装置において、
前記粗面化された領域は、前記露出面の周縁部にあり、
前記表面粗さが小さい領域は、前記露出面において、前記粗面化された領域の内側にある、半導体装置。 - 請求項1記載の半導体装置において、
前記外部端子は、前記基材の前記第2面と対向する側の基材対向面と、前記外部端子の前記基材対向面とは反対側の端子面と、を有し、
前記外部端子の前記基材対向面は、前記基材の前記第2面と対向する接合面と、前記基材の前記貫通孔から露出する前記露出面と、を有している、半導体装置。 - 請求項16記載の半導体装置において、
前記接合面の表面粗さは、前記露出面のうち、前記導電性部材が接合される前記接合部の表面粗さよりも大きい、半導体装置。 - 第1面と、前記第1面とは反対側の第2面と、前記第1面および前記第2面のうちの一方から他方に向かって形成された貫通孔と、を有する絶縁性の基材と、
前記基材の前記第2面に形成された外部端子と、
主面、前記主面に形成されたパッド、および前記主面とは反対側の裏面を有し、前記裏面が前記基材の前記第1面と対向するように、前記基材の前記第1面上に搭載された半導体チップと、
前記外部端子のうちの前記基材の前記貫通孔から露出する露出面と、前記半導体チップの前記パッドとを、電気的に接続する導電性部材と、
前記基材の前記貫通孔の内部、前記半導体チップ、および前記導電性部材を封止する封止体と、
を含み、
前記露出面は、第1領域と、前記第1領域よりも表面粗さが大きい第2領域とを有し、
前記導電性部材は、前記第1領域に接合されている、半導体装置。
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CN201410200904.9A CN104218017B (zh) | 2013-05-31 | 2014-05-13 | 半导体装置 |
CN201420243438.8U CN203983265U (zh) | 2013-05-31 | 2014-05-13 | 半导体装置 |
US14/278,300 US9337134B2 (en) | 2013-05-31 | 2014-05-15 | Semiconductor device |
KR20140063244A KR20140141474A (ko) | 2013-05-31 | 2014-05-26 | 반도체 장치 |
EP20140169979 EP2816590A3 (en) | 2013-05-31 | 2014-05-27 | Semiconductor device with anchor means for the sealing resin |
HK15101659.3A HK1201376A1 (en) | 2013-05-31 | 2015-02-13 | Semiconductor device |
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CN107025481B (zh) * | 2016-02-02 | 2021-08-20 | 上海伯乐电子有限公司 | 柔性印制电路板及应用其的智能卡模块和智能卡 |
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CN104218017A (zh) | 2014-12-17 |
EP2816590A2 (en) | 2014-12-24 |
TWI611535B (zh) | 2018-01-11 |
US9337134B2 (en) | 2016-05-10 |
US20140353822A1 (en) | 2014-12-04 |
TW201445690A (zh) | 2014-12-01 |
CN104218017B (zh) | 2018-12-18 |
EP2816590A3 (en) | 2015-04-08 |
CN203983265U (zh) | 2014-12-03 |
US20160293564A1 (en) | 2016-10-06 |
US9583455B2 (en) | 2017-02-28 |
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JP6125332B2 (ja) | 2017-05-10 |
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