JP2014154800A - 配線基板及びその製造方法 - Google Patents

配線基板及びその製造方法 Download PDF

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Publication number
JP2014154800A
JP2014154800A JP2013025210A JP2013025210A JP2014154800A JP 2014154800 A JP2014154800 A JP 2014154800A JP 2013025210 A JP2013025210 A JP 2013025210A JP 2013025210 A JP2013025210 A JP 2013025210A JP 2014154800 A JP2014154800 A JP 2014154800A
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Japan
Prior art keywords
layer
wiring
insulating layer
via hole
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2013025210A
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English (en)
Japanese (ja)
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JP2014154800A5 (enExample
Inventor
Noriyoshi Shimizu
規良 清水
Wataru Kaneda
渉 金田
Akio Mutsukawa
昭雄 六川
Toshinori Koyama
利徳 小山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2013025210A priority Critical patent/JP2014154800A/ja
Priority to US14/141,765 priority patent/US9455219B2/en
Publication of JP2014154800A publication Critical patent/JP2014154800A/ja
Publication of JP2014154800A5 publication Critical patent/JP2014154800A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32227—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32235—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2013025210A 2013-02-13 2013-02-13 配線基板及びその製造方法 Pending JP2014154800A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2013025210A JP2014154800A (ja) 2013-02-13 2013-02-13 配線基板及びその製造方法
US14/141,765 US9455219B2 (en) 2013-02-13 2013-12-27 Wiring substrate and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013025210A JP2014154800A (ja) 2013-02-13 2013-02-13 配線基板及びその製造方法

Publications (2)

Publication Number Publication Date
JP2014154800A true JP2014154800A (ja) 2014-08-25
JP2014154800A5 JP2014154800A5 (enExample) 2016-01-28

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Country Status (2)

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US (1) US9455219B2 (enExample)
JP (1) JP2014154800A (enExample)

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016127248A (ja) * 2015-01-08 2016-07-11 日本特殊陶業株式会社 多層配線基板
JP2017050310A (ja) * 2015-08-31 2017-03-09 新光電気工業株式会社 電子部品装置及びその製造方法
WO2017043375A1 (ja) * 2015-09-08 2017-03-16 東レ株式会社 感光性樹脂組成物、感光性シート、半導体装置および半導体装置の製造方法
WO2017073481A1 (ja) * 2015-10-28 2017-05-04 東レ株式会社 ポジ型感光性樹脂組成物、感光性シート、硬化膜、層間絶縁膜、半導体保護膜、半導体装置の製造方法、半導体電子部品および半導体装置
WO2017170032A1 (ja) * 2016-03-28 2017-10-05 東レ株式会社 感光性フィルム
KR20190011125A (ko) * 2017-07-24 2019-02-01 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
CN109561569A (zh) * 2017-09-27 2019-04-02 揖斐电株式会社 印刷布线板
JP2019125709A (ja) * 2018-01-17 2019-07-25 新光電気工業株式会社 配線基板及びその製造方法と電子部品装置
KR20190093191A (ko) * 2016-12-30 2019-08-08 인텔 코포레이션 팬 아웃 스케일링을 위한 필러 및 비아 접속부를 구비한 고밀도 상호접촉 층을 가진 패키지 기판
JP2020521347A (ja) * 2017-04-21 2020-07-16 フラウンホーファー−ゲゼルシャフト・ツール・フェルデルング・デル・アンゲヴァンテン・フォルシュング・アインゲトラーゲネル・フェライン 流体の体積流量と相互作用するｍｅｍｓトランスデューサ、およびその製造方法
US10804191B2 (en) 2017-10-11 2020-10-13 Ibiden Co., Ltd. Printed wiring board
US11088081B2 (en) 2018-10-02 2021-08-10 Samsung Electronics Co., Ltd. Semiconductor package having a connection structure with tapering connection via layers
US11177205B2 (en) 2018-12-18 2021-11-16 Samsung Electronics Co., Ltd. Semiconductor package having multi-level and multi-directional shape narrowing vias
JP2022124091A (ja) * 2021-02-15 2022-08-25 凸版印刷株式会社 配線基板積層体
JP2022545091A (ja) * 2019-08-19 2022-10-25 アトテック ドイチェランド ゲーエムベーハー ウント コ カーゲー 銅で充填されたマイクロビアを含む高密度相互接続プリント回路基板の製造方法
JP2024001328A (ja) * 2019-05-31 2024-01-09 コネクトフリー株式会社 ソフトウェア開発装置およびソフトウェア開発プログラム

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US9252110B2 (en) 2014-01-17 2016-02-02 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method of forming same
JP6133227B2 (ja) * 2014-03-27 2017-05-24 新光電気工業株式会社 配線基板及びその製造方法
TWI566305B (zh) * 2014-10-29 2017-01-11 巨擘科技股份有限公司 製造三維積體電路的方法
US10504874B2 (en) * 2016-08-01 2019-12-10 Taiwan Semiconductor Manufacturing Company Limited Structures and methods for providing electrical isolation in semiconductor devices
CN112289688B (zh) * 2019-07-22 2024-05-07 盛合晶微半导体(江阴)有限公司 一种重新布线层的制备方法
KR102706158B1 (ko) 2019-08-30 2024-09-11 삼성전자주식회사 반도체 패키지 제조 방법
KR20220046134A (ko) * 2020-10-07 2022-04-14 삼성전자주식회사 반도체 패키지
US12148688B2 (en) * 2023-02-13 2024-11-19 Dyi-chung Hu Semiconductor substrate and manufacturing method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007234889A (ja) * 2006-03-01 2007-09-13 Shinko Electric Ind Co Ltd 配線の形成方法
WO2010010910A1 (ja) * 2008-07-23 2010-01-28 日本電気株式会社 コアレス配線基板、半導体装置及びそれらの製造方法
JP2010157690A (ja) * 2008-12-29 2010-07-15 Ibiden Co Ltd 電子部品実装用基板及び電子部品実装用基板の製造方法
JP2011014847A (ja) * 2009-07-06 2011-01-20 Shinko Electric Ind Co Ltd 多層配線基板
WO2011089936A1 (ja) * 2010-01-22 2011-07-28 日本電気株式会社 機能素子内蔵基板及び配線基板

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3961092B2 (ja) * 1997-06-03 2007-08-15 株式会社東芝 複合配線基板、フレキシブル基板、半導体装置、および複合配線基板の製造方法
JPH11126978A (ja) 1997-10-24 1999-05-11 Kyocera Corp 多層配線基板
KR100385042B1 (ko) * 1998-12-03 2003-06-18 인터내셔널 비지네스 머신즈 코포레이션 내 일렉트로 마이그레이션의 구조물을 도핑으로 형성하는 방법
US6375693B1 (en) * 1999-05-07 2002-04-23 International Business Machines Corporation Chemical-mechanical planarization of barriers or liners for copper metallurgy
US6573822B2 (en) * 2001-06-18 2003-06-03 Intel Corporation Tunable inductor using microelectromechanical switches
US6812576B1 (en) * 2002-05-14 2004-11-02 Applied Micro Circuits Corporation Fanned out interconnect via structure for electronic package substrates
US6818469B2 (en) * 2002-05-27 2004-11-16 Nec Corporation Thin film capacitor, method for manufacturing the same and printed circuit board incorporating the same
US7265038B2 (en) * 2003-11-25 2007-09-04 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a multi-layer seed layer for improved Cu ECP
US7834273B2 (en) * 2005-07-07 2010-11-16 Ibiden Co., Ltd. Multilayer printed wiring board
JPWO2009147936A1 (ja) * 2008-06-02 2011-10-27 イビデン株式会社 多層プリント配線板の製造方法
JP2012216773A (ja) * 2011-03-29 2012-11-08 Shinko Electric Ind Co Ltd 配線基板及びその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007234889A (ja) * 2006-03-01 2007-09-13 Shinko Electric Ind Co Ltd 配線の形成方法
WO2010010910A1 (ja) * 2008-07-23 2010-01-28 日本電気株式会社 コアレス配線基板、半導体装置及びそれらの製造方法
JP2010157690A (ja) * 2008-12-29 2010-07-15 Ibiden Co Ltd 電子部品実装用基板及び電子部品実装用基板の製造方法
JP2011014847A (ja) * 2009-07-06 2011-01-20 Shinko Electric Ind Co Ltd 多層配線基板
WO2011089936A1 (ja) * 2010-01-22 2011-07-28 日本電気株式会社 機能素子内蔵基板及び配線基板

Cited By (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016127248A (ja) * 2015-01-08 2016-07-11 日本特殊陶業株式会社 多層配線基板
JP2017050310A (ja) * 2015-08-31 2017-03-09 新光電気工業株式会社 電子部品装置及びその製造方法
WO2017043375A1 (ja) * 2015-09-08 2017-03-16 東レ株式会社 感光性樹脂組成物、感光性シート、半導体装置および半導体装置の製造方法
WO2017073481A1 (ja) * 2015-10-28 2017-05-04 東レ株式会社 ポジ型感光性樹脂組成物、感光性シート、硬化膜、層間絶縁膜、半導体保護膜、半導体装置の製造方法、半導体電子部品および半導体装置
WO2017170032A1 (ja) * 2016-03-28 2017-10-05 東レ株式会社 感光性フィルム
JPWO2017170032A1 (ja) * 2016-03-28 2019-02-07 東レ株式会社 感光性フィルム
KR102596788B1 (ko) * 2016-12-30 2023-10-31 인텔 코포레이션 팬 아웃 스케일링을 위한 필러 및 비아 접속부를 구비한 고밀도 상호접속 층을 가진 패키지 기판
KR20190093191A (ko) * 2016-12-30 2019-08-08 인텔 코포레이션 팬 아웃 스케일링을 위한 필러 및 비아 접속부를 구비한 고밀도 상호접촉 층을 가진 패키지 기판
JP2020521347A (ja) * 2017-04-21 2020-07-16 フラウンホーファー−ゲゼルシャフト・ツール・フェルデルング・デル・アンゲヴァンテン・フォルシュング・アインゲトラーゲネル・フェライン 流体の体積流量と相互作用するｍｅｍｓトランスデューサ、およびその製造方法
US11554950B2 (en) 2017-04-21 2023-01-17 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. MEMS transducer for interacting with a volume flow of a fluid, and method of producing same
KR102412613B1 (ko) * 2017-07-24 2022-06-23 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
KR20190011125A (ko) * 2017-07-24 2019-02-01 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
CN109561569B (zh) * 2017-09-27 2023-12-29 揖斐电株式会社 印刷布线板
CN109561569A (zh) * 2017-09-27 2019-04-02 揖斐电株式会社 印刷布线板
US10804191B2 (en) 2017-10-11 2020-10-13 Ibiden Co., Ltd. Printed wiring board
JP7032148B2 (ja) 2018-01-17 2022-03-08 新光電気工業株式会社 配線基板及びその製造方法と電子部品装置
JP2019125709A (ja) * 2018-01-17 2019-07-25 新光電気工業株式会社 配線基板及びその製造方法と電子部品装置
US11088081B2 (en) 2018-10-02 2021-08-10 Samsung Electronics Co., Ltd. Semiconductor package having a connection structure with tapering connection via layers
US11670518B2 (en) 2018-10-02 2023-06-06 Samsung Electronics Co., Ltd. Method of manufacturing semiconductor package having connection structure with tapering connection via layers
US11967549B2 (en) 2018-12-18 2024-04-23 Samsung Electronics Co., Ltd. Semiconductor package
US11177205B2 (en) 2018-12-18 2021-11-16 Samsung Electronics Co., Ltd. Semiconductor package having multi-level and multi-directional shape narrowing vias
JP2024001328A (ja) * 2019-05-31 2024-01-09 コネクトフリー株式会社 ソフトウェア開発装置およびソフトウェア開発プログラム
JP7630066B2 (ja) 2019-05-31 2025-02-17 久利寿 帝都 ソフトウェア開発装置およびソフトウェア開発プログラム
JP2025032310A (ja) * 2019-05-31 2025-03-11 久利寿 帝都 ソフトウェア開発装置およびソフトウェア開発プログラム
US12393409B2 (en) 2019-05-31 2025-08-19 Connectfree Corporation Software development device and software development program
JP2022545091A (ja) * 2019-08-19 2022-10-25 アトテック ドイチェランド ゲーエムベーハー ウント コ カーゲー 銅で充填されたマイクロビアを含む高密度相互接続プリント回路基板の製造方法
JP2022124091A (ja) * 2021-02-15 2022-08-25 凸版印刷株式会社 配線基板積層体
JP7676800B2 (ja) 2021-02-15 2025-05-15 Ｔｏｐｐａｎホールディングス株式会社 配線基板積層体

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