JP2012151455A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2012151455A JP2012151455A JP2011278165A JP2011278165A JP2012151455A JP 2012151455 A JP2012151455 A JP 2012151455A JP 2011278165 A JP2011278165 A JP 2011278165A JP 2011278165 A JP2011278165 A JP 2011278165A JP 2012151455 A JP2012151455 A JP 2012151455A
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- Prior art keywords
- transistor
- regions
- insulating film
- pair
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Abstract
【解決手段】第1の領域と、第1の領域の側面に接した一対の第2の領域と、一対の第2の領域の側面に接した一対の第3の領域と、を含む酸化物半導体膜と、酸化物半導体膜上に設けられたゲート絶縁膜と、ゲート絶縁膜上に第1の領域と重畳した第1の電極と、を有し、第1の領域は、CAAC酸化物半導体領域であり、一対の第2の領域及び一対の第3の領域は、ドーパントを含む非晶質な酸化物半導体領域であり、一対の第3の領域のドーパント濃度は、一対の第2の領域のドーパント濃度より高い半導体装置である。
【選択図】図1
Description
(実施の形態1)
図1(A)は、トランジスタ100の平面図である。なお、図1(A)において、下地絶縁膜102、ゲート絶縁膜111及び層間絶縁膜117は、便宜上、図示していない。
次に、トランジスタ100の作製方法について、図2及び図3を用いて説明する。
本実施の形態では、実施の形態1で示したトランジスタ100と構成が一部異なるトランジスタ200について説明する。
トランジスタ200は、トランジスタ100のゲート絶縁膜111の形状が異なったトランジスタである。
次に、トランジスタ200の作製方法について、図2及び図5を用いて説明する。
本実施の形態では、先の実施の形態で示したトランジスタと構成が一部異なるトランジスタ300について説明する。
トランジスタ300は、第2の電極219a及び第3の電極219bの一対の第3の領域209a、209bと接する面において、トランジスタ200と異なっている。
次に、トランジスタ300の作製方法について、図7を用いて説明する。
本実施の形態では、実施の形態1乃至実施の形態3に示したトランジスタにおいて、酸化物半導体膜に含まれる第1の領域、一対の第2の領域及び一対の第3の領域がトランジスタに与える電気特性の影響を、バンド図を用いて説明する。なお、図6に示すトランジスタ300を例にして説明する。
本実施の形態では、先の実施の形態で示したトランジスタと異なるトランジスタの例について図9を用いて説明する。
本実施の形態では、図10を用いて、ドーパントを添加した酸化物半導体を用いた抵抗素子について説明する。
図11(A)に半導体装置を構成する記憶素子(以下、メモリセルとも記す)の回路図の一例を示す。メモリセルは、酸化物半導体以外の材料をチャネル形成領域に用いたトランジスタ1160と酸化物半導体をチャネル形成領域に用いたトランジスタ1162によって構成される。
本実施の形態では、容量素子を有するメモリセルの回路図の一例を示す。図13(A)に示すメモリセル1170は、第1の配線SL、第2の配線BL、第3の配線S1、第4の配線S2と、第5の配線WLと、トランジスタ1171(第1のトランジスタ)と、トランジスタ1172(第2のトランジスタ)と、容量素子1173とから構成されている。トランジスタ1171は、酸化物半導体以外の材料をチャネル形成領域に用いており、トランジスタ1172はチャネル形成領域に酸化物半導体を用いている。
本実施の形態では、先の実施の形態に示すトランジスタを用いた半導体装置の例について、図14を参照して説明する。
酸化物半導体をチャネル形成領域に用いたトランジスタを少なくとも一部に用いてCPU(Central Processing Unit)を構成することができる。
101 基板
102 下地絶縁膜
103 酸化物半導体膜
105 第1の領域
107a 第2の領域
107b 第2の領域
109a 第3の領域
109b 第3の領域
111 ゲート絶縁膜
113 第1の電極
114 絶縁膜
115 サイドウォール絶縁膜
115a サイドウォール絶縁膜
115b サイドウォール絶縁膜
117 層間絶縁膜
119a 第2の電極
119b 第3の電極
116a 開口部
116b 開口部
130 酸化物半導体膜
132 酸化物半導体膜
140 酸化物半導体膜
150 ドーパント
200 トランジスタ
201 基板
202 下地絶縁膜
203 酸化物半導体膜
205 第1の領域
207a 第2の領域
207b 第2の領域
209a 第3の領域
209b 第3の領域
210 絶縁膜
211 ゲート絶縁膜
212 導電膜
213 第1の電極
215 サイドウォール絶縁膜
215a サイドウォール絶縁膜
215b サイドウォール絶縁膜
216a 開口部
216b 開口部
214 絶縁膜
217 層間絶縁膜
219a 第2の電極
219b 第3の電極
300 トランジスタ
301 基板
302 下地絶縁膜
303 酸化物半導体膜
305 第1の領域
307a 第2の領域
307b 第2の領域
309a 第3の領域
309b 第3の領域
311 ゲート絶縁膜
313 第1の電極
314 絶縁膜
315 サイドウォール絶縁膜
315a サイドウォール絶縁膜
315b サイドウォール絶縁膜
317 層間絶縁膜
319a 第2の電極
319b 第3の電極
340 酸化物半導体膜
400 トランジスタ
401 基板
402 下地絶縁膜
403 酸化物半導体膜
405 第1の領域
407a 第2の領域
407b 第2の領域
409a 第3の領域
409b 第3の領域
410a 第4の領域
410b 第4の領域
411 ゲート絶縁膜
413 第1の電極
419a 第2の電極
419b 第3の電極
420 絶縁膜
500 トランジスタ
600 抵抗素子
601 基板
602 下地絶縁膜
603 酸化物半導体膜
604a 導電膜
604b 導電膜
606 絶縁膜
610 抵抗素子
1100 メモリセル
1110 メモリセルアレイ
1111 配線駆動回路
1112 読み出し回路
1113 配線駆動回路
1120 メモリセルアレイ
1130 メモリセル
1131 トランジスタ
1132 容量素子
1140 メモリセルアレイ
1141 スイッチング素子
1142 記憶素子
1143 記憶素子群
1150 メモリセル
1151 トランジスタ
1152 トランジスタ
1153 トランジスタ
1154 トランジスタ
1155 トランジスタ
1156 トランジスタ
1160 トランジスタ
1161 トランジスタ
1162 トランジスタ
1163 トランジスタ
1164 トランジスタ
1170 メモリセル
1171 トランジスタ
1172 トランジスタ
1173 容量素子
1180 メモリセル
1181 トランジスタ
1182 トランジスタ
1183 容量素子
1189 ROMインターフェース
1190 基板
1191 ALU
1192 ALUコントローラ
1193 インストラクションデコーダ
1194 インタラプトコントローラ
1195 タイミングコントローラ
1196 レジスタ
1197 レジスタコントローラ
1198 バスインターフェース
1199 ROM
Claims (11)
- 第1の領域と、前記第1の領域の側面に接した一対の第2の領域と、前記一対の第2の領域の側面に接した一対の第3の領域と、を含む酸化物半導体膜と、
前記酸化物半導体膜上に設けられたゲート絶縁膜と、
前記第1の領域と重畳し、前記ゲート絶縁膜上に設けられた第1の電極と、を有し、
前記第1の領域は、非単結晶であり、かつc軸配向の結晶領域を有する酸化物半導体領域であり、
前記一対の第2の領域及び前記一対の第3の領域は、ドーパントを含む非晶質な酸化物半導体領域であり、
前記一対の第3の領域のドーパント濃度は、前記一対の第2の領域のドーパント濃度より高いことを特徴とする半導体装置。 - 請求項1において、
前記第1の電極の側面に設けられたサイドウォール絶縁膜と、
前記一対の第3の領域に電気的に接続された第2の電極及び第3の電極と、を有する
ことを特徴とする半導体装置。 - 請求項2において、
前記第2の電極及び第3の電極は、前記一対の第3の領域の上面に接していることを特徴とする半導体装置。 - 請求項2において、
前記第2の電極及び第3の電極は、前記一対の第3の領域の下面に接していることを特徴とする半導体装置。 - 請求項1乃至請求項4のいずれか一において、
前記ゲート絶縁膜は、前記第1の領域、前記一対の第2の領域、及び前記一対の第3の領域上に設けられていることを特徴とする半導体装置。 - 請求項1乃至請求項4のいずれか一において、
前記ゲート絶縁膜は、前記第1の領域上に設けられていることを特徴とする半導体装置。 - 請求項2乃至請求項6のいずれか一において、
前記ゲート絶縁膜は、酸化物絶縁体であり、
前記サイドウォール絶縁膜は、窒化物絶縁体であることを特徴とする半導体装置。 - 請求項2乃至請求項6のいずれか一において、
前記ゲート絶縁膜及び前記サイドウォール絶縁膜は、酸化物絶縁体であることを特徴とする半導体装置。 - 請求項1乃至請求項8のいずれか一において、
前記一対の第2の領域及び前記一対の第3の領域は、前記ドーパントとして、水素又は希ガス元素から選ばれた一以上を含み、
前記一対の第2の領域及び前記一対の第3の領域に含まれる前記ドーパントの濃度は、5×1018atoms/cm3以上1×1022atoms/cm3以下であることを特徴とする半導体装置。 - 請求項1乃至請求項8のいずれか一において、
前記一対の第2の領域及び前記一対の第3の領域は、前記ドーパントとして、水素又は希ガス元素から選ばれた一以上を含み、
前記一対の第2の領域に含まれる前記ドーパントの濃度は、5×1018atoms/cm3以上5×1019atoms/cm3未満であり、
前記一対の第3の領域に含まれる前記ドーパントの濃度は、5×1019atoms/cm3以上1×1022atoms/cm3以下であることを特徴とする半導体装置。 - 請求項1乃至請求項10のいずれか一において、
前記酸化物半導体膜は、In、Ga、Sn及びZnから選ばれた二以上の元素を含むことを特徴とする半導体装置。
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US20200013903A1 (en) | 2020-01-09 |
JP2023153225A (ja) | 2023-10-17 |
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US20160247939A1 (en) | 2016-08-25 |
JP2018139294A (ja) | 2018-09-06 |
JP5784479B2 (ja) | 2015-09-24 |
US11923249B2 (en) | 2024-03-05 |
JP2017130684A (ja) | 2017-07-27 |
JP2019087758A (ja) | 2019-06-06 |
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US20150125992A1 (en) | 2015-05-07 |
US20120161121A1 (en) | 2012-06-28 |
US10886414B2 (en) | 2021-01-05 |
JP6320593B2 (ja) | 2018-05-09 |
US8941112B2 (en) | 2015-01-27 |
JP2022033289A (ja) | 2022-02-28 |
JP6683854B2 (ja) | 2020-04-22 |
JP2015188116A (ja) | 2015-10-29 |
CN102569351A (zh) | 2012-07-11 |
JP6118849B2 (ja) | 2017-04-19 |
JP6479236B2 (ja) | 2019-03-06 |
CN108321091A (zh) | 2018-07-24 |
JP2020127013A (ja) | 2020-08-20 |
US10522692B2 (en) | 2019-12-31 |
JP7331159B2 (ja) | 2023-08-22 |
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