JP2011258941A - 半導体装置 - Google Patents
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Abstract
【解決手段】通常のゲート電極の他に、閾値電圧を制御するための第2のゲート電極が備えられたnチャネル型トランジスタ、或いはpチャネル型トランジスタを、相補型の論理回路に用いる。そして、オフ電流が極めて小さい絶縁ゲート電界効果型トランジスタをスイッチング素子として用い、上記第2のゲート電極の電位を制御する。上記スイッチング素子として機能するトランジスタは、シリコン半導体よりもバンドギャップが広く、真性キャリア密度がシリコンよりも低い半導体材料を、チャネル形成領域に含む。
【選択図】図1
Description
図1(A)に、本発明の一態様に係る半導体装置において用いられる、論理回路の構成の一例を示す。
本実施の形態では、本発明の一態様に係る半導体装置において用いられる、論理回路の構成の一例を示す。
本実施の形態では、本発明の一態様に係る半導体装置において用いられる、論理回路の構成の一例を示す。
本実施の形態では、本発明の一態様に係る半導体装置において用いられる、論理回路の構成の一例を示す。
本実施の形態では、本発明の半導体装置の一形態に相当する半導体表示装置の、構成の一例について説明する。
本実施の形態では、シリコンを用いたトランジスタと、酸化物半導体を用いたトランジスタとを有する、本発明の一態様に係る半導体装置の作製方法について説明する。
本実施の形態では、実施の形態6とは異なる構造を有する、酸化物半導体膜を用いたトランジスタについて説明する。
本発明の一態様に係る半導体装置では、論理回路が有するロジック部を、バルク状の単結晶半導体基板を用いて作製されたトランジスタで構成していても良い。
101 ロジック部
102 トランジスタ
103 pチャネル型トランジスタ
104 nチャネル型トランジスタ
105 保持容量
110 基板
111 第2のゲート電極
112 絶縁膜
113 半導体膜
114 ソース電極
115 ドレイン電極
116 絶縁膜
117 第1のゲート電極
118 絶縁膜
120 半導体膜
121 ソース電極
122 ドレイン電極
123 ゲート電極
130 ゲート電極
131 絶縁膜
132 酸化物半導体膜
133 ソース電極
134 ドレイン電極
135 絶縁膜
136 配線
200 論理回路
201 ロジック部
202 トランジスタ
203 pチャネル型トランジスタ
204 nチャネル型トランジスタ
230 回路
231 抵抗
232 抵抗
300 論理回路
301 ロジック部
302 トランジスタ
303 トランジスタ
304 pチャネル型トランジスタ
305 pチャネル型トランジスタ
306 nチャネル型トランジスタ
307 nチャネル型トランジスタ
400 論理回路
401 ロジック部
402 トランジスタ
403 トランジスタ
404 pチャネル型トランジスタ
405 pチャネル型トランジスタ
406 nチャネル型トランジスタ
407 nチャネル型トランジスタ
500 レジスタ
501 インバータ
502 インバータ
503 スイッチング素子
504 スイッチング素子
510 フリップフロップ
511 NAND
512 NAND
513 NAND
514 NAND
600 半導体表示装置
601 画素部
602 走査線駆動回路
603 信号線駆動回路
610 シフトレジスタ
611 記憶回路
612 記憶回路
613 レベルシフタ
614 DAC
615 バッファ
620 フリップフロップ
621 記憶素子
622 記憶素子
623 レベルシフタ
624 DAC
625 バッファ
700 基板
701 ゲート電極
702 絶縁膜
703 絶縁膜
704 nチャネル型トランジスタ
705 pチャネル型トランジスタ
706 半導体膜
707 半導体膜
708 絶縁膜
709 ゲート電極
710 ゲート電極
711 配線
712 絶縁膜
713 ゲート電極
714 ゲート絶縁膜
715 酸化物半導体膜
716 電極
717 電極
718 電極
719 電極
720 電極
721 電極
722 電極
723 絶縁膜
724 トランジスタ
730 ゲート電極
731 ゲート絶縁膜
732 酸化物半導体膜
733 チャネル保護膜
734 電極
735 電極
736 絶縁膜
741 ゲート電極
742 ゲート絶縁膜
743 電極
744 電極
745 酸化物半導体膜
746 絶縁膜
751 電極
752 電極
753 酸化物半導体膜
754 ゲート絶縁膜
755 ゲート電極
800 半導体基板
801 nチャネル型トランジスタ
802 pチャネル型トランジスタ
803 絶縁膜
804 絶縁膜
805 トランジスタ
806 素子分離用絶縁膜
807 pウェル
808 nウェル
809 n型の不純物領域
810 n型の不純物領域
811 ゲート絶縁膜
812 ゲート電極
813 p型の不純物領域
814 p型の不純物領域
815 ゲート電極
816 n型の不純物領域
820 電極
821 電極
822 電極
823 電極
830 ゲート電極
831 絶縁膜
832 酸化物半導体膜
833 電極
834 電極
835 絶縁膜
7001 筐体
7002 表示部
7011 筐体
7012 表示部
7013 支持台
7021 筐体
7022 表示部
7031 筐体
7032 筐体
7033 表示部
7034 表示部
7035 マイクロホン
7036 スピーカー
7037 操作キー
7038 スタイラス
7041 筐体
7042 表示部
7043 音声入力部
7044 音声出力部
7045 操作キー
7046 受光部
7051 筐体
7052 表示部
7053 操作キー
Claims (8)
- nチャネル型トランジスタと、pチャネル型トランジスタと、シリコンよりもバンドギャップが広く、真性キャリア密度がシリコンよりも低い半導体材料をチャネル形成領域に含んでいるトランジスタとを有し、
前記nチャネル型トランジスタと前記pチャネル型トランジスタとは、第1の電位が与えられている第1のノードと、第2の電位が与えられている第2のノードの間において、直列に接続されており、
前記nチャネル型トランジスタまたは前記pチャネル型トランジスタは、第1のゲート電極に加えて、チャネル形成領域を間に挟んで前記第1のゲート電極と向かい合っている第2のゲート電極を有しており、
前記nチャネル型トランジスタが有する前記第1のゲート電極及び前記pチャネル型トランジスタが有する前記第1のゲート電極に与えられる信号の論理値は一致しており、
前記トランジスタにより、前記第2のゲート電極への電位の供給が制御される半導体装置。 - nチャネル型トランジスタと、pチャネル型トランジスタと、シリコンよりもバンドギャップが広く、真性キャリア密度がシリコンよりも低い半導体材料をチャネル形成領域に含んでいるトランジスタとを有し、
前記nチャネル型トランジスタと前記pチャネル型トランジスタとは、第1の電位が与えられている第1のノードと、第2の電位が与えられている第2のノードの間において、直列に接続されており、
前記nチャネル型トランジスタまたは前記pチャネル型トランジスタは、第1のゲート電極に加えて、チャネル形成領域を間に挟んで前記第1のゲート電極と向かい合っている第2のゲート電極を有しており、
前記nチャネル型トランジスタ及び前記pチャネル型トランジスタは、前記チャネル形成領域にシリコンまたはゲルマニウムを用いており、
前記nチャネル型トランジスタが有する前記第1のゲート電極及び前記pチャネル型トランジスタが有する前記第1のゲート電極に与えられる信号の論理値は一致しており、
前記トランジスタにより、前記第2のゲート電極への電位の供給が制御される半導体装置。 - nチャネル型トランジスタと、pチャネル型トランジスタと、シリコンよりもバンドギャップが広く、真性キャリア密度がシリコンよりも低い半導体材料をチャネル形成領域に含んでいるトランジスタとを有し、
前記nチャネル型トランジスタと前記pチャネル型トランジスタとは、第1の電位が与えられている第1のノードと、第2の電位が与えられている第2のノードの間において、直列に接続されており、
前記nチャネル型トランジスタが有する前記第1のゲート電極及び前記pチャネル型トランジスタが有する前記第1のゲート電極に与えられる信号の論理値は一致しており、
前記nチャネル型トランジスタまたは前記pチャネル型トランジスタの基板電位は、前記トランジスタにより制御される半導体装置。 - nチャネル型トランジスタと、pチャネル型トランジスタと、シリコンよりもバンドギャップが広く、真性キャリア密度がシリコンよりも低い半導体材料をチャネル形成領域に含んでいるトランジスタとを有し、
前記nチャネル型トランジスタと前記pチャネル型トランジスタとは、第1の電位が与えられている第1のノードと、第2の電位が与えられている第2のノードの間において、直列に接続されており、
前記nチャネル型トランジスタが有する前記第1のゲート電極及び前記pチャネル型トランジスタが有する前記第1のゲート電極に与えられる信号の論理値は一致しており、
前記nチャネル型トランジスタ及び前記pチャネル型トランジスタは、前記チャネル形成領域にシリコンまたはゲルマニウムを用いており、
前記nチャネル型トランジスタまたは前記pチャネル型トランジスタの基板電位は、前記トランジスタにより制御される半導体装置。 - 請求項1乃至請求項4のいずれか1項において、
前記半導体材料は、酸化物半導体である半導体装置。 - 請求項5において、
前記酸化物半導体は、In−Ga−Zn−O系の酸化物半導体である半導体装置。 - 請求項5または請求項6において、
前記チャネル形成領域の水素濃度は、5×1019/cm3以下である半導体装置。 - 請求項1乃至請求項7のいずれか1項において、
前記トランジスタのオフ電流密度は、100zA/μm以下である半導体装置。
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TW201227929A (en) | 2012-07-01 |
TWI533437B (zh) | 2016-05-11 |
JP5706227B2 (ja) | 2015-04-22 |
US20110278564A1 (en) | 2011-11-17 |
KR101821112B1 (ko) | 2018-01-23 |
US8664658B2 (en) | 2014-03-04 |
KR101465463B1 (ko) | 2014-11-26 |
KR20140067985A (ko) | 2014-06-05 |
KR20110126071A (ko) | 2011-11-22 |
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