JP2011142665A5 - - Google Patents

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Publication number
JP2011142665A5
JP2011142665A5 JP2011040461A JP2011040461A JP2011142665A5 JP 2011142665 A5 JP2011142665 A5 JP 2011142665A5 JP 2011040461 A JP2011040461 A JP 2011040461A JP 2011040461 A JP2011040461 A JP 2011040461A JP 2011142665 A5 JP2011142665 A5 JP 2011142665A5
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JP
Japan
Prior art keywords
signal
inverter
semiconductor device
phase
delay
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JP2011040461A
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English (en)
Japanese (ja)
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JP5055448B2 (ja
JP2011142665A (ja
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Priority claimed from KR10-2004-0031983A external-priority patent/KR100537202B1/ko
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Publication of JP2011142665A publication Critical patent/JP2011142665A/ja
Publication of JP2011142665A5 publication Critical patent/JP2011142665A5/ja
Application granted granted Critical
Publication of JP5055448B2 publication Critical patent/JP5055448B2/ja
Expired - Fee Related legal-status Critical Current
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JP2011040461A 2004-05-06 2011-02-25 ディレイロックループのディレイロック状態の情報の使用が可能な半導体素子 Expired - Fee Related JP5055448B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2004-0031983A KR100537202B1 (ko) 2004-05-06 2004-05-06 지연고정루프의 지연고정상태 정보의 이용이 가능한반도체 소자
KR2004-031983 2004-05-06

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2004190213A Division JP2005323323A (ja) 2004-05-06 2004-06-28 ディレイロックループのディレイロック状態の情報の使用が可能な半導体素子

Publications (3)

Publication Number Publication Date
JP2011142665A JP2011142665A (ja) 2011-07-21
JP2011142665A5 true JP2011142665A5 (enExample) 2011-10-06
JP5055448B2 JP5055448B2 (ja) 2012-10-24

Family

ID=35239297

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2004190213A Pending JP2005323323A (ja) 2004-05-06 2004-06-28 ディレイロックループのディレイロック状態の情報の使用が可能な半導体素子
JP2011040461A Expired - Fee Related JP5055448B2 (ja) 2004-05-06 2011-02-25 ディレイロックループのディレイロック状態の情報の使用が可能な半導体素子

Family Applications Before (1)

Application Number Title Priority Date Filing Date
JP2004190213A Pending JP2005323323A (ja) 2004-05-06 2004-06-28 ディレイロックループのディレイロック状態の情報の使用が可能な半導体素子

Country Status (6)

Country Link
US (1) US7099232B2 (enExample)
JP (2) JP2005323323A (enExample)
KR (1) KR100537202B1 (enExample)
CN (1) CN1694181B (enExample)
DE (1) DE102004031450B4 (enExample)
TW (1) TWI287358B (enExample)

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KR100537202B1 (ko) * 2004-05-06 2005-12-16 주식회사 하이닉스반도체 지연고정루프의 지연고정상태 정보의 이용이 가능한반도체 소자
KR100713082B1 (ko) * 2005-03-02 2007-05-02 주식회사 하이닉스반도체 클럭의 듀티 비율을 조정할 수 있는 지연 고정 루프
KR100834400B1 (ko) 2005-09-28 2008-06-04 주식회사 하이닉스반도체 Ｄｒａｍ의 동작 주파수를 높이기 위한 지연고정루프 및 그의 출력드라이버
KR100743493B1 (ko) * 2006-02-21 2007-07-30 삼성전자주식회사 적응식 지연 고정 루프
JP4714037B2 (ja) * 2006-02-23 2011-06-29 シャープ株式会社 同期型メモリのコントロールシステム
KR100757921B1 (ko) 2006-03-07 2007-09-11 주식회사 하이닉스반도체 반도체 메모리 장치의 ｄｌｌ 회로 및 클럭 지연 고정 방법
JP5134779B2 (ja) * 2006-03-13 2013-01-30 ルネサスエレクトロニクス株式会社 遅延同期回路
KR100813528B1 (ko) 2006-06-27 2008-03-17 주식회사 하이닉스반도체 지연 고정 루프의 딜레이 라인 및 그 딜레이 타임 제어방법
JP2008217209A (ja) 2007-03-01 2008-09-18 Hitachi Ltd 差分スナップショット管理方法、計算機システム及びｎａｓ計算機
KR100856070B1 (ko) * 2007-03-30 2008-09-02 주식회사 하이닉스반도체 반도체 메모리 장치 및 그의 구동방법
KR100863016B1 (ko) * 2007-05-31 2008-10-13 주식회사 하이닉스반도체 동작 모드 설정 장치, 이를 포함하는 반도체 집적 회로 및반도체 집적 회로의 제어 방법
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JP5377843B2 (ja) * 2007-09-13 2013-12-25 ピーエスフォー ルクスコ エスエイアールエル タイミング制御回路及び半導体記憶装置
KR20090045773A (ko) * 2007-11-02 2009-05-08 주식회사 하이닉스반도체 고속으로 동작하는 반도체 장치의 지연 고정 회로
US7795937B2 (en) * 2008-03-26 2010-09-14 Mstar Semiconductor, Inc. Semi-digital delay locked loop circuit and method
KR100968460B1 (ko) * 2008-11-11 2010-07-07 주식회사 하이닉스반도체 Ｄｌｌ 회로 및 ｄｌｌ 회로의 업데이트 제어 장치
KR101123073B1 (ko) * 2009-05-21 2012-03-05 주식회사 하이닉스반도체 지연고정루프회로 및 이를 이용한 반도체 메모리 장치
KR101222064B1 (ko) * 2010-04-28 2013-01-15 에스케이하이닉스 주식회사 반도체 집적회로의 지연고정루프 및 그의 구동방법
US9553594B1 (en) 2015-12-15 2017-01-24 Freescale Semiconductor, Inc. Delay-locked loop with false-lock detection and recovery circuit
CN114079457A (zh) * 2020-08-11 2022-02-22 长鑫存储技术有限公司 延迟锁定环电路

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KR100537202B1 (ko) * 2004-05-06 2005-12-16 주식회사 하이닉스반도체 지연고정루프의 지연고정상태 정보의 이용이 가능한반도체 소자

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