JP2010515275A - スルーチップ接続を有するフロントエンドプロセス済ウェハ - Google Patents

スルーチップ接続を有するフロントエンドプロセス済ウェハ Download PDF

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Publication number
JP2010515275A
JP2010515275A JP2009544291A JP2009544291A JP2010515275A JP 2010515275 A JP2010515275 A JP 2010515275A JP 2009544291 A JP2009544291 A JP 2009544291A JP 2009544291 A JP2009544291 A JP 2009544291A JP 2010515275 A JP2010515275 A JP 2010515275A
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JP
Japan
Prior art keywords
vias
semiconductor wafer
layer
forming
conductive
Prior art date
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Pending
Application number
JP2009544291A
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English (en)
Japanese (ja)
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JP2010515275A5 (https=
Inventor
ジョン・トレッツァ
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Cufer Asset Ltd LLC
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Cufer Asset Ltd LLC
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Filing date
Publication date
Application filed by Cufer Asset Ltd LLC filed Critical Cufer Asset Ltd LLC
Publication of JP2010515275A publication Critical patent/JP2010515275A/ja
Publication of JP2010515275A5 publication Critical patent/JP2010515275A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0245—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising use of blind vias during the manufacture
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/213—Cross-sectional shapes or dispositions
    • H10W20/2134—TSVs extending from the semiconductor wafer into back-end-of-line layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/217—Through-semiconductor vias, e.g. TSVs comprising ring-shaped isolation structures outside of the via holes

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2009544291A 2006-12-29 2007-12-28 スルーチップ接続を有するフロントエンドプロセス済ウェハ Pending JP2010515275A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US88267106P 2006-12-29 2006-12-29
PCT/US2007/089061 WO2008083284A2 (en) 2006-12-29 2007-12-28 Front-end processed wafer having through-chip connections

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2013115456A Division JP5686851B2 (ja) 2006-12-29 2013-05-31 スルーチップ接続を有するフロントエンドプロセス済ウェハ

Publications (2)

Publication Number Publication Date
JP2010515275A true JP2010515275A (ja) 2010-05-06
JP2010515275A5 JP2010515275A5 (https=) 2010-10-28

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ID=39589215

Family Applications (2)

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JP2009544291A Pending JP2010515275A (ja) 2006-12-29 2007-12-28 スルーチップ接続を有するフロントエンドプロセス済ウェハ
JP2013115456A Active JP5686851B2 (ja) 2006-12-29 2013-05-31 スルーチップ接続を有するフロントエンドプロセス済ウェハ

Family Applications After (1)

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Country Status (5)

Country Link
EP (1) EP2097924A4 (https=)
JP (2) JP2010515275A (https=)
KR (1) KR101088926B1 (https=)
CN (1) CN101663742B (https=)
WO (1) WO2008083284A2 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013201353A (ja) * 2012-03-26 2013-10-03 Renesas Electronics Corp 半導体集積回路装置の製造方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007044685B3 (de) * 2007-09-19 2009-04-02 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Elektronisches System und Verfahren zur Herstellung eines dreidimensionalen elektronischen Systems
FR2987937B1 (fr) * 2012-03-12 2014-03-28 Altatech Semiconductor Procede de realisation de plaquettes semi-conductrices
CN113380748B (zh) * 2021-05-26 2026-02-13 日月光半导体制造股份有限公司 半导体封装装置及其制造方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03218653A (ja) * 1989-11-13 1991-09-26 Mitsubishi Electric Corp エアーブリッジ金属配線を具えた半導体装置およびその製造方法
WO2004064159A1 (ja) * 2003-01-15 2004-07-29 Fujitsu Limited 半導体装置及び三次元実装半導体装置、並びに半導体装置の製造方法
JP2004221357A (ja) * 2003-01-15 2004-08-05 Shinko Electric Ind Co Ltd 半導体装置の製造方法
JP2005203752A (ja) * 2003-12-16 2005-07-28 Seiko Epson Corp 半導体装置の製造方法、半導体装置、回路基板、電子機器
JP2005310817A (ja) * 2004-04-16 2005-11-04 Seiko Epson Corp 半導体装置の製造方法、回路基板、並びに電子機器
JP2006049557A (ja) * 2004-08-04 2006-02-16 Seiko Epson Corp 半導体装置

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Publication number Priority date Publication date Assignee Title
JP3979791B2 (ja) 2000-03-08 2007-09-19 株式会社ルネサステクノロジ 半導体装置およびその製造方法
EP2560199B1 (en) * 2002-04-05 2016-08-03 STMicroelectronics S.r.l. Process for manufacturing a through insulated interconnection in a body of semiconductor material
JP4285629B2 (ja) * 2002-04-25 2009-06-24 富士通株式会社 集積回路を搭載するインターポーザ基板の作製方法
JP3748844B2 (ja) * 2002-09-25 2006-02-22 Ｎｅｃエレクトロニクス株式会社 半導体集積回路およびそのテスト方法
SE526366C3 (sv) * 2003-03-21 2005-10-26 Silex Microsystems Ab Elektriska anslutningar i substrat
JP3891299B2 (ja) * 2003-05-06 2007-03-14 セイコーエプソン株式会社 半導体装置の製造方法、半導体装置、半導体デバイス、電子機器
JP4340517B2 (ja) * 2003-10-30 2009-10-07 Ｏｋｉセミコンダクタ株式会社 半導体装置及びその製造方法
TWI228295B (en) * 2003-11-10 2005-02-21 Shih-Hsien Tseng IC structure and a manufacturing method
KR100569590B1 (ko) * 2003-12-30 2006-04-10 매그나칩 반도체 유한회사 고주파 반도체 장치 및 그 제조방법
TW200535918A (en) * 2004-03-09 2005-11-01 Japan Science & Tech Agency Semiconductor device and methods for fabricating the same, semiconductor system having laminated structure, semiconductor interposer, and semiconductor system
JP3875240B2 (ja) 2004-03-31 2007-01-31 株式会社東芝 電子部品の製造方法
WO2006014411A1 (en) * 2004-07-02 2006-02-09 Strasbaugh Method and system for processing wafers
CN102290425B (zh) * 2004-08-20 2014-04-02 Kamiyacho知识产权控股公司 具有三维层叠结构的半导体器件的制造方法
JP4524156B2 (ja) * 2004-08-30 2010-08-11 新光電気工業株式会社 半導体装置及びその製造方法
US7838997B2 (en) * 2005-06-14 2010-11-23 John Trezza Remote chip attachment
US7767493B2 (en) * 2005-06-14 2010-08-03 John Trezza Post & penetration interconnection
US7488680B2 (en) 2005-08-30 2009-02-10 International Business Machines Corporation Conductive through via process for electronic device carriers

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03218653A (ja) * 1989-11-13 1991-09-26 Mitsubishi Electric Corp エアーブリッジ金属配線を具えた半導体装置およびその製造方法
WO2004064159A1 (ja) * 2003-01-15 2004-07-29 Fujitsu Limited 半導体装置及び三次元実装半導体装置、並びに半導体装置の製造方法
JP2004221357A (ja) * 2003-01-15 2004-08-05 Shinko Electric Ind Co Ltd 半導体装置の製造方法
JP2005203752A (ja) * 2003-12-16 2005-07-28 Seiko Epson Corp 半導体装置の製造方法、半導体装置、回路基板、電子機器
JP2005310817A (ja) * 2004-04-16 2005-11-04 Seiko Epson Corp 半導体装置の製造方法、回路基板、並びに電子機器
JP2006049557A (ja) * 2004-08-04 2006-02-16 Seiko Epson Corp 半導体装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013201353A (ja) * 2012-03-26 2013-10-03 Renesas Electronics Corp 半導体集積回路装置の製造方法
US9240330B2 (en) 2012-03-26 2016-01-19 Renesas Electronics Corporation Method of manufacturing a semiconductor integrated circuit device

Also Published As

Publication number Publication date
KR101088926B1 (ko) 2011-12-01
WO2008083284A2 (en) 2008-07-10
CN101663742A (zh) 2010-03-03
WO2008083284A3 (en) 2008-08-21
JP5686851B2 (ja) 2015-03-18
JP2013175786A (ja) 2013-09-05
KR20090094371A (ko) 2009-09-04
EP2097924A4 (en) 2012-01-04
EP2097924A2 (en) 2009-09-09
CN101663742B (zh) 2013-11-06

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