EP2097924A4 - Front-end processed wafer having through-chip connections - Google Patents

Front-end processed wafer having through-chip connections

Info

Publication number
EP2097924A4
EP2097924A4 EP07870039A EP07870039A EP2097924A4 EP 2097924 A4 EP2097924 A4 EP 2097924A4 EP 07870039 A EP07870039 A EP 07870039A EP 07870039 A EP07870039 A EP 07870039A EP 2097924 A4 EP2097924 A4 EP 2097924A4
Authority
EP
European Patent Office
Prior art keywords
tranche
flea
connections
treated
tranche treated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP07870039A
Other languages
German (de)
English (en)
French (fr)
Other versions
EP2097924A2 (en
Inventor
John Trezza
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cufer Asset Ltd LLC
Original Assignee
Cufer Asset Ltd LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cufer Asset Ltd LLC filed Critical Cufer Asset Ltd LLC
Publication of EP2097924A2 publication Critical patent/EP2097924A2/en
Publication of EP2097924A4 publication Critical patent/EP2097924A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0245—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising use of blind vias during the manufacture
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/213—Cross-sectional shapes or dispositions
    • H10W20/2134—TSVs extending from the semiconductor wafer into back-end-of-line layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/217—Through-semiconductor vias, e.g. TSVs comprising ring-shaped isolation structures outside of the via holes
EP07870039A 2006-12-29 2007-12-28 Front-end processed wafer having through-chip connections Withdrawn EP2097924A4 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US88267106P 2006-12-29 2006-12-29
PCT/US2007/089061 WO2008083284A2 (en) 2006-12-29 2007-12-28 Front-end processed wafer having through-chip connections

Publications (2)

Publication Number Publication Date
EP2097924A2 EP2097924A2 (en) 2009-09-09
EP2097924A4 true EP2097924A4 (en) 2012-01-04

Family

ID=39589215

Family Applications (1)

Application Number Title Priority Date Filing Date
EP07870039A Withdrawn EP2097924A4 (en) 2006-12-29 2007-12-28 Front-end processed wafer having through-chip connections

Country Status (5)

Country Link
EP (1) EP2097924A4 (https=)
JP (2) JP2010515275A (https=)
KR (1) KR101088926B1 (https=)
CN (1) CN101663742B (https=)
WO (1) WO2008083284A2 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007044685B3 (de) * 2007-09-19 2009-04-02 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Elektronisches System und Verfahren zur Herstellung eines dreidimensionalen elektronischen Systems
FR2987937B1 (fr) * 2012-03-12 2014-03-28 Altatech Semiconductor Procede de realisation de plaquettes semi-conductrices
JP5925006B2 (ja) * 2012-03-26 2016-05-25 ルネサスエレクトロニクス株式会社 半導体集積回路装置の製造方法
CN113380748B (zh) * 2021-05-26 2026-02-13 日月光半导体制造股份有限公司 半导体封装装置及其制造方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1351288A1 (en) * 2002-04-05 2003-10-08 STMicroelectronics S.r.l. Process for manufacturing a through insulated interconnection in a body of semiconductor material
US20030200654A1 (en) * 2002-04-25 2003-10-30 Fujitsu Limited Method of manufacturing electronic circuit component
US20050001326A1 (en) * 2003-05-06 2005-01-06 Seiko Epson Corporation Semiconductor device, stacked semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument
US20050101116A1 (en) * 2003-11-10 2005-05-12 Shih-Hsien Tseng Integrated circuit device and the manufacturing method thereof
US20050139954A1 (en) * 2003-12-30 2005-06-30 Pyo Sung G. Radio frequency semiconductor device and method of manufacturing the same
EP1686623A1 (en) * 2003-10-30 2006-08-02 Japan Science and Technology Agency Semiconductor device and process for fabricating the same

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03218653A (ja) * 1989-11-13 1991-09-26 Mitsubishi Electric Corp エアーブリッジ金属配線を具えた半導体装置およびその製造方法
JP3979791B2 (ja) 2000-03-08 2007-09-19 株式会社ルネサステクノロジ 半導体装置およびその製造方法
JP3748844B2 (ja) * 2002-09-25 2006-02-22 Ｎｅｃエレクトロニクス株式会社 半導体集積回路およびそのテスト方法
JP4322508B2 (ja) * 2003-01-15 2009-09-02 新光電気工業株式会社 半導体装置の製造方法
JP4145301B2 (ja) * 2003-01-15 2008-09-03 富士通株式会社 半導体装置及び三次元実装半導体装置
SE526366C3 (sv) * 2003-03-21 2005-10-26 Silex Microsystems Ab Elektriska anslutningar i substrat
JP4114660B2 (ja) * 2003-12-16 2008-07-09 セイコーエプソン株式会社 半導体装置の製造方法、半導体装置、回路基板、電子機器
TW200535918A (en) * 2004-03-09 2005-11-01 Japan Science & Tech Agency Semiconductor device and methods for fabricating the same, semiconductor system having laminated structure, semiconductor interposer, and semiconductor system
JP3875240B2 (ja) 2004-03-31 2007-01-31 株式会社東芝 電子部品の製造方法
JP4492196B2 (ja) * 2004-04-16 2010-06-30 セイコーエプソン株式会社 半導体装置の製造方法、回路基板、並びに電子機器
WO2006014411A1 (en) * 2004-07-02 2006-02-09 Strasbaugh Method and system for processing wafers
JP2006049557A (ja) * 2004-08-04 2006-02-16 Seiko Epson Corp 半導体装置
CN102290425B (zh) * 2004-08-20 2014-04-02 Kamiyacho知识产权控股公司 具有三维层叠结构的半导体器件的制造方法
JP4524156B2 (ja) * 2004-08-30 2010-08-11 新光電気工業株式会社 半導体装置及びその製造方法
US7838997B2 (en) * 2005-06-14 2010-11-23 John Trezza Remote chip attachment
US7767493B2 (en) * 2005-06-14 2010-08-03 John Trezza Post & penetration interconnection
US7488680B2 (en) 2005-08-30 2009-02-10 International Business Machines Corporation Conductive through via process for electronic device carriers

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1351288A1 (en) * 2002-04-05 2003-10-08 STMicroelectronics S.r.l. Process for manufacturing a through insulated interconnection in a body of semiconductor material
US20030200654A1 (en) * 2002-04-25 2003-10-30 Fujitsu Limited Method of manufacturing electronic circuit component
US20050001326A1 (en) * 2003-05-06 2005-01-06 Seiko Epson Corporation Semiconductor device, stacked semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument
EP1686623A1 (en) * 2003-10-30 2006-08-02 Japan Science and Technology Agency Semiconductor device and process for fabricating the same
US20050101116A1 (en) * 2003-11-10 2005-05-12 Shih-Hsien Tseng Integrated circuit device and the manufacturing method thereof
US20050139954A1 (en) * 2003-12-30 2005-06-30 Pyo Sung G. Radio frequency semiconductor device and method of manufacturing the same

Also Published As

Publication number Publication date
JP2010515275A (ja) 2010-05-06
KR101088926B1 (ko) 2011-12-01
WO2008083284A2 (en) 2008-07-10
CN101663742A (zh) 2010-03-03
WO2008083284A3 (en) 2008-08-21
JP5686851B2 (ja) 2015-03-18
JP2013175786A (ja) 2013-09-05
KR20090094371A (ko) 2009-09-04
EP2097924A2 (en) 2009-09-09
CN101663742B (zh) 2013-11-06

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Legal Events

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PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

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Effective date: 20090619

AK Designated contracting states

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Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC MT NL PL PT RO SE SI SK TR

RIN1 Information on inventor provided before grant (corrected)

Inventor name: TREZZA, JOHN

DAX Request for extension of the european patent (deleted)
A4 Supplementary search report drawn up and despatched

Effective date: 20111201

RIC1 Information provided on ipc code assigned before grant

Ipc: H01L 21/768 20060101AFI20111125BHEP

Ipc: H01L 23/48 20060101ALI20111125BHEP

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN WITHDRAWN

18W Application withdrawn

Effective date: 20120629