JP5686851B2 - スルーチップ接続を有するフロントエンドプロセス済ウェハ - Google Patents
スルーチップ接続を有するフロントエンドプロセス済ウェハ Download PDFInfo
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- JP5686851B2 JP5686851B2 JP2013115456A JP2013115456A JP5686851B2 JP 5686851 B2 JP5686851 B2 JP 5686851B2 JP 2013115456 A JP2013115456 A JP 2013115456A JP 2013115456 A JP2013115456 A JP 2013115456A JP 5686851 B2 JP5686851 B2 JP 5686851B2
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- vias
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- 238000000034 method Methods 0.000 claims description 54
- 239000004065 semiconductor Substances 0.000 claims description 8
- 239000012212 insulator Substances 0.000 claims description 5
- 230000000149 penetrating effect Effects 0.000 claims 1
- 238000003672 processing method Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 49
- 235000012431 wafers Nutrition 0.000 description 49
- 229920002120 photoresistant polymer Polymers 0.000 description 18
- 238000013459 approach Methods 0.000 description 16
- 239000000463 material Substances 0.000 description 16
- 229910052751 metal Inorganic materials 0.000 description 13
- 239000002184 metal Substances 0.000 description 13
- 230000008901 benefit Effects 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 10
- 238000001465 metallisation Methods 0.000 description 10
- 238000007747 plating Methods 0.000 description 10
- 239000004020 conductor Substances 0.000 description 9
- 239000011231 conductive filler Substances 0.000 description 8
- 239000007787 solid Substances 0.000 description 8
- 238000000151 deposition Methods 0.000 description 6
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- BGTFCAQCKWKTRL-YDEUACAXSA-N chembl1095986 Chemical compound C1[C@@H](N)[C@@H](O)[C@H](C)O[C@H]1O[C@@H]([C@H]1C(N[C@H](C2=CC(O)=CC(O[C@@H]3[C@H]([C@@H](O)[C@H](O)[C@@H](CO)O3)O)=C2C=2C(O)=CC=C(C=2)[C@@H](NC(=O)[C@@H]2NC(=O)[C@@H]3C=4C=C(C(=C(O)C=4)C)OC=4C(O)=CC=C(C=4)[C@@H](N)C(=O)N[C@@H](C(=O)N3)[C@H](O)C=3C=CC(O4)=CC=3)C(=O)N1)C(O)=O)=O)C(C=C1)=CC=C1OC1=C(O[C@@H]3[C@H]([C@H](O)[C@@H](O)[C@H](CO[C@@H]5[C@H]([C@@H](O)[C@H](O)[C@@H](C)O5)O)O3)O[C@@H]3[C@H]([C@@H](O)[C@H](O)[C@@H](CO)O3)O[C@@H]3[C@H]([C@H](O)[C@@H](CO)O3)O)C4=CC2=C1 BGTFCAQCKWKTRL-YDEUACAXSA-N 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 239000002344 surface layer Substances 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Description
[関連出願の相互参照]
Claims (3)
- 半導体ウェハに複数のバイアを形成する工程であって、前記複数のバイアは、少なくとも1つの環状バイアを含む工程と、
前記複数のバイアのうちの少なくとも幾つかを導電性にする工程と、
前記複数のバイア上にメタライズ層を形成する工程と、
前記環状バイアに絶縁体を充填する工程と、
前記環状バイアによって囲まれた中央ポストに、前記中央ポストを導電性にするためにドーピングする工程と、
を備える半導体ウェハ処理方法。 - 前記環状バイアを形成する工程は、前記半導体ウェハを貫通しない前記環状バイアを形成する工程を含む、
請求項1に記載の方法。 - 前記ドーピングする工程は、フロントエンドプロセスで実行され、前記方法は、前記半導体ウェハの底部を除去する工程をさらに備える、
請求項1または2に記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US88267106P | 2006-12-29 | 2006-12-29 | |
US60/882,671 | 2006-12-29 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009544291A Division JP2010515275A (ja) | 2006-12-29 | 2007-12-28 | スルーチップ接続を有するフロントエンドプロセス済ウェハ |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2013175786A JP2013175786A (ja) | 2013-09-05 |
JP5686851B2 true JP5686851B2 (ja) | 2015-03-18 |
Family
ID=39589215
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009544291A Pending JP2010515275A (ja) | 2006-12-29 | 2007-12-28 | スルーチップ接続を有するフロントエンドプロセス済ウェハ |
JP2013115456A Active JP5686851B2 (ja) | 2006-12-29 | 2013-05-31 | スルーチップ接続を有するフロントエンドプロセス済ウェハ |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009544291A Pending JP2010515275A (ja) | 2006-12-29 | 2007-12-28 | スルーチップ接続を有するフロントエンドプロセス済ウェハ |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP2097924A4 (ja) |
JP (2) | JP2010515275A (ja) |
KR (1) | KR101088926B1 (ja) |
CN (1) | CN101663742B (ja) |
WO (1) | WO2008083284A2 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102007044685B3 (de) * | 2007-09-19 | 2009-04-02 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Elektronisches System und Verfahren zur Herstellung eines dreidimensionalen elektronischen Systems |
FR2987937B1 (fr) * | 2012-03-12 | 2014-03-28 | Altatech Semiconductor | Procede de realisation de plaquettes semi-conductrices |
JP5925006B2 (ja) * | 2012-03-26 | 2016-05-25 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置の製造方法 |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03218653A (ja) * | 1989-11-13 | 1991-09-26 | Mitsubishi Electric Corp | エアーブリッジ金属配線を具えた半導体装置およびその製造方法 |
JP3979791B2 (ja) | 2000-03-08 | 2007-09-19 | 株式会社ルネサステクノロジ | 半導体装置およびその製造方法 |
EP1351288B1 (en) * | 2002-04-05 | 2015-10-28 | STMicroelectronics Srl | Process for manufacturing an insulated interconnection through a body of semiconductor material and corresponding semiconductor device |
JP4285629B2 (ja) * | 2002-04-25 | 2009-06-24 | 富士通株式会社 | 集積回路を搭載するインターポーザ基板の作製方法 |
JP3748844B2 (ja) * | 2002-09-25 | 2006-02-22 | Necエレクトロニクス株式会社 | 半導体集積回路およびそのテスト方法 |
WO2004064159A1 (ja) * | 2003-01-15 | 2004-07-29 | Fujitsu Limited | 半導体装置及び三次元実装半導体装置、並びに半導体装置の製造方法 |
JP4322508B2 (ja) * | 2003-01-15 | 2009-09-02 | 新光電気工業株式会社 | 半導体装置の製造方法 |
SE526366C3 (sv) * | 2003-03-21 | 2005-10-26 | Silex Microsystems Ab | Elektriska anslutningar i substrat |
JP3891299B2 (ja) * | 2003-05-06 | 2007-03-14 | セイコーエプソン株式会社 | 半導体装置の製造方法、半導体装置、半導体デバイス、電子機器 |
JP4340517B2 (ja) * | 2003-10-30 | 2009-10-07 | Okiセミコンダクタ株式会社 | 半導体装置及びその製造方法 |
TWI228295B (en) * | 2003-11-10 | 2005-02-21 | Shih-Hsien Tseng | IC structure and a manufacturing method |
JP4114660B2 (ja) * | 2003-12-16 | 2008-07-09 | セイコーエプソン株式会社 | 半導体装置の製造方法、半導体装置、回路基板、電子機器 |
KR100569590B1 (ko) * | 2003-12-30 | 2006-04-10 | 매그나칩 반도체 유한회사 | 고주파 반도체 장치 및 그 제조방법 |
WO2005086216A1 (ja) * | 2004-03-09 | 2005-09-15 | Japan Science And Technology Agency | 半導体素子及び半導体素子の製造方法 |
JP3875240B2 (ja) | 2004-03-31 | 2007-01-31 | 株式会社東芝 | 電子部品の製造方法 |
JP4492196B2 (ja) * | 2004-04-16 | 2010-06-30 | セイコーエプソン株式会社 | 半導体装置の製造方法、回路基板、並びに電子機器 |
US7249992B2 (en) * | 2004-07-02 | 2007-07-31 | Strasbaugh | Method, apparatus and system for use in processing wafers |
JP2006049557A (ja) * | 2004-08-04 | 2006-02-16 | Seiko Epson Corp | 半導体装置 |
WO2006019156A1 (ja) * | 2004-08-20 | 2006-02-23 | Zycube Co., Ltd. | 三次元積層構造を持つ半導体装置の製造方法 |
JP4524156B2 (ja) * | 2004-08-30 | 2010-08-11 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
US7838997B2 (en) * | 2005-06-14 | 2010-11-23 | John Trezza | Remote chip attachment |
US7215032B2 (en) * | 2005-06-14 | 2007-05-08 | Cubic Wafer, Inc. | Triaxial through-chip connection |
US7488680B2 (en) | 2005-08-30 | 2009-02-10 | International Business Machines Corporation | Conductive through via process for electronic device carriers |
-
2007
- 2007-12-28 CN CN2007800479122A patent/CN101663742B/zh active Active
- 2007-12-28 EP EP07870039A patent/EP2097924A4/en not_active Withdrawn
- 2007-12-28 JP JP2009544291A patent/JP2010515275A/ja active Pending
- 2007-12-28 WO PCT/US2007/089061 patent/WO2008083284A2/en active Application Filing
- 2007-12-28 KR KR1020097014823A patent/KR101088926B1/ko active IP Right Grant
-
2013
- 2013-05-31 JP JP2013115456A patent/JP5686851B2/ja active Active
Also Published As
Publication number | Publication date |
---|---|
KR101088926B1 (ko) | 2011-12-01 |
JP2013175786A (ja) | 2013-09-05 |
KR20090094371A (ko) | 2009-09-04 |
CN101663742B (zh) | 2013-11-06 |
WO2008083284A3 (en) | 2008-08-21 |
CN101663742A (zh) | 2010-03-03 |
EP2097924A2 (en) | 2009-09-09 |
EP2097924A4 (en) | 2012-01-04 |
JP2010515275A (ja) | 2010-05-06 |
WO2008083284A2 (en) | 2008-07-10 |
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