CN101663742B - 具有贯穿芯片连接的前端处理晶片 - Google Patents

具有贯穿芯片连接的前端处理晶片 Download PDF

Info

Publication number
CN101663742B
CN101663742B CN2007800479122A CN200780047912A CN101663742B CN 101663742 B CN101663742 B CN 101663742B CN 2007800479122 A CN2007800479122 A CN 2007800479122A CN 200780047912 A CN200780047912 A CN 200780047912A CN 101663742 B CN101663742 B CN 101663742B
Authority
CN
China
Prior art keywords
via hole
semiconductor wafer
end processing
vias
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN2007800479122A
Other languages
English (en)
Chinese (zh)
Other versions
CN101663742A (zh
Inventor
约翰·特雷扎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cufer Asset Ltd LLC
Original Assignee
Cufer Asset Ltd LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cufer Asset Ltd LLC filed Critical Cufer Asset Ltd LLC
Publication of CN101663742A publication Critical patent/CN101663742A/zh
Application granted granted Critical
Publication of CN101663742B publication Critical patent/CN101663742B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0245—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising use of blind vias during the manufacture
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/213—Cross-sectional shapes or dispositions
    • H10W20/2134—TSVs extending from the semiconductor wafer into back-end-of-line layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/217—Through-semiconductor vias, e.g. TSVs comprising ring-shaped isolation structures outside of the via holes

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
CN2007800479122A 2006-12-29 2007-12-28 具有贯穿芯片连接的前端处理晶片 Active CN101663742B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US88267106P 2006-12-29 2006-12-29
US60/882,671 2006-12-29
PCT/US2007/089061 WO2008083284A2 (en) 2006-12-29 2007-12-28 Front-end processed wafer having through-chip connections

Publications (2)

Publication Number Publication Date
CN101663742A CN101663742A (zh) 2010-03-03
CN101663742B true CN101663742B (zh) 2013-11-06

Family

ID=39589215

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2007800479122A Active CN101663742B (zh) 2006-12-29 2007-12-28 具有贯穿芯片连接的前端处理晶片

Country Status (5)

Country Link
EP (1) EP2097924A4 (https=)
JP (2) JP2010515275A (https=)
KR (1) KR101088926B1 (https=)
CN (1) CN101663742B (https=)
WO (1) WO2008083284A2 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007044685B3 (de) * 2007-09-19 2009-04-02 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Elektronisches System und Verfahren zur Herstellung eines dreidimensionalen elektronischen Systems
FR2987937B1 (fr) * 2012-03-12 2014-03-28 Altatech Semiconductor Procede de realisation de plaquettes semi-conductrices
JP5925006B2 (ja) * 2012-03-26 2016-05-25 ルネサスエレクトロニクス株式会社 半導体集積回路装置の製造方法
CN113380748B (zh) * 2021-05-26 2026-02-13 日月光半导体制造股份有限公司 半导体封装装置及其制造方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1791975A (zh) * 2003-03-21 2006-06-21 西雷克斯微系统股份有限公司 衬底内的电连接

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03218653A (ja) * 1989-11-13 1991-09-26 Mitsubishi Electric Corp エアーブリッジ金属配線を具えた半導体装置およびその製造方法
JP3979791B2 (ja) 2000-03-08 2007-09-19 株式会社ルネサステクノロジ 半導体装置およびその製造方法
EP2560199B1 (en) * 2002-04-05 2016-08-03 STMicroelectronics S.r.l. Process for manufacturing a through insulated interconnection in a body of semiconductor material
JP4285629B2 (ja) * 2002-04-25 2009-06-24 富士通株式会社 集積回路を搭載するインターポーザ基板の作製方法
JP3748844B2 (ja) * 2002-09-25 2006-02-22 Ｎｅｃエレクトロニクス株式会社 半導体集積回路およびそのテスト方法
JP4322508B2 (ja) * 2003-01-15 2009-09-02 新光電気工業株式会社 半導体装置の製造方法
JP4145301B2 (ja) * 2003-01-15 2008-09-03 富士通株式会社 半導体装置及び三次元実装半導体装置
JP3891299B2 (ja) * 2003-05-06 2007-03-14 セイコーエプソン株式会社 半導体装置の製造方法、半導体装置、半導体デバイス、電子機器
JP4340517B2 (ja) * 2003-10-30 2009-10-07 Ｏｋｉセミコンダクタ株式会社 半導体装置及びその製造方法
TWI228295B (en) * 2003-11-10 2005-02-21 Shih-Hsien Tseng IC structure and a manufacturing method
JP4114660B2 (ja) * 2003-12-16 2008-07-09 セイコーエプソン株式会社 半導体装置の製造方法、半導体装置、回路基板、電子機器
KR100569590B1 (ko) * 2003-12-30 2006-04-10 매그나칩 반도체 유한회사 고주파 반도체 장치 및 그 제조방법
TW200535918A (en) * 2004-03-09 2005-11-01 Japan Science & Tech Agency Semiconductor device and methods for fabricating the same, semiconductor system having laminated structure, semiconductor interposer, and semiconductor system
JP3875240B2 (ja) 2004-03-31 2007-01-31 株式会社東芝 電子部品の製造方法
JP4492196B2 (ja) * 2004-04-16 2010-06-30 セイコーエプソン株式会社 半導体装置の製造方法、回路基板、並びに電子機器
WO2006014411A1 (en) * 2004-07-02 2006-02-09 Strasbaugh Method and system for processing wafers
JP2006049557A (ja) * 2004-08-04 2006-02-16 Seiko Epson Corp 半導体装置
CN102290425B (zh) * 2004-08-20 2014-04-02 Kamiyacho知识产权控股公司 具有三维层叠结构的半导体器件的制造方法
JP4524156B2 (ja) * 2004-08-30 2010-08-11 新光電気工業株式会社 半導体装置及びその製造方法
US7838997B2 (en) * 2005-06-14 2010-11-23 John Trezza Remote chip attachment
US7767493B2 (en) * 2005-06-14 2010-08-03 John Trezza Post & penetration interconnection
US7488680B2 (en) 2005-08-30 2009-02-10 International Business Machines Corporation Conductive through via process for electronic device carriers

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1791975A (zh) * 2003-03-21 2006-06-21 西雷克斯微系统股份有限公司 衬底内的电连接

Also Published As

Publication number Publication date
JP2010515275A (ja) 2010-05-06
KR101088926B1 (ko) 2011-12-01
WO2008083284A2 (en) 2008-07-10
CN101663742A (zh) 2010-03-03
WO2008083284A3 (en) 2008-08-21
JP5686851B2 (ja) 2015-03-18
JP2013175786A (ja) 2013-09-05
KR20090094371A (ko) 2009-09-04
EP2097924A4 (en) 2012-01-04
EP2097924A2 (en) 2009-09-09

Similar Documents

Publication Publication Date Title
US7687397B2 (en) Front-end processed wafer having through-chip connections
US7897484B2 (en) Fabricating a top conductive layer in a semiconductor die
US20090218698A1 (en) Wafer-Level Integrated Circuit Package with Top and Bottom Side Electrical Connections
US20160118367A1 (en) Redistribution layers for microfeature workpieces, and associated systems and methods
JP2019515511A (ja) ３ｄ集積デバイスにおける相互接続のためのバリア層
US12438120B2 (en) Chip package structure with redistribution layer having bonding portion
US10262959B2 (en) Semiconductor devices and methods of forming thereof
KR101132825B1 (ko) 알루미늄이 함유되지 않은 솔더 범프 연결용 다이 영역 및 알루미늄이 함유되지 않은 와이어 본딩 용 테스트 구조를 포함하는 반도체 디바이스
US9646944B2 (en) Alignment structures and methods of forming same
CN104037145A (zh) 用于晶片级封装的由垫限定的接触
US20110057305A1 (en) Package substrate having semiconductor component embedded therein and fabrication method thereof
US7998854B2 (en) Wafer level integration module with interconnects
CN107342232A (zh) 晶片封装体的形成方法
CN101663742B (zh) 具有贯穿芯片连接的前端处理晶片
US20240096828A1 (en) Semiconductor structure having dummy conductive member and manufacturing method thereof
CN114883311A (zh) 接合的晶圆结构及其制作方法
US9837366B1 (en) Semicondcutor structure and semiconductor manufacturing process thereof
CN101188231A (zh) 半导体器件和半导体晶片及其制造方法
US8329573B2 (en) Wafer level integration module having controlled resistivity interconnects
CN110379767A (zh) 晶圆级封装芯片通孔互连的方法以及芯片的测试方法
CN102915921A (zh) 通过装设附加保护层以在运送期间保护半导体装置的反应性金属表面的技术
US20240128217A1 (en) Semiconductor device and manufacturing method thereof
CN120089600A (zh) 一种从基材表面去除残留物的方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant