KR101088926B1 - 쓰루-칩 연결부들을 지닌 프론트-엔드 공정처리된 웨이퍼 - Google Patents

쓰루-칩 연결부들을 지닌 프론트-엔드 공정처리된 웨이퍼 Download PDF

Info

Publication number
KR101088926B1
KR101088926B1 KR1020097014823A KR20097014823A KR101088926B1 KR 101088926 B1 KR101088926 B1 KR 101088926B1 KR 1020097014823 A KR1020097014823 A KR 1020097014823A KR 20097014823 A KR20097014823 A KR 20097014823A KR 101088926 B1 KR101088926 B1 KR 101088926B1
Authority
KR
South Korea
Prior art keywords
vias
semiconductor wafer
forming
electrically conductive
delete delete
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020097014823A
Other languages
English (en)
Korean (ko)
Other versions
KR20090094371A (ko
Inventor
존 트레자
Original Assignee
쿠퍼 에셋 엘티디. 엘.엘.씨.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 쿠퍼 에셋 엘티디. 엘.엘.씨. filed Critical 쿠퍼 에셋 엘티디. 엘.엘.씨.
Publication of KR20090094371A publication Critical patent/KR20090094371A/ko
Application granted granted Critical
Publication of KR101088926B1 publication Critical patent/KR101088926B1/ko
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0245—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising use of blind vias during the manufacture
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/213—Cross-sectional shapes or dispositions
    • H10W20/2134—TSVs extending from the semiconductor wafer into back-end-of-line layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/217—Through-semiconductor vias, e.g. TSVs comprising ring-shaped isolation structures outside of the via holes

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1020097014823A 2006-12-29 2007-12-28 쓰루-칩 연결부들을 지닌 프론트-엔드 공정처리된 웨이퍼 Active KR101088926B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US88267106P 2006-12-29 2006-12-29
US60/882,671 2006-12-29
PCT/US2007/089061 WO2008083284A2 (en) 2006-12-29 2007-12-28 Front-end processed wafer having through-chip connections

Publications (2)

Publication Number Publication Date
KR20090094371A KR20090094371A (ko) 2009-09-04
KR101088926B1 true KR101088926B1 (ko) 2011-12-01

Family

ID=39589215

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020097014823A Active KR101088926B1 (ko) 2006-12-29 2007-12-28 쓰루-칩 연결부들을 지닌 프론트-엔드 공정처리된 웨이퍼

Country Status (5)

Country Link
EP (1) EP2097924A4 (https=)
JP (2) JP2010515275A (https=)
KR (1) KR101088926B1 (https=)
CN (1) CN101663742B (https=)
WO (1) WO2008083284A2 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007044685B3 (de) * 2007-09-19 2009-04-02 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Elektronisches System und Verfahren zur Herstellung eines dreidimensionalen elektronischen Systems
FR2987937B1 (fr) * 2012-03-12 2014-03-28 Altatech Semiconductor Procede de realisation de plaquettes semi-conductrices
JP5925006B2 (ja) * 2012-03-26 2016-05-25 ルネサスエレクトロニクス株式会社 半導体集積回路装置の製造方法
CN113380748B (zh) * 2021-05-26 2026-02-13 日月光半导体制造股份有限公司 半导体封装装置及其制造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010030366A1 (en) 2000-03-08 2001-10-18 Hiroshi Nakano Semiconducting system and production method
US20050218488A1 (en) 2004-03-31 2005-10-06 Mie Matsuo Electronic component having micro-electrical mechanical system
US20060281363A1 (en) * 2005-06-14 2006-12-14 John Trezza Remote chip attachment
US20070048896A1 (en) 2005-08-30 2007-03-01 International Business Machines Corporation Conductive through via structure and process for electronic device carriers

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03218653A (ja) * 1989-11-13 1991-09-26 Mitsubishi Electric Corp エアーブリッジ金属配線を具えた半導体装置およびその製造方法
EP2560199B1 (en) * 2002-04-05 2016-08-03 STMicroelectronics S.r.l. Process for manufacturing a through insulated interconnection in a body of semiconductor material
JP4285629B2 (ja) * 2002-04-25 2009-06-24 富士通株式会社 集積回路を搭載するインターポーザ基板の作製方法
JP3748844B2 (ja) * 2002-09-25 2006-02-22 Ｎｅｃエレクトロニクス株式会社 半導体集積回路およびそのテスト方法
JP4322508B2 (ja) * 2003-01-15 2009-09-02 新光電気工業株式会社 半導体装置の製造方法
JP4145301B2 (ja) * 2003-01-15 2008-09-03 富士通株式会社 半導体装置及び三次元実装半導体装置
SE526366C3 (sv) * 2003-03-21 2005-10-26 Silex Microsystems Ab Elektriska anslutningar i substrat
JP3891299B2 (ja) * 2003-05-06 2007-03-14 セイコーエプソン株式会社 半導体装置の製造方法、半導体装置、半導体デバイス、電子機器
JP4340517B2 (ja) * 2003-10-30 2009-10-07 Ｏｋｉセミコンダクタ株式会社 半導体装置及びその製造方法
TWI228295B (en) * 2003-11-10 2005-02-21 Shih-Hsien Tseng IC structure and a manufacturing method
JP4114660B2 (ja) * 2003-12-16 2008-07-09 セイコーエプソン株式会社 半導体装置の製造方法、半導体装置、回路基板、電子機器
KR100569590B1 (ko) * 2003-12-30 2006-04-10 매그나칩 반도체 유한회사 고주파 반도체 장치 및 그 제조방법
TW200535918A (en) * 2004-03-09 2005-11-01 Japan Science & Tech Agency Semiconductor device and methods for fabricating the same, semiconductor system having laminated structure, semiconductor interposer, and semiconductor system
JP4492196B2 (ja) * 2004-04-16 2010-06-30 セイコーエプソン株式会社 半導体装置の製造方法、回路基板、並びに電子機器
WO2006014411A1 (en) * 2004-07-02 2006-02-09 Strasbaugh Method and system for processing wafers
JP2006049557A (ja) * 2004-08-04 2006-02-16 Seiko Epson Corp 半導体装置
CN102290425B (zh) * 2004-08-20 2014-04-02 Kamiyacho知识产权控股公司 具有三维层叠结构的半导体器件的制造方法
JP4524156B2 (ja) * 2004-08-30 2010-08-11 新光電気工業株式会社 半導体装置及びその製造方法
US7767493B2 (en) * 2005-06-14 2010-08-03 John Trezza Post & penetration interconnection

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010030366A1 (en) 2000-03-08 2001-10-18 Hiroshi Nakano Semiconducting system and production method
US20050218488A1 (en) 2004-03-31 2005-10-06 Mie Matsuo Electronic component having micro-electrical mechanical system
US20060281363A1 (en) * 2005-06-14 2006-12-14 John Trezza Remote chip attachment
US20070048896A1 (en) 2005-08-30 2007-03-01 International Business Machines Corporation Conductive through via structure and process for electronic device carriers

Also Published As

Publication number Publication date
JP2010515275A (ja) 2010-05-06
WO2008083284A2 (en) 2008-07-10
CN101663742A (zh) 2010-03-03
WO2008083284A3 (en) 2008-08-21
JP5686851B2 (ja) 2015-03-18
JP2013175786A (ja) 2013-09-05
KR20090094371A (ko) 2009-09-04
EP2097924A4 (en) 2012-01-04
EP2097924A2 (en) 2009-09-09
CN101663742B (zh) 2013-11-06

Similar Documents

Publication Publication Date Title
US7687397B2 (en) Front-end processed wafer having through-chip connections
US7919835B2 (en) Semiconductor device and method for manufacturing the same
US7453150B1 (en) Three-dimensional face-to-face integration assembly
KR101379115B1 (ko) 퓨즈-타입 쓰루 실리콘 비아를 갖는 3ｄ 칩-스택
US7897484B2 (en) Fabricating a top conductive layer in a semiconductor die
US10424508B2 (en) Interconnection structure having a via structure and fabrication thereof
US11605596B2 (en) Semiconductor device having through silicon vias
TW202010069A (zh) 晶片封裝結構之形成方法
KR101088926B1 (ko) 쓰루-칩 연결부들을 지닌 프론트-엔드 공정처리된 웨이퍼
WO2009136873A2 (en) Wafer level integration module with interconnects
US8329573B2 (en) Wafer level integration module having controlled resistivity interconnects
US9478489B2 (en) Semiconductor dies with reduced area consumption
CN108122781B (zh) 半导体结构及其制造方法
US12334463B2 (en) Semiconductor structure having copper pillar within solder bump and manufacturing method thereof
US20200105646A1 (en) Semiconductor structure having through silicon via structure and method for forming the same
TWI871628B (zh) 凸塊結構及其製作方法
TWI857265B (zh) 半導體裝置及其製程
US12272620B2 (en) Semiconductor structure having elastic member within via
CN101060119B (zh) 集成电路结构及其制造方法
CN120637319A (zh) 半导体结构及其制造方法
CN113097091A (zh) 一种半导体结构及其制造方法

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

A201 Request for examination
E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

FPAY Annual fee payment

Payment date: 20141030

Year of fee payment: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

FPAY Annual fee payment

Payment date: 20161028

Year of fee payment: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

FPAY Annual fee payment

Payment date: 20170929

Year of fee payment: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

FPAY Annual fee payment

Payment date: 20180928

Year of fee payment: 8

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

FPAY Annual fee payment

Payment date: 20190924

Year of fee payment: 9

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 9

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 10

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 11

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 12

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 13

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 14

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000