TW202010069A - 晶片封裝結構之形成方法 - Google Patents

晶片封裝結構之形成方法 Download PDF

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TW202010069A
TW202010069A TW108127663A TW108127663A TW202010069A TW 202010069 A TW202010069 A TW 202010069A TW 108127663 A TW108127663 A TW 108127663A TW 108127663 A TW108127663 A TW 108127663A TW 202010069 A TW202010069 A TW 202010069A
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Taiwan
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layer
redistribution layer
chip package
width
bonding portion
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TW108127663A
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English (en)
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志航 董
邵棟樑
楊素純
張耕銘
余振華
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台灣積體電路製造股份有限公司
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Publication of TW202010069A publication Critical patent/TW202010069A/zh

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Abstract

本發明實施例提供一種晶片封裝結構之形成方法。上述方法包括部分地移除第一重分佈層以於第一重分佈層中形成校準溝槽。校準溝槽圍繞第一重分佈層的第一接合部分。上述方法包括於第一接合部分之上形成液相層、於液相層之上設置晶片結構。第一接合部分的第一寬度大抵上等於晶片結構的第二寬度。上述方法包括將液相層蒸發。在將液相層蒸發之後晶片結構接合至第一接合部分。

Description

晶片封裝結構之形成方法
本發明實施例有關於一種晶片封裝結構及其形成方法，且特別有關於一種將晶片結構接合至重分佈層(redistribution layer)的方法。
半導體裝置被使用於各種電子裝置中，例如:個人電腦、手機、數位相機以及其他電子設備。一般而言，在半導體基板上依序沉積絕緣或介電層、導電層以及半導體層，並且以微影之方式將各材料層圖案化以於其上形成電路組件及元件，藉此製造半導體裝置。
半導體工業經由持續降低最小特徵部件尺寸持續精進各電子組件(例如:電晶體、二極體、電阻器、電容器等)的集積密度(integration density)，這使得更多組件可被整合至一給定面積。在一些應用中，這些較小的電子組件亦使用較小的封裝，上述較小的封裝佔有面積較小或高度較低。
已發展新的封裝技術以增半導體裝置之密度與功能。這些相對較新的半導體裝置封裝技術面臨製造上的挑戰。
本發明實施例包括一種晶片封裝結構之形成方法。上述方法包括部分地移除第一重分佈層以於上述第一重分佈層中形成校準溝槽。上述校準溝槽圍繞上述第一重分佈層的第一接合部分。上述方法包括於上述第一接合部分之上形成液相層、於上述液相層之上設置晶片結構。上述第一接合部分的第一寬度大抵上等於上述晶片結構的第二寬度。上述方法包括將上述液相層蒸發。在將上述液相層蒸發的步驟之後上述晶片結構接合至上述第一接合部分。
本發明實施例亦包括一種形成晶片封裝結構的方法。上述方法包括部分地移除載體基板以於上述載體基板中形成校準溝槽。上述校準溝槽圍繞上述載體基板的接合部分。上述方法亦包括於上述接合部分之上形成液相層、於上述液相層之上設置晶片結構。上述晶片結構與上述接合部分具有相同的形狀。上述方法亦包括將上述液相層蒸發。在將上述液相層蒸發的步驟之後上述晶片結構接合至上述接合部分。
本發明實施例又包括一種晶片封裝結構。上述晶片封裝結構包括第一重分佈層、晶片結構以及保護層。上述第一重分佈層具有接合部分。上述晶片結構接合至上述接合部分，上述接合部分的第一寬度大抵上等於上述晶片結構的第二寬度。上述保護層位於上述第一重分佈層之上且圍繞上述晶片結構。上述保護層的一部分延伸至上述第一重分佈層中且圍繞上述接合部分。
以下的揭露內容提供許多不同的實施例或範例以實施本案的不同特徵。以下的揭露內容敘述各個構件及其排列方式的特定範例，以簡化說明。當然，這些特定的範例並非用以限定。例如，若是本發明實施例敘述了一第一特徵部件形成於一第二特徵部件之上或上方，即表示其可能包含上述第一特徵部件與上述第二特徵部件是直接接觸的實施例，亦可能包含了有附加特徵部件形成於上述第一特徵部件與上述第二特徵部件之間，而使上述第一特徵部件與第二特徵部件可能未直接接觸的實施例。此外，本發明實施例在各例子中可能重複標號及/或字母。此重複是為了達到簡明之目的，而並非用來指出所述之各實施例及/或配置之間的關係。
此外，其中可能用到與空間相對用詞，例如「在…下方」、「下方」、「較低的」、「上方」、「較高的」及類似的用詞，這些空間相對用詞係為了便於描述圖示中一個(些)元件或特徵部件與另一個(些)元件或特徵部件之間的關係，這些空間相對用詞包括使用中或操作中的裝置之不同方位，以及圖式中所描述的方位。當裝置被轉向不同方位時(旋轉90度或其他方位)，則其中所使用的空間相對形容詞也將依轉向後的方位來解釋。應理解的是，在所述方法的其他實施例中，可於所述方法之前、之中與之後提供額外的操作步驟，且一些所述之操作步驟可被取代或省略。
其他特徵部件與製程亦可被包括於本發明實施例中。舉例而言，可加入檢測結構以輔助3D封裝或3D積體電路裝置之驗證測試。舉例而言，檢測結構可包括形成於重分佈層中或基板上的測試墊(上述重分佈層或基板使得3D封裝或3D積體電路可被測試)、探針及/或探針卡(probe cards)之使用、以及類似之元件。可對中間結構及最終結構進行驗證測試。此外，於此所揭露的結構與方法可以與測試方法結合使用，其包括已知合格晶粒(know good dies)之中間驗證以增加良率並降低成本。
第1A-1M圖係為根據一些實施例之形成晶片封裝結構之製程之各階段的剖面圖。根據一些實施例，如第1A圖所示，提供基板110。在一些實施例中，基板110係為晶圓。根據一些實施例，基板110亦可稱為載體基板。根據一些實施例，基板110包括半導體結構112、裝置114、重分佈層116以及導電墊118。
根據一些實施例，半導體結構112具有表面112a。在一些實施例中，半導體結構112係由元素半導體材料形成，其包括單晶、多晶或非晶(amorphous)結構中的矽或鍺。
在一些其他的實施例中，半導體結構112係由化合物半導體(例如:碳化矽(silicon carbide)、砷化鎵(gallium arsenide)、磷化鎵(gallium phosphide)、磷化銦(indium phosphide)、或砷化銦(indium arsenide))、合金半導體(例如:SiGe或GaAsP)、或上述之組合形成。半導體結構112亦可包括多層半導體、絕緣層上半導體(semiconductor on insulator (SOI)，例如:絕緣層上矽或絕緣層上鍺)、或上述之組合。
根據一些實施例，裝置114包括主動裝置114a及/或被動裝置114b。主動裝置114a可包括形成於表面112a的電晶體。根據一些實施例，被動裝置114b係形成於半導體結構112之中或之上。被動裝置114b包括電阻器、電容器或其他適當之被動裝置。
根據一些實施例，重分佈層116係形成於半導體結構112與裝置114之上。根據一些實施例，導電墊118係形成於重分佈層116之上。根據一些實施例，重分佈層116包括介電層116a、線路層116b以及導孔(conductive vias)116c。根據一些實施例，介電層116a係形成於表面112a之上。 根據一些實施例，線路層116b係形成於介電層116a中。
如第1A圖所示，根據一些實施例，導孔116c於不同的線路層116b之間以及線路層116b與導電墊118之間提供電性連接。根據一些實施例，裝置114經由線路層116b與導孔116c電性連接至導電墊118。
根據一些實施例，介電層116a係由含氧材料(例如:氧化矽)或其他適當之絕緣材料形成。根據一些實施例，線路層116b、導孔116c以及導電墊118係由導電材料形成，上述導電材料可例如為金屬(例如:鋁、銅或鎢)或合金。
根據一些實施例，如第1B圖所示，於重分佈層116之上形成罩幕層120。根據一些實施例，罩幕層120覆蓋導電墊118。根據一些實施例，罩幕層120具有溝槽122。根據一些實施例，溝槽122穿過罩幕層120且暴露出其下方之重分佈層116。
根據一些實施例，溝槽122暴露出其下方之介電層116a。根據一些實施例，溝槽122為環形(ring shape)。根據一些實施例，溝槽122連續地圍繞罩幕層120之一部分124。根據一些實施例，罩幕層120係由高分子材料形成，例如:光阻材料。根據一些實施例，使用塗布製程以及微影製程形成罩幕層120。
根據一些實施例，如第1C圖所示，經由溝槽122移除介電層116a的一部分。根據一些實施例，上述移除製程於介電層116a中形成校準溝槽(alignment trench)116t。根據一些實施例，校準溝槽 116t圍繞重分佈層116之接合部分116d。
根據一些實施例，校準溝槽116t連續地圍繞整個接合部分116d。根據一些實施例，校準溝槽116t部分地暴露出線路層116b。根據一些實施例，上述移除製程包括蝕刻製程(例如:乾式蝕刻製程)。
根據一些實施例，如第1D圖所示，移除罩幕層120。根據一些實施例上述移除製程包括蝕刻製程。根據一些實施例，接合部分116d之側壁 S1形成校準溝槽116t之內側壁。
第1E-1圖係為根據一些實施例之第1E圖之晶片封裝結構的上視圖。根據一些實施例，第1E圖係沿著第1E-1圖中的截面線(sectional line)1E-1E繪示出晶片封裝結構的剖面圖。
根據一些實施例，如第1E圖與第1E-1圖所示，於接合部分116d之上形成液相層 130。根據一些實施例，可經由在接合部分116d之上分配(dispensing)一滴液體(或數滴液體)來形成液相層130。根據一些實施例，校準溝槽116t連續地圍繞整個接合部分116d與液相層130。
根據一些實施例，液相層130未形成於校準溝槽116t中。根據一些實施例，液相層130係由水形成。在一些其他的實施例中，液相層130係由乙醇(alcohol)、丙醇(propyl alcohol)、或其他適當之具有良好揮發性(volatility)與良好表面張力之液體形成。
根據一些實施例，接合部分116d具有寬度W1與長度L1。根據一些實施例，寬度W1為約3000μm至約7000μm。根據一些實施例，長度L1為約3000μm至約7000μm。
根據一些實施例，接合部分116d具有頂表面TS。在一些實施例中，液相層130之體積與頂表面 TS之表面面積的比值為約1 μL/cm2 至約40 μL/cm2 。在一些實施例中，液相層130之體積與頂表面TS之表面面積的比值為約2 μL/cm2 至約20 μL/cm2 。根據一些實施例，液相層130具有寬度W11。在一些實施例中，寬度 W11與寬度 W1的比值為約0.1至約0.5。在一些實施例中，寬度 W11與寬度 W1的比值為約0.2至約0.25。
根據一些實施例，如第1F圖所示，提供晶片結構140。根據一些實施例，晶片結構140包括半導體結構142、裝置144、重分佈層 146以及導電墊148。根據一些實施例，半導體結構142具有表面142a。在一些實施例中，半導體結構142係由元素半導體材料形成，其包括單晶、多晶或非晶結構中的矽或鍺。
在一些其他的實施例中，半導體結構142係由化合物半導體(例如:碳化矽、砷化鎵、磷化鎵、磷化銦、或砷化銦)、合金半導體(例如:SiGe或GaAsP)、或上述之組合形成。半導體結構142亦可包括多層半導體、絕緣層上半導體(例如:絕緣層上矽或絕緣層上鍺)、或上述之組合。
根據一些實施例，裝置144包括主動裝置144a及/或被動裝置144b。主動裝置144a可包括形成於表面142a的電晶體。根據一些實施例，被動裝置144b係形成於半導體結構142之中或之上。被動裝置144b包括電阻器、電容器或其他適當之被動裝置。
根據一些實施例，重分佈層146係形成於半導體結構142與裝置144之上。根據一些實施例，導電墊148係形成於重分佈層146之上。根據一些實施例，於晶圓上進行切割製程以將晶圓切割成數個晶片結構140。根據一些實施例，切割製程包括電漿蝕刻製程或隱形切割製程(stealth dicing process)。在一些實施例中，重分佈層 146之側壁S2與半導體結構142之側壁S3大抵上共平面。
根據一些實施例，重分佈層146包括介電層146a、線路層146b以及導孔146c。根據一些實施例，介電層146a係形成於表面142a之上。根據一些實施例，線路層146b係形成於介電層146a中。
根據一些實施例，導孔146c於不同的線路層146b之間以及線路層146b與導電墊148之間提供電性連接。根據一些實施例，裝置144經由線路層146b與導孔146c電性連接至導電墊148。
根據一些實施例，介電層146a係由含氧材料(例如:氧化矽)或其他適當之絕緣材料形成。根據一些實施例，線路層146b、導孔146c以及導電墊148係由導電材料形成，上述導電材料可例如為金屬(例如:鋁、銅或鎢)或合金。
第1G-1圖係為根據一些實施例之第1G圖之晶片封裝結構的上視圖。根據一些實施例，第1G圖係沿著第1G-1圖中的截面線1G-1G繪示出晶片封裝結構的剖面圖。
根據一些實施例，如第1G圖與第1G-1圖所示，於液相層130上設置晶片結構140。根據一些實施例，重分佈層146係位於導體結構142與液相層130之間。根據一些實施例，重分佈層146係位於半導體結構142與接合部分116d之間。
根據一些實施例，液相層130之表面張力幫助晶片結構140與接合部分116d對準。因此，根據一些實施例，晶片結構140以自對準(self-aligned)之方式與接合部分116d對準。因此，根據一些實施例，經由液相層130而大幅增進晶片結構140與接合部分116d之間的對準精度。因此，增進了良率，且可大幅增加製程容許範圍(process window)。因此，相較於使用精度(accuracy)高且產出量(throughput)低的處理儀器，可使用精度低且產出量高的處理儀器進行處理製程。因此，增進了產出量。
根據一些實施例，晶片結構140具有面向接合部分116d的接合表面141。根據一些實施例，接合表面141直接接觸液相層130。根據一些實施例，接合表面141(或重分佈層146)與接合部分116d具有相同的形狀(例如:矩形)。根據一些實施例，接合表面141(或重分佈層146)與接合部分116d的形狀非圓形(non-circular shape)，因此晶片結構140無法於液相層130之上自由旋轉。因此，根據一些實施例，非圓形的形狀幫助接合表面141(或重分佈層146)經由液相層130與接合部分116d對準。
在一些實施例中，接合部分116d的寬度W1大抵上等於晶片結構140的寬度W2。根據一些實施例，用語“大抵上等於”表示寬度W1與寬度W2之間的差異在寬度W1與寬度W2之間之平均值的0.05%以內。上述差異可能是由製程所造成。根據一些實施例，寬度W2為約3000μm至約7000μm。
在一些實施例中，接合部分116d之長度L1大抵上等於晶片結構140之長度 L2。根據一些實施例，用語“大抵上等於”表示長度L1與長度L2之間的差異在長度L1與長度L2之間之平均值的0.05%以內。上述差異可能是由製程所造成。根據一些實施例，長度L2可為約3000μm至約7000μm。
根據一些實施例，如第1H圖所示，將液相層130蒸發。根據一些實施例，在將液相層130蒸發(evaporate)之後，晶片結構140直接接觸接合部分116d。根據一些實施例，重分佈層146直接接觸接合部分116d。
在一些實施例中，接合部分116d之側壁S1與重分佈層146之側壁S2大抵上共平面。在一些實施例中，側壁S1與S2以及半導體結構142之側壁S3大抵上共平面。根據一些實施例，重分佈層146具有寬度W2，其大抵上等於接合部分116d之寬度W1。
根據一些實施例，晶片結構140之介電層146a直接接觸且接合至重分佈層116之介電層116a。根據一些實施例，導電墊148各自直接位於導電墊118之上。根據一些實施例，導電墊148各自直接接觸且接合至導電墊118。
根據一些實施例，於室溫下將液相層130蒸發。根據一些實施例，在將液相層130蒸發之後，在約140℃至約200℃的溫度下進行退火製程約1小時至約5小時以增進介電層116a與介電層146a之間的接合強度。
根據一些實施例，在將液相層130蒸發之後，在約170℃至約400℃的溫度下進行退火製程約50分鐘至約2小時以增進導電墊118與導電墊148之間的接合強度。
根據一些實施例，校準溝槽116t具有寬度W3與深度D1。根據一些實施例，寬度W3為約1μm至約100μm。根據一些實施例，寬度W3可為約10μm至約100μm。根據一些實施例，深度D1為約0.5μm至約100μm。根據一些實施例，深度D1為約3μm至約100μm。
在將晶片結構140接合至接合部分116d之後，可於晶片結構140上進行電測試(electrical test)。根據一些實施例，電測試亦可稱為已知合格晶粒測試(known good die (KGD) test)。若晶片結構140未通過電測試，可以另一晶片結構(未繪示於圖中)取代晶片結構140。根據一些實施例，此晶片結構(未繪示於圖中)可經由第1G-1H圖的步驟接合至接合部分116d。根據一些實施例，此晶片結構(未繪示於圖中)具有與晶片結構140相同的結構。
根據一些實施例，如第1I圖所示，於重分佈層116之上形成保護層150以圍繞晶片結構140。根據一些實施例，校準溝槽116t被保護層150填充。根據一些實施例，校準溝槽116t中的保護層150圍繞接合部分116d。根據一些實施例，保護層150係由絕緣材料形成，例如:含氧材料(例如:氧化矽)。
根據一些實施例，如第1J圖所示，部分地移除保護層150以於保護層150中形成貫穿孔152。根據一些實施例，貫穿孔152穿過保護層150且延伸至校準溝槽116t中。根據一些實施例，貫穿孔152部分地暴露出線路層116b。根據一些實施例，上述移除製程包括蝕刻製程(例如:乾式蝕刻製程)。
如第1K圖所示，根據一些實施例，於貫穿孔152中形成導孔結構160。根據一些實施例，導孔結構160穿過保護層150。根據一些實施例，導孔結構160電性連接至重分佈層116之線路層116b。根據一些實施例，導孔結構160穿過重分佈層116之校準溝槽116t中之保護層150之部分。
根據一些實施例，如第1L圖所示，於晶片結構140、保護層150與導孔結構160之上形成重分佈層170。根據一些實施例，重分佈層170包括介電層172、線路層174以及導孔176。根據一些實施例，線路層174係形成於介電層172中。
根據一些實施例，導孔176於不同線路層174之間提供電性連接。根據一些實施例，介電層172係由含氧材料(例如:氧化矽)或其他適當之絕緣材料形成。根據一些實施例，線路層174與導孔176係由導電材料形成，例如:金屬(例如:鋁、銅或鎢)或合金。
根據一些實施例，如第1L圖所示，於重分佈層170之上形成導電墊180。根據一些實施例，導電墊180電性連接至線路層174。根據一些實施例，導電墊180係由導電材料形成，例如:金屬(例如:鋁、銅或鎢)或合金。
根據一些實施例，如第1L圖所示，於各導電墊180之上形成導電凸塊190。根據一些實施例，導電凸塊190係由導電材料形成，例如:焊接材料(例如:錫(tin))。
根據一些實施例，如第1L圖與第1M圖所示，進行切割製程以沿著切割線SC切穿(cut through)重分佈層170、保護層150與基板110，以形成晶片封裝結構100。為了簡明起見，第1M圖僅繪示出數個晶片封裝結構100之一者。
第2圖係為根據一些實施例之晶片封裝結構200的剖面圖。根據一些實施例，如第2圖所示，晶片封裝結構200類似於第1M圖之晶片封裝結構100，除了晶片封裝結構200更包括晶片結構140a以及重分佈層116之接合部分116e。
根據一些實施例，晶片結構140a接合至接合部分116e。根據一些實施例，晶片結構140a相同或類似於晶片結構140。晶片結構140與晶片結構140a具有相同或不同的寬度。根據一些實施例，接合部分116e相同或類似於接合部分116d。接合部分116d與接合部分116e具有相同或不同的寬度。
用來形成晶片封裝結構200的製程與材料可類似或相同於前述用來形成晶片封裝結構100的製程與材料。
第3圖係為根據一些實施例之晶片封裝結構300的剖面圖。根據一些實施例，如第3圖所示，晶片封裝結構300類似於第1M圖之晶片封裝結構100，除了晶片封裝結構300更包括導孔結構310。
根據一些實施例，導孔結構 310穿過半導體結構142且延伸至介電層146a中以電性連接至線路層146b。根據一些實施例，導孔結構310將線路層174電性連接至線路層146b。
根據一些實施例，導孔結構310之形成包括:在形成重分佈層170之前部分地移除半導體結構142與介電層146a以於半導體結構142與介電層146a中形成貫穿孔142b，以及於貫穿孔142b中形成導孔結構 310，其中貫穿孔142b穿過半導體結構142且延伸至介電層146a中。
用來形成晶片封裝結構300的製程與材料可類似或相同於前述用來形成晶片封裝結構100的製程與材料。
第4圖係為根據一些實施例之晶片封裝結構400的剖面圖。根據一些實施例，如第4圖所示，晶片封裝結構400類似於第1M圖之晶片封裝結構100，除了晶片封裝結構400之晶片結構140之重分佈層146具有第一部分P1以及第二部分P2，且第一部分P1比第二部分P2狹窄。
根據一些實施例，第二部分P2位於第一部分P1與半導體結構142之間。根據一些實施例，第一部分P1直接接觸接合部分116d。根據一些實施例，第一部分P1亦可稱為接合部分。根據一些實施例，第一部分P1之寬度W2大抵上等於接合部分116d之寬度W1。
根據一些實施例，用語“大抵上等於”表示寬度W1與寬度W2之間的差異在寬度W1與寬度W2之間之平均值的0.05%以內。上述差異可能是由製程所造成。根據一些實施例，第二部分P2具有寬度W4。根據一些實施例，寬度W2與寬度W4之間的差異可為約1μm至約50μm。根據一些實施例，寬度W2與寬度W4之間的差異可為約10μm至約30μm。根據一些實施例，寬度W4大於寬度W1或寬度W2。
根據一些實施例，晶片結構140之形成包括:於晶圓之上形成重分佈層，於重分佈層上進行微影製程與蝕刻製程以於重分佈層中形成溝槽(其中溝槽圍繞重分佈層之第一部分，且重分佈層之第二部分位於溝槽與第一部分之下)，以及進行晶圓切割製程(dicing process或cutting process)以沿著溝槽切割晶圓以及第二部分(其中晶圓與第二部分被切割成晶片結構140)。根據一些實施例，晶圓切割製程包括使用砂輪刀片(abrasive blade)。相較於以電漿蝕刻製程達成的晶圓切割製程，以使用砂輪刀片達成的晶圓切割製程具有較低的製程成本。
根據一些實施例，由於第一部分P1是以微影與蝕刻製程定義出，微影與蝕刻製程之製程精度高於使用砂輪刀片之製程之精度，因此第一部分P1的寬度W2精確地等於接合部分116d之寬度W1。
用來形成晶片封裝結構400的製程與材料可類似或相同於前述用來形成晶片封裝結構100的製程與材料。
第5圖係為根據一些實施例之晶片封裝結構500的剖面圖。根據一些實施例，如第5圖所示，晶片封裝結構500類似於第4圖之晶片封裝結構400，除了晶片封裝結構500更包括晶片結構140a以及重分佈層116之接合部分116e。
根據一些實施例，晶片結構140a被接合至接合部分116e。根據一些實施例，晶片結構140a相同或類似於晶片結構140。根據一些實施例，接合部分116e相同或類似於接合部分116d。
用來形成晶片封裝結構500的製程與材料可類似或相同於前述用來形成晶片封裝結構100與400的製程與材料。
第6圖係為根據一些實施例之晶片封裝結構600的剖面圖。根據一些實施例，如第6圖所示，晶片封裝結構600類似於第4圖之晶片封裝結構400，除了晶片封裝結構600更包括導孔結構610。
根據一些實施例，導孔結構610穿過半導體結構142且延伸至介電層146a中以電性連接至線路層146b。根據一些實施例，導孔結構610將線路層174電性連接至線路層146b。
根據一些實施例，導孔結構610之形成包括:在形成重分佈層170之前部分地移除半導體結構142與介電層146a以於半導體結構142與介電層146a中形成貫穿孔142b(其中貫穿孔142b穿過半導體結構142且延伸至介電層146a中)，以及於貫穿孔142b中形成導孔結構610。根據一些實施例，導孔結構610係由導電材料形成，例如:金屬(例如:鋁、銅或鎢)或合金。
用來形成晶片封裝結構600的製程與材料可類似或相同於前述用來形成晶片封裝結構100與400的製程與材料。
第7A-7C圖係為根據一些實施例之形成晶片封裝結構之製程之各階段的剖面圖。根據一些實施例，如第7A圖所示，在1F圖的步驟之後，於液相層130上設置晶片結構140。根據一些實施例，半導體結構142位於重分佈層146與液相層130之間。
根據一些實施例，如第7B圖所示，將液相層130蒸發。根據一些實施例，在將液相層130蒸發之後，晶片結構140直接接觸且接合至接合部分116d。根據一些實施例，半導體結構142直接接觸接合部分116d。
在一些實施例中，接合部分116d之側壁S1與半導體結構142之側壁S3大抵上共平面。在一些實施例中，重分佈層146之側壁S2與側壁S1及S3大抵上共平面。根據一些實施例，半導體結構142具有寬度W2，寬度W2大抵上等於接合部分116d之寬度W1。根據一些實施例，半導體結構142直接接觸且接合至重分佈層116之介電層116a。
根據一些實施例，如第7C圖所示，進行第1I-1M圖之步驟以形成晶片封裝結構700。為了簡明起見，第7C圖僅繪示出數個晶片封裝結構700之一者。
用來形成晶片封裝結構700的材料可類似或相同於前述用來形成晶片封裝結構100的材料。.
第8圖係為根據一些實施例之晶片封裝結構800的剖面圖。根據一些實施例，如第 8圖所示，晶片封裝結構800類似於第7C圖之晶片封裝結構700，除了晶片封裝結構800更包括晶片結構140a以及重分佈層116之接合部分116e。
根據一些實施例，晶片結構140a被接合至接合部分116e。根據一些實施例，晶片結構140a相同或類似於晶片結構140。根據一些實施例，接合部分116e相同或類似於接合部分116d。
用來形成晶片封裝結構800的製程與材料可類似或相同於前述用來形成晶片封裝結構100與700的製程與材料。
根據一些實施例，提供一種晶片封裝結構及其形成方法。上述方法 (用來形成晶片封裝結構)於重分佈層之接合部分之上形成液相層。接合部分被校準溝槽圍繞。接著，於液相層之上設置晶片結構。晶片結構經由晶片結構與接合部分之間之液相層的表面張力以自對準之方式對準於接合部分。因此，液相層增進了晶片結構與接合部分之間的對準精度。接下來，將液相層蒸發，且晶片結構接合至接合部分。
根據一些實施例，提供一種晶片封裝結構之形成方法。上述方法包括部分地移除第一重分佈層以於上述第一重分佈層中形成校準溝槽。上述校準溝槽圍繞上述第一重分佈層之接合部分。上述方法包括於上述接合部分之上形成液相層。上述方法包括於上述液相層之上設置晶片結構。上述接合部分之第一寬度大抵上等於上述晶片結構之第二寬度。上述方法包括將上述液相層蒸發。在將上述液相層蒸發之後上述晶片結構直接接觸上述接合部分。
在一些實施例中，上述液相層係由水所形成。
在一些實施例中，在部分地移除上述第一重分佈層以於上述第一重分佈層中形成上述校準溝槽的步驟之前，上述方法亦包括於基板之上形成上述第一重分佈層。
在一些實施例中，上述第一接合部分的第一長度大抵上等於上述晶片結構的第二長度。
在一些實施例中，上述晶片結構包括基板以及位於上述基板之上的第二重分佈層，在將上述液相層蒸發之後上述第二重分佈層直接接觸上述第一接合部分，且上述第二重分佈層具有上述第二寬度。
在一些實施例中，上述晶片結構包括基板以及位於上述基板之上的第二重分佈層，上述第二重分佈層具有第二接合部分以及上述第二接合部分與上述基板之間的一部分，上述第二接合部分比上述部分窄，上述第二接合部分具有上述第二寬度，且在將上述液相層蒸發之後上述第二接合部分直接接觸上述第一接合部分。
在一些實施例中，上述晶片結構包括基板以及位於上述基板之上的第二重分佈層，在將上述液相層蒸發之後上述基板直接接觸上述第一接合部分，且上述基板具有上述第二寬度。
在一些實施例中，上述方法亦包括在將上述液相層蒸發之後於上述第一重分佈層之上形成保護層以圍繞上述晶片結構，上述校準溝槽被上述保護層填充。
在一些實施例中，上述方法亦包括在形成上述保護層之後部分地移除上述保護層以於上述保護層中形成貫穿孔，並於上述貫穿孔中形成導孔結構，上述貫穿孔穿過上述保護層且延伸至上述校準溝槽中。
在一些實施例中，上述晶片結構包括基板以及位於上述基板之上的第二重分佈層，在將上述液相層蒸發之後上述第二重分佈層直接接觸上述第一接合部分，且上述方法亦包括在形成上述保護層之後部分地移除上述基板以於上述基板中形成貫穿孔，並於上述貫穿孔中形成導孔結構，上述貫穿孔穿過上述基板且上述導孔結構電性連接至上述第二重分佈層。
根據一些實施例，提供一種晶片封裝結構之形成方法。上述方法包括部分地移除載體基板以於載體基板中形成校準溝槽。校準溝槽圍繞載體基板之接合部分。上述方法包括於接合部分之上形成液相層。上述方法包括於液相層之上設置晶片結構。晶片結構與接合部分具有相同的形狀。上述方法包括將液相層蒸發。在將液相層蒸發之後晶片結構接合至接合部分。
在一些實施例中，上述接合部分的第一寬度大抵上等於上述晶片結構的第二寬度。
在一些實施例中，上述接合部分的第一長度大抵上等於上述晶片結構的第二長度。
在一些實施例中，上述晶片結構包括基板以及位於上述基板之上的第二重分佈層。在將上述液相層蒸發之後上述基板直接接觸上述接合部分。
在一些實施例中，上述方法亦包括在將上述液相層蒸發的步驟之後於上述載體基板之上形成保護層以圍繞上述晶片結構。上述保護層填充上述校準溝槽。
根據一些實施例，提供一種晶片封裝結構。晶片封裝結構包括具有接合部分的第一重分佈層。晶片封裝結構包括接合至接合部分的晶片結構。接合部分之第一寬度大抵上等於晶片結構之第二寬度。晶片封裝結構包括保護層。保護層位於第一重分佈層之上且圍繞晶片結構。保護層的一部分延伸至第一重分佈層中且圍繞接合部分。
在一些實施例中，上述接合部分的第一側壁與上述晶片結構的第二側壁大抵上共平面。
在一些實施例中，上述晶片結構包括基板以及第二重分佈層。上述第二重分佈層位於上述基板與上述接合部分之間。上述第二重分佈層直接接觸上述接合部分，且上述第二重分佈層具有上述第二寬度。
在一些實施例中，上述晶片結構包括基板以及第二重分佈層。上述第二重分佈層位於上述基板之上。上述基板直接接觸上述接合部分，且上述基板具有上述第二寬度。
在一些實施例中，上述晶片封裝結構亦包括導孔結構。上述導孔結構穿過上述保護層且電性連接至上述第一重分佈層。上述導孔結構穿過上述第一重分佈層中的上述保護層的上述部分。
前述內文概述了許多實施例之特徵部件，使本技術領域中具有通常知識者可以更加了解本發明實施例之各層面。本技術領域中具有通常知識者應可理解，且可輕易地以本發明實施例為基礎來設計或修飾其他製程及結構，並以此達到與在此介紹的實施例相同之目的及/或達到與在此介紹的實施例相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本發明實施例的發明精神與範圍。在不背離本發明實施例的發明精神與範圍之前提下，可對本發明實施例進行各種改變、置換或修改。
100、200、300、400、500、600、700、800‧‧‧晶片封裝結構； 110‧‧‧基板； 112‧‧‧半導體結構； 112a‧‧‧半導體結構的表面； 114‧‧‧裝置； 114a‧‧‧主動裝置； 114b‧‧‧被動裝置； 116‧‧‧重分佈層； 116a‧‧‧介電層； 116b‧‧‧線路層； 116c‧‧‧導孔； 116d、116e‧‧‧接合部分； 116t‧‧‧校準溝槽； 118‧‧‧導電墊； 120‧‧‧罩幕層； 122‧‧‧溝槽； 124‧‧‧罩幕層的一部分； 130‧‧‧液相層； 140、140a‧‧‧晶片結構； 141‧‧‧接合表面； 142‧‧‧半導體結構； 142a‧‧‧半導體結構的表面； 142b‧‧‧貫穿孔； 144‧‧‧裝置； 144a‧‧‧主動裝置； 144b‧‧‧被動裝置； 146‧‧‧重分佈層； 146a‧‧‧介電層； 146b‧‧‧線路層； 146c‧‧‧導孔； 148‧‧‧導電墊； 150‧‧‧保護層； 152‧‧‧貫穿孔； 160‧‧‧導孔結構； 170‧‧‧重分佈層； 172‧‧‧介電層； 174‧‧‧線路層； 176‧‧‧導孔； 180‧‧‧導電墊； 190‧‧‧導電凸塊； 310‧‧‧導孔結構； 610‧‧‧導孔結構； S1‧‧‧接合部分之側壁； S2‧‧‧重分佈層之側壁； S3‧‧‧半導體結構之側壁； TS‧‧‧接合部分之頂表面； W1‧‧‧接合部分之寬段； W11‧‧‧液相層之寬度； W2‧‧‧晶片結構之寬度； W3‧‧‧校準溝槽之寬度； L1‧‧‧接合部分之長度； L2‧‧‧晶片結構之長度； D1‧‧‧校準溝槽之深度； 1E-1E‧‧‧截面線； 1G-1G‧‧‧截面線； SC‧‧‧切割線； P1‧‧‧重分佈層之第一部分； P2‧‧‧重分佈層之第二部分； W4‧‧‧重分佈層之第二部分之寬度。
以下將配合所附圖式詳述本發明實施例。應注意的是，各種特徵部件並未按照比例繪製且僅用以說明例示。事實上，元件的尺寸可能經放大或縮小，以清楚地說明本發明實施例。 第1A-1M圖係為根據一些實施例之形成晶片封裝結構之製程之各階段的剖面圖。 第1E-1圖係為根據一些實施例之第1E圖之晶片封裝結構的上視圖。 第1G-1圖係為根據一些實施例之第1G圖之晶片封裝結構的上視圖。 第2圖係為根據一些實施例之晶片封裝結構200的剖面圖。 第3圖係為根據一些實施例之晶片封裝結構300的剖面圖。 第4圖係為根據一些實施例之晶片封裝結構400的剖面圖。 第5圖係為根據一些實施例之晶片封裝結構500的剖面圖。 第6圖係為根據一些實施例之晶片封裝結構600的剖面圖。 第7A-7C圖係為根據一些實施例之形成晶片封裝結構之製程之各階段的剖面圖。 第8圖係為根據一些實施例之晶片封裝結構800的剖面圖。
110‧‧‧基板
112‧‧‧半導體結構
116‧‧‧重分佈層
116a‧‧‧介電層
116b‧‧‧線路層
116d‧‧‧接合部分
116t‧‧‧校準溝槽
118‧‧‧導電墊
130‧‧‧液相層
140‧‧‧晶片結構
141‧‧‧接合表面
142‧‧‧半導體結構
146‧‧‧重分佈層
148‧‧‧導電墊
W1‧‧‧接合部分之寬段
W2‧‧‧晶片結構之寬度

Claims (1)

  1. 一種形成晶片封裝結構的方法，包括： 部分地移除一第一重分佈層以於該第一重分佈層中形成一校準溝槽，其中該校準溝槽圍繞該第一重分佈層的一第一接合部分； 於該第一接合部分之上形成一液相層； 於該液相層之上設置一晶片結構，其中該第一接合部分的一第一寬度大抵上等於該晶片結構的一第二寬度；以及 將該液相層蒸發，其中在將該液相層蒸發之後該晶片結構接合至該第一接合部分。
TW108127663A 2018-08-14 2019-08-05 晶片封裝結構之形成方法 TW202010069A (zh)

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