CN110828323A - 芯片封装结构的形成方法 - Google Patents

芯片封装结构的形成方法 Download PDF

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Publication number
CN110828323A
CN110828323A CN201910489767.8A CN201910489767A CN110828323A CN 110828323 A CN110828323 A CN 110828323A CN 201910489767 A CN201910489767 A CN 201910489767A CN 110828323 A CN110828323 A CN 110828323A
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layer
chip
bonding portion
redistribution layer
width
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CN201910489767.8A
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Inventor
董志航
邵栋樑
杨素纯
张耕铭
余振华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN110828323A publication Critical patent/CN110828323A/zh
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Abstract

本公开实施例提供一种芯片封装结构的形成方法。上述方法包括部分地移除第一重分布层以于第一重分布层中形成校准沟槽。校准沟槽围绕第一重分布层的第一接合部分。上述方法包括于第一接合部分之上形成液相层、于液相层之上设置芯片结构。第一接合部分的第一宽度大抵上等于芯片结构的第二宽度。上述方法包括将液相层蒸发。在将液相层蒸发之后芯片结构接合至第一接合部分。

Description

芯片封装结构的形成方法
技术领域
本公开实施例有关于一种芯片封装结构及其形成方法，且特别有关于一种将芯片结构接合至重分布层(redistribution layer)的方法。
背景技术
半导体装置被使用于各种电子装置中，例如：个人电脑、手机、数码相机以及其他电子设备。一般而言，在半导体基板上按序沉积绝缘或介电层、导电层以及半导体层，并且以微影的方式将各材料层图案化以于其上形成电路组件及元件，借此制造半导体装置。
半导体工业经由持续降低最小特征部件尺寸持续精进各电子组件(例如：晶体管、二极管、电阻器、电容器等)的集积密度(integration density)，这使得更多组件可被整合至一给定面积。在一些应用中，这些较小的电子组件亦使用较小的封装，上述较小的封装占有面积较小或高度较低。
已发展新的封装技术以增半导体装置的密度与功能。这些相对较新的半导体装置封装技术面临制造上的挑战。
发明内容
本公开实施例包括一种芯片封装结构的形成方法。上述方法包括部分地移除第一重分布层以于上述第一重分布层中形成校准沟槽。上述校准沟槽围绕上述第一重分布层的第一接合部分。上述方法包括于上述第一接合部分之上形成液相层、于上述液相层之上设置芯片结构。上述第一接合部分的第一宽度大抵上等于上述芯片结构的第二宽度。上述方法包括将上述液相层蒸发。在将上述液相层蒸发的步骤之后上述芯片结构接合至上述第一接合部分。
本公开实施例亦包括一种形成芯片封装结构的方法。上述方法包括部分地移除载体基板以于上述载体基板中形成校准沟槽。上述校准沟槽围绕上述载体基板的接合部分。上述方法亦包括于上述接合部分之上形成液相层、于上述液相层之上设置芯片结构。上述芯片结构与上述接合部分具有相同的形状。上述方法亦包括将上述液相层蒸发。在将上述液相层蒸发的步骤之后上述芯片结构接合至上述接合部分。
本公开实施例又包括一种芯片封装结构。上述芯片封装结构包括第一重分布层、芯片结构以及保护层。上述第一重分布层具有接合部分。上述芯片结构接合至上述接合部分，上述接合部分的第一宽度大抵上等于上述芯片结构的第二宽度。上述保护层位于上述第一重分布层之上且围绕上述芯片结构。上述保护层的一部分延伸至上述第一重分布层中且围绕上述接合部分。
附图说明
以下将配合附图详述本公开实施例。应注意的是，各种特征部件并未按照比例绘制且仅用以说明例示。事实上，元件的尺寸可能经放大或缩小，以清楚地说明本公开实施例。
图1A-1M为根据一些实施例的形成芯片封装结构的工艺的各阶段的剖面图。
图1E-1为根据一些实施例的图1E的芯片封装结构的上视图。
图1G-1为根据一些实施例的图1G的芯片封装结构的上视图。
图2为根据一些实施例的芯片封装结构200的剖面图。
图3为根据一些实施例的芯片封装结构300的剖面图。
图4为根据一些实施例的芯片封装结构400的剖面图。
图5为根据一些实施例的芯片封装结构500的剖面图。
图6为根据一些实施例的芯片封装结构600的剖面图。
图7A-7C为根据一些实施例的形成芯片封装结构的工艺的各阶段的剖面图。
图8为根据一些实施例的芯片封装结构800的剖面图。
附图标记说明：
100、200、300、400、500、600、700、800～芯片封装结构；
110～基板；
112～半导体结构；
112a～半导体结构的表面；
114～装置；
114a～主动装置；
114b～被动装置；
116～重分布层；
116a～介电层；
116b～线路层；
116c～导孔；
116d、116e～接合部分；
116t～校准沟槽；
118～导电垫；
120～掩模层；
122～沟槽；
124～掩模层的一部分；
130～液相层；
140、140a～芯片结构；
141～接合表面；
142～半导体结构；
142a～半导体结构的表面；
142b～贯穿孔；
144～装置；
144a～主动装置；
144b～被动装置；
146～重分布层；
146a～介电层；
146b～线路层；
146c～导孔；
148～导电垫；
150～保护层；
152～贯穿孔；
160～导孔结构；
170～重分布层；
172～介电层；
174～线路层；
176～导孔；
180～导电垫；
190～导电凸块；
310～导孔结构；
610～导孔结构；
S1～接合部分的侧壁；
S2～重分布层的侧壁；
S3～半导体结构的侧壁；
TS～接合部分的顶表面；
W1～接合部分的宽段；
W11～液相层的宽度；
W2～芯片结构的宽度；
W3～校准沟槽的宽度；
L1～接合部分的长度；
L2～芯片结构的长度；
D1～校准沟槽的深度；
1E-1E～截面线；
1G-1G～截面线；
SC～切割线；
P1～重分布层的第一部分；
P2～重分布层的第二部分；
W4～重分布层的第二部分的宽度。
具体实施方式
以下的公开内容提供许多不同的实施例或范例以实施本公开的不同特征。以下的公开内容叙述各个构件及其排列方式的特定范例，以简化说明。当然，这些特定的范例并非用以限定。例如，若是本公开实施例叙述了一第一特征部件形成于一第二特征部件之上或上方，即表示其可能包含上述第一特征部件与上述第二特征部件是直接接触的实施例，亦可能包含了有附加特征部件形成于上述第一特征部件与上述第二特征部件之间，而使上述第一特征部件与第二特征部件可能未直接接触的实施例。此外，本公开实施例在各例子中可能重复标号及/或字母。此重复是为了达到简明的目的，而并非用来指出所述的各实施例及/或配置之间的关系。
此外，其中可能用到与空间相对用词，例如「在…下方」、「下方」、「较低的」、「上方」、「较高的」及类似的用词，这些空间相对用词为了便于描述图示中一个(些)元件或特征部件与另一个(些)元件或特征部件之间的关系，这些空间相对用词包括使用中或操作中的装置的不同方位，以及附图中所描述的方位。当装置被转向不同方位时(旋转90度或其他方位)，则其中所使用的空间相对形容词也将依转向后的方位来解释。应理解的是，在所述方法的其他实施例中，可于所述方法之前、之中与之后提供额外的操作步骤，且一些所述的操作步骤可被取代或省略。
其他特征部件与工艺亦可被包括于本公开实施例中。举例而言，可加入检测结构以辅助3D封装或3D集成电路装置的验证测试。举例而言，检测结构可包括形成于重分布层中或基板上的测试垫(上述重分布层或基板使得3D封装或3D集成电路可被测试)、探针及/或探针卡(probe cards)的使用、以及类似的元件。可对中间结构及最终结构进行验证测试。此外，于此所公开的结构与方法可以与测试方法结合使用，其包括已知合格晶粒(knowgood dies)的中间验证以增加良率并降低成本。
图1A-1M为根据一些实施例的形成芯片封装结构的工艺的各阶段的剖面图。根据一些实施例，如图1A所示，提供基板110。在一些实施例中，基板110为晶圆。根据一些实施例，基板110亦可称为载体基板。根据一些实施例，基板110包括半导体结构112、装置114、重分布层116以及导电垫118。
根据一些实施例，半导体结构112具有表面112a。在一些实施例中，半导体结构112是由元素半导体材料形成，其包括单晶、多晶或非晶(amorphous)结构中的硅或锗。
在一些其他的实施例中，半导体结构112是由化合物半导体(例如：碳化硅(silicon carbide)、砷化镓(gallium arsenide)、磷化镓(gallium phosphide)、磷化铟(indium phosphide)、或砷化铟(indium arsenide))、合金半导体(例如：SiGe或GaAsP)、或上述的组合形成。半导体结构112亦可包括多层半导体、绝缘层上半导体(semiconductoron insulator(SOI)，例如：绝缘层上硅或绝缘层上锗)、或上述的组合。
根据一些实施例，装置114包括主动装置114a及/或被动装置114b。主动装置114a可包括形成于表面112a的晶体管。根据一些实施例，被动装置114b是形成于半导体结构112之中或之上。被动装置114b包括电阻器、电容器或其他适当的被动装置。
根据一些实施例，重分布层116形成于半导体结构112与装置114之上。根据一些实施例，导电垫118形成于重分布层116之上。根据一些实施例，重分布层116包括介电层116a、线路层116b以及导孔(conductive vias)116c。根据一些实施例，介电层116a形成于表面112a之上。根据一些实施例，线路层116b形成于介电层116a中。
如图1A所示，根据一些实施例，导孔116c于不同的线路层116b之间以及线路层116b与导电垫118之间提供电性连接。根据一些实施例，装置114经由线路层116b与导孔116c电性连接至导电垫118。
根据一些实施例，介电层116a由含氧材料(例如：氧化硅)或其他适当的绝缘材料形成。根据一些实施例，线路层116b、导孔116c以及导电垫118由导电材料形成，上述导电材料可例如为金属(例如：铝、铜或钨)或合金。
根据一些实施例，如图1B所示，于重分布层116之上形成掩模层120。根据一些实施例，掩模层120覆盖导电垫118。根据一些实施例，掩模层120具有沟槽122。根据一些实施例，沟槽122穿过掩模层120且暴露出其下方的重分布层116。
根据一些实施例，沟槽122暴露出其下方的介电层116a。根据一些实施例，沟槽122为环形(ring shape)。根据一些实施例，沟槽122连续地围绕掩模层120的一部分124。根据一些实施例，掩模层120由高分子材料形成，例如：光阻材料。根据一些实施例，使用涂布工艺以及微影工艺形成掩模层120。
根据一些实施例，如图1C所示，经由沟槽122移除介电层116a的一部分。根据一些实施例，上述移除工艺于介电层116a中形成校准沟槽(alignment trench)116t。根据一些实施例，校准沟槽116t围绕重分布层116的接合部分116d。
根据一些实施例，校准沟槽116t连续地围绕整个接合部分116d。根据一些实施例，校准沟槽116t部分地暴露出线路层116b。根据一些实施例，上述移除工艺包括蚀刻工艺(例如：干式蚀刻工艺)。
根据一些实施例，如图1D所示，移除掩模层120。根据一些实施例上述移除工艺包括蚀刻工艺。根据一些实施例，接合部分116d的侧壁S1形成校准沟槽116t的内侧壁。
图1E-1为根据一些实施例的图1E的芯片封装结构的上视图。根据一些实施例，图1E是沿着第1E-1图中的截面线(sectional line)1E-1E示出芯片封装结构的剖面图。
根据一些实施例，如图1E与图1E-1所示，于接合部分116d之上形成液相层130。根据一些实施例，可经由在接合部分116d之上分配(dispensing)一滴液体(或数滴液体)来形成液相层130。根据一些实施例，校准沟槽116t连续地围绕整个接合部分116d与液相层130。
根据一些实施例，液相层130未形成于校准沟槽116t中。根据一些实施例，液相层130由水形成。在一些其他的实施例中，液相层130由乙醇(alcohol)、丙醇(propylalcohol)、或其他适当的具有良好挥发性(volatility)与良好表面张力的液体形成。
根据一些实施例，接合部分116d具有宽度W1与长度L1。根据一些实施例，宽度W1为约3000μm至约7000μm。根据一些实施例，长度L1为约3000μm至约7000μm。
根据一些实施例，接合部分116d具有顶表面TS。在一些实施例中，液相层130的体积与顶表面TS的表面面积的比值为约1μL/cm2至约40μL/cm2。在一些实施例中，液相层130的体积与顶表面TS的表面面积的比值为约2μL/cm2至约20μL/cm2。根据一些实施例，液相层130具有宽度W11。在一些实施例中，宽度W11与宽度W1的比值为约0.1至约0.5。在一些实施例中，宽度W11与宽度W1的比值为约0.2至约0.25。
根据一些实施例，如图1F所示，提供芯片结构140。根据一些实施例，芯片结构140包括半导体结构142、装置144、重分布层146以及导电垫148。根据一些实施例，半导体结构142具有表面142a。在一些实施例中，半导体结构142由元素半导体材料形成，其包括单晶、多晶或非晶结构中的硅或锗。
在一些其他的实施例中，半导体结构142由化合物半导体(例如：碳化硅、砷化镓、磷化镓、磷化铟、或砷化铟)、合金半导体(例如：SiGe或GaAsP)、或上述的组合形成。半导体结构142亦可包括多层半导体、绝缘层上半导体(例如：绝缘层上硅或绝缘层上锗)、或上述的组合。
根据一些实施例，装置144包括主动装置144a及/或被动装置144b。主动装置144a可包括形成于表面142a的晶体管。根据一些实施例，被动装置144b形成于半导体结构142之中或之上。被动装置144b包括电阻器、电容器或其他适当的被动装置。
根据一些实施例，重分布层146形成于半导体结构142与装置144之上。根据一些实施例，导电垫148形成于重分布层146之上。根据一些实施例，于晶圆上进行切割工艺以将晶圆切割成数个芯片结构140。根据一些实施例，切割工艺包括等离子体蚀刻工艺或隐形切割工艺(stealth dicing process)。在一些实施例中，重分布层146的侧壁S2与半导体结构142的侧壁S3大抵上共平面。
根据一些实施例，重分布层146包括介电层146a、线路层146b以及导孔146c。根据一些实施例，介电层146a形成于表面142a之上。根据一些实施例，线路层146b形成于介电层146a中。
根据一些实施例，导孔146c于不同的线路层146b之间以及线路层146b与导电垫148之间提供电性连接。根据一些实施例，装置144经由线路层146b与导孔146c电性连接至导电垫148。
根据一些实施例，介电层146a由含氧材料(例如：氧化硅)或其他适当的绝缘材料形成。根据一些实施例，线路层146b、导孔146c以及导电垫148由导电材料形成，上述导电材料可例如为金属(例如：铝、铜或钨)或合金。
图1G-1为根据一些实施例的图1G的芯片封装结构的上视图。根据一些实施例，图1G是沿着图1G-1中的截面线1G-1G示出芯片封装结构的剖面图。
根据一些实施例，如图1G与图1G-1所示，于液相层130上设置芯片结构140。根据一些实施例，重分布层146位于导体结构142与液相层130之间。根据一些实施例，重分布层146位于半导体结构142与接合部分116d之间。
根据一些实施例，液相层130的表面张力帮助芯片结构140与接合部分116d对准。因此，根据一些实施例，芯片结构140以自对准(self-aligned)的方式与接合部分116d对准。因此，根据一些实施例，经由液相层130而大幅增进芯片结构140与接合部分116d之间的对准精度。因此，增进了良率，且可大幅增加工艺容许范围(process window)。因此，相较于使用精度(accuracy)高且产出量(throughput)低的处理仪器，可使用精度低且产出量高的处理仪器进行处理工艺。因此，增进了产出量。
根据一些实施例，芯片结构140具有面向接合部分116d的接合表面141。根据一些实施例，接合表面141直接接触液相层130。根据一些实施例，接合表面141(或重分布层146)与接合部分116d具有相同的形状(例如：矩形)。根据一些实施例，接合表面141(或重分布层146)与接合部分116d的形状非圆形(non-circular shape)，因此芯片结构140无法于液相层130之上自由旋转。因此，根据一些实施例，非圆形的形状帮助接合表面141(或重分布层146)经由液相层130与接合部分116d对准。
在一些实施例中，接合部分116d的宽度W1大抵上等于芯片结构140的宽度W2。根据一些实施例，用语“大抵上等于”表示宽度W1与宽度W2之间的差异在宽度W1与宽度W2之间的平均值的0.05％以内。上述差异可能是由工艺所造成。根据一些实施例，宽度W2为约3000μm至约7000μm。
在一些实施例中，接合部分116d的长度L1大抵上等于芯片结构140的长度L2。根据一些实施例，用语“大抵上等于”表示长度L1与长度L2之间的差异在长度L1与长度L2之间的平均值的0.05％以内。上述差异可能是由工艺所造成。根据一些实施例，长度L2可为约3000μm至约7000μm。
根据一些实施例，如图1H所示，将液相层130蒸发。根据一些实施例，在将液相层130蒸发(evaporate)之后，芯片结构140直接接触接合部分116d。根据一些实施例，重分布层146直接接触接合部分116d。
在一些实施例中，接合部分116d的侧壁S1与重分布层146的侧壁S2大抵上共平面。在一些实施例中，侧壁S1与S2以及半导体结构142的侧壁S3大抵上共平面。根据一些实施例，重分布层146具有宽度W2，其大抵上等于接合部分116d的宽度W1。
根据一些实施例，芯片结构140的介电层146a直接接触且接合至重分布层116的介电层116a。根据一些实施例，导电垫148各自直接位于导电垫118之上。根据一些实施例，导电垫148各自直接接触且接合至导电垫118。
根据一些实施例，于室温下将液相层130蒸发。根据一些实施例，在将液相层130蒸发之后，在约140℃至约200℃的温度下进行退火工艺约1小时至约5小时以增进介电层116a与介电层146a之间的接合强度。
根据一些实施例，在将液相层130蒸发之后，在约170℃至约400℃的温度下进行退火工艺约50分钟至约2小时以增进导电垫118与导电垫148之间的接合强度。
根据一些实施例，校准沟槽116t具有宽度W3与深度D1。根据一些实施例，宽度W3为约1μm至约100μm。根据一些实施例，宽度W3可为约10μm至约100μm。根据一些实施例，深度D1为约0.5μm至约100μm。根据一些实施例，深度D1为约3μm至约100μm。
在将芯片结构140接合至接合部分116d之后，可于芯片结构140上进行电测试(electrical test)。根据一些实施例，电测试亦可称为已知合格晶粒测试(known gooddie(KGD)test)。若芯片结构140未通过电测试，可以另一芯片结构(未示出于图中)取代芯片结构140。根据一些实施例，此芯片结构(未示出于图中)可经由图1G-1H的步骤接合至接合部分116d。根据一些实施例，此芯片结构(未示出于图中)具有与芯片结构140相同的结构。
根据一些实施例，如图1I所示，于重分布层116之上形成保护层150以围绕芯片结构140。根据一些实施例，校准沟槽116t被保护层150填充。根据一些实施例，校准沟槽116t中的保护层150围绕接合部分116d。根据一些实施例，保护层150由绝缘材料形成，例如：含氧材料(例如：氧化硅)。
根据一些实施例，如图1J所示，部分地移除保护层150以于保护层150中形成贯穿孔152。根据一些实施例，贯穿孔152穿过保护层150且延伸至校准沟槽116t中。根据一些实施例，贯穿孔152部分地暴露出线路层116b。根据一些实施例，上述移除工艺包括蚀刻工艺(例如：干式蚀刻工艺)。
如图1K所示，根据一些实施例，于贯穿孔152中形成导孔结构160。根据一些实施例，导孔结构160穿过保护层150。根据一些实施例，导孔结构160电性连接至重分布层116的线路层116b。根据一些实施例，导孔结构160穿过重分布层116的校准沟槽116t中的保护层150的部分。
根据一些实施例，如图1L所示，于芯片结构140、保护层150与导孔结构160之上形成重分布层170。根据一些实施例，重分布层170包括介电层172、线路层174以及导孔176。根据一些实施例，线路层174形成于介电层172中。
根据一些实施例，导孔176于不同线路层174之间提供电性连接。根据一些实施例，介电层172由含氧材料(例如：氧化硅)或其他适当的绝缘材料形成。根据一些实施例，线路层174与导孔176由导电材料形成，例如：金属(例如：铝、铜或钨)或合金。
根据一些实施例，如图1L所示，于重分布层170之上形成导电垫180。根据一些实施例，导电垫180电性连接至线路层174。根据一些实施例，导电垫180由导电材料形成，例如：金属(例如：铝、铜或钨)或合金。
根据一些实施例，如图1L所示，于各导电垫180之上形成导电凸块190。根据一些实施例，导电凸块190由导电材料形成，例如：焊接材料(例如：锡(tin))。
根据一些实施例，如图1L与图1M所示，进行切割工艺以沿着切割线SC切穿(cutthrough)重分布层170、保护层150与基板110，以形成芯片封装结构100。为了简明起见，图1M仅示出数个芯片封装结构100的一者。
图2为根据一些实施例的芯片封装结构200的剖面图。根据一些实施例，如图2所示，芯片封装结构200类似于图1M的芯片封装结构100，除了芯片封装结构200还包括芯片结构140a以及重分布层116的接合部分116e。
根据一些实施例，芯片结构140a接合至接合部分116e。根据一些实施例，芯片结构140a相同或类似于芯片结构140。芯片结构140与芯片结构140a具有相同或不同的宽度。根据一些实施例，接合部分116e相同或类似于接合部分116d。接合部分116d与接合部分116e具有相同或不同的宽度。
用来形成芯片封装结构200的工艺与材料可类似或相同于前述用来形成芯片封装结构100的工艺与材料。
图3为根据一些实施例的芯片封装结构300的剖面图。根据一些实施例，如图3所示，芯片封装结构300类似于图1M的芯片封装结构100，除了芯片封装结构300还包括导孔结构310。
根据一些实施例，导孔结构310穿过半导体结构142且延伸至介电层146a中以电性连接至线路层146b。根据一些实施例，导孔结构310将线路层174电性连接至线路层146b。
根据一些实施例，导孔结构310的形成包括：在形成重分布层170之前部分地移除半导体结构142与介电层146a以于半导体结构142与介电层146a中形成贯穿孔142b，以及于贯穿孔142b中形成导孔结构310，其中贯穿孔142b穿过半导体结构142且延伸至介电层146a中。
用来形成芯片封装结构300的工艺与材料可类似或相同于前述用来形成芯片封装结构100的工艺与材料。
图4为根据一些实施例的芯片封装结构400的剖面图。根据一些实施例，如图4所示，芯片封装结构400类似于图1M的芯片封装结构100，除了芯片封装结构400的芯片结构140的重分布层146具有第一部分P1以及第二部分P2，且第一部分P1比第二部分P2狭窄。
根据一些实施例，第二部分P2位于第一部分P1与半导体结构142之间。根据一些实施例，第一部分P1直接接触接合部分116d。根据一些实施例，第一部分P1亦可称为接合部分。根据一些实施例，第一部分P1的宽度W2大抵上等于接合部分116d的宽度W1。
根据一些实施例，用语“大抵上等于”表示宽度W1与宽度W2之间的差异在宽度W1与宽度W2之间的平均值的0.05％以内。上述差异可能是由工艺所造成。根据一些实施例，第二部分P2具有宽度W4。根据一些实施例，宽度W2与宽度W4之间的差异可为约1μm至约50μm。根据一些实施例，宽度W2与宽度W4之间的差异可为约10μm至约30μm。根据一些实施例，宽度W4大于宽度W1或宽度W2。
根据一些实施例，芯片结构140的形成包括：于晶圆之上形成重分布层，于重分布层上进行微影工艺与蚀刻工艺以于重分布层中形成沟槽(其中沟槽围绕重分布层的第一部分，且重分布层的第二部分位于沟槽与第一部分之下)，以及进行晶圆切割工艺(dicingprocess或cutting process)以沿着沟槽切割晶圆以及第二部分(其中晶圆与第二部分被切割成芯片结构140)。根据一些实施例，晶圆切割工艺包括使用砂轮刀片(abrasiveblade)。相较于以等离子体蚀刻工艺实现的晶圆切割工艺，以使用砂轮刀片实现的晶圆切割工艺具有较低的工艺成本。
根据一些实施例，由于第一部分P1是以微影与蚀刻工艺定义出，微影与蚀刻工艺的工艺精度高于使用砂轮刀片的工艺的精度，因此第一部分P1的宽度W2精确地等于接合部分116d的宽度W1。
用来形成芯片封装结构400的工艺与材料可类似或相同于前述用来形成芯片封装结构100的工艺与材料。
图5为根据一些实施例的芯片封装结构500的剖面图。根据一些实施例，如图5所示，芯片封装结构500类似于图4的芯片封装结构400，除了芯片封装结构500还包括芯片结构140a以及重分布层116的接合部分116e。
根据一些实施例，芯片结构140a被接合至接合部分116e。根据一些实施例，芯片结构140a相同或类似于芯片结构140。根据一些实施例，接合部分116e相同或类似于接合部分116d。
用来形成芯片封装结构500的工艺与材料可类似或相同于前述用来形成芯片封装结构100与400的工艺与材料。
图6为根据一些实施例的芯片封装结构600的剖面图。根据一些实施例，如图6所示，芯片封装结构600类似于图4的芯片封装结构400，除了芯片封装结构600还包括导孔结构610。
根据一些实施例，导孔结构610穿过半导体结构142且延伸至介电层146a中以电性连接至线路层146b。根据一些实施例，导孔结构610将线路层174电性连接至线路层146b。
根据一些实施例，导孔结构610的形成包括：在形成重分布层170之前部分地移除半导体结构142与介电层146a以于半导体结构142与介电层146a中形成贯穿孔142b(其中贯穿孔142b穿过半导体结构142且延伸至介电层146a中)，以及于贯穿孔142b中形成导孔结构610。根据一些实施例，导孔结构610是由导电材料形成，例如：金属(例如：铝、铜或钨)或合金。
用来形成芯片封装结构600的工艺与材料可类似或相同于前述用来形成芯片封装结构100与400的工艺与材料。
图7A-7C为根据一些实施例的形成芯片封装结构的工艺的各阶段的剖面图。根据一些实施例，如图7A所示，在图1F的步骤之后，于液相层130上设置芯片结构140。根据一些实施例，半导体结构142位于重分布层146与液相层130之间。
根据一些实施例，如图7B所示，将液相层130蒸发。根据一些实施例，在将液相层130蒸发之后，芯片结构140直接接触且接合至接合部分116d。根据一些实施例，半导体结构142直接接触接合部分116d。
在一些实施例中，接合部分116d的侧壁S1与半导体结构142的侧壁S3大抵上共平面。在一些实施例中，重分布层146的侧壁S2与侧壁S1及S3大抵上共平面。根据一些实施例，半导体结构142具有宽度W2，宽度W2大抵上等于接合部分116d的宽度W1。根据一些实施例，半导体结构142直接接触且接合至重分布层116的介电层116a。
根据一些实施例，如图7C所示，进行图1I-1M的步骤以形成芯片封装结构700。为了简明起见，图7C仅示出数个芯片封装结构700的一者。
用来形成芯片封装结构700的材料可类似或相同于前述用来形成芯片封装结构100的材料。.
图8为根据一些实施例的芯片封装结构800的剖面图。根据一些实施例，如第8图所示，芯片封装结构800类似于图7C的芯片封装结构700，除了芯片封装结构800还包括芯片结构140a以及重分布层116的接合部分116e。
根据一些实施例，芯片结构140a被接合至接合部分116e。根据一些实施例，芯片结构140a相同或类似于芯片结构140。根据一些实施例，接合部分116e相同或类似于接合部分116d。
用来形成芯片封装结构800的工艺与材料可类似或相同于前述用来形成芯片封装结构100与700的工艺与材料。
根据一些实施例，提供一种芯片封装结构及其形成方法。上述方法(用来形成芯片封装结构)于重分布层的接合部分之上形成液相层。接合部分被校准沟槽围绕。接着，于液相层之上设置芯片结构。芯片结构经由芯片结构与接合部分之间的液相层的表面张力以自对准的方式对准于接合部分。因此，液相层增进了芯片结构与接合部分之间的对准精度。接下来，将液相层蒸发，且芯片结构接合至接合部分。
根据一些实施例，提供一种芯片封装结构的形成方法。上述方法包括部分地移除第一重分布层以于上述第一重分布层中形成校准沟槽。上述校准沟槽围绕上述第一重分布层的接合部分。上述方法包括于上述接合部分之上形成液相层。上述方法包括于上述液相层之上设置芯片结构。上述接合部分的第一宽度大抵上等于上述芯片结构的第二宽度。上述方法包括将上述液相层蒸发。在将上述液相层蒸发之后上述芯片结构直接接触上述接合部分。
在一些实施例中，上述液相层由水所形成。
在一些实施例中，在部分地移除上述第一重分布层以于上述第一重分布层中形成上述校准沟槽的步骤之前，上述方法亦包括于基板之上形成上述第一重分布层。
在一些实施例中，上述第一接合部分的第一长度大抵上等于上述芯片结构的第二长度。
在一些实施例中，上述芯片结构包括基板以及位于上述基板之上的第二重分布层，在将上述液相层蒸发之后上述第二重分布层直接接触上述第一接合部分，且上述第二重分布层具有上述第二宽度。
在一些实施例中，上述芯片结构包括基板以及位于上述基板之上的第二重分布层，上述第二重分布层具有第二接合部分以及上述第二接合部分与上述基板之间的一部分，上述第二接合部分比上述部分窄，上述第二接合部分具有上述第二宽度，且在将上述液相层蒸发之后上述第二接合部分直接接触上述第一接合部分。
在一些实施例中，上述芯片结构包括基板以及位于上述基板之上的第二重分布层，在将上述液相层蒸发之后上述基板直接接触上述第一接合部分，且上述基板具有上述第二宽度。
在一些实施例中，上述方法亦包括在将上述液相层蒸发之后于上述第一重分布层之上形成保护层以围绕上述芯片结构，上述校准沟槽被上述保护层填充。
在一些实施例中，上述方法亦包括在形成上述保护层之后部分地移除上述保护层以于上述保护层中形成贯穿孔，并于上述贯穿孔中形成导孔结构，上述贯穿孔穿过上述保护层且延伸至上述校准沟槽中。
在一些实施例中，上述芯片结构包括基板以及位于上述基板之上的第二重分布层，在将上述液相层蒸发之后上述第二重分布层直接接触上述第一接合部分，且上述方法亦包括在形成上述保护层之后部分地移除上述基板以于上述基板中形成贯穿孔，并于上述贯穿孔中形成导孔结构，上述贯穿孔穿过上述基板且上述导孔结构电性连接至上述第二重分布层。
根据一些实施例，提供一种芯片封装结构的形成方法。上述方法包括部分地移除载体基板以于载体基板中形成校准沟槽。校准沟槽围绕载体基板的接合部分。上述方法包括于接合部分之上形成液相层。上述方法包括于液相层之上设置芯片结构。芯片结构与接合部分具有相同的形状。上述方法包括将液相层蒸发。在将液相层蒸发之后芯片结构接合至接合部分。
在一些实施例中，上述接合部分的第一宽度大抵上等于上述芯片结构的第二宽度。
在一些实施例中，上述接合部分的第一长度大抵上等于上述芯片结构的第二长度。
在一些实施例中，上述芯片结构包括基板以及位于上述基板之上的第二重分布层。在将上述液相层蒸发之后上述基板直接接触上述接合部分。
在一些实施例中，上述方法亦包括在将上述液相层蒸发的步骤之后于上述载体基板之上形成保护层以围绕上述芯片结构。上述保护层填充上述校准沟槽。
根据一些实施例，提供一种芯片封装结构。芯片封装结构包括具有接合部分的第一重分布层。芯片封装结构包括接合至接合部分的芯片结构。接合部分的第一宽度大抵上等于芯片结构的第二宽度。芯片封装结构包括保护层。保护层位于第一重分布层之上且围绕芯片结构。保护层的一部分延伸至第一重分布层中且围绕接合部分。
在一些实施例中，上述接合部分的第一侧壁与上述芯片结构的第二侧壁大抵上共平面。
在一些实施例中，上述芯片结构包括基板以及第二重分布层。上述第二重分布层位于上述基板与上述接合部分之间。上述第二重分布层直接接触上述接合部分，且上述第二重分布层具有上述第二宽度。
在一些实施例中，上述芯片结构包括基板以及第二重分布层。上述第二重分布层位于上述基板之上。上述基板直接接触上述接合部分，且上述基板具有上述第二宽度。
在一些实施例中，上述芯片封装结构亦包括导孔结构。上述导孔结构穿过上述保护层且电性连接至上述第一重分布层。上述导孔结构穿过上述第一重分布层中的上述保护层的上述部分。
前述内文概述了许多实施例的特征部件，使本技术领域中技术人员可以更加了解本公开实施例的各层面。本技术领域中技术人员应可理解，且可轻易地以本公开实施例为基础来设计或修饰其他工艺及结构，并以此达到与在此介绍的实施例相同的目的及/或达到与在此介绍的实施例相同的优点。本技术领域中技术人员也应了解这些相等的结构并未背离本公开实施例的公开构思与范围。在不背离本公开实施例的公开构思与范围的前提下，可对本公开实施例进行各种改变、置换或修改。

Claims (1)

1.一种芯片封装结构的形成方法，包括：
部分地移除一第一重分布层以于该第一重分布层中形成一校准沟槽，其中该校准沟槽围绕该第一重分布层的一第一接合部分；
于该第一接合部分之上形成一液相层；
于该液相层之上设置一芯片结构，其中该第一接合部分的一第一宽度大抵上等于该芯片结构的一第二宽度；以及
将该液相层蒸发，其中在将该液相层蒸发之后该芯片结构接合至该第一接合部分。
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