JP2010239325A5 - - Google Patents
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- Publication number
- JP2010239325A5 JP2010239325A5 JP2009083786A JP2009083786A JP2010239325A5 JP 2010239325 A5 JP2010239325 A5 JP 2010239325A5 JP 2009083786 A JP2009083786 A JP 2009083786A JP 2009083786 A JP2009083786 A JP 2009083786A JP 2010239325 A5 JP2010239325 A5 JP 2010239325A5
- Authority
- JP
- Japan
- Prior art keywords
- inverter circuits
- flop
- type flip
- bit
- clocked gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 1
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009083786A JP5140029B2 (ja) | 2009-03-30 | 2009-03-30 | 半導体装置 |
| PCT/JP2010/055029 WO2010113713A1 (ja) | 2009-03-30 | 2010-03-24 | 半導体装置 |
| CN201080013413.3A CN102369668B (zh) | 2009-03-30 | 2010-03-24 | 半导体装置 |
| US13/255,846 US8283945B2 (en) | 2009-03-30 | 2010-03-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009083786A JP5140029B2 (ja) | 2009-03-30 | 2009-03-30 | 半導体装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2010239325A JP2010239325A (ja) | 2010-10-21 |
| JP2010239325A5 true JP2010239325A5 (enExample) | 2011-12-15 |
| JP5140029B2 JP5140029B2 (ja) | 2013-02-06 |
Family
ID=42828008
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2009083786A Expired - Fee Related JP5140029B2 (ja) | 2009-03-30 | 2009-03-30 | 半導体装置 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US8283945B2 (enExample) |
| JP (1) | JP5140029B2 (enExample) |
| CN (1) | CN102369668B (enExample) |
| WO (1) | WO2010113713A1 (enExample) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011162116A1 (ja) | 2010-06-24 | 2011-12-29 | 太陽誘電株式会社 | 半導体装置 |
| JP5890733B2 (ja) * | 2012-04-09 | 2016-03-22 | 太陽誘電株式会社 | 再構成可能な半導体装置の配置配線方法、そのプログラム、及び配置配線装置 |
| JP5822772B2 (ja) | 2012-04-11 | 2015-11-24 | 太陽誘電株式会社 | 再構成可能な半導体装置 |
| US9350357B2 (en) | 2012-10-28 | 2016-05-24 | Taiyo Yuden Co., Ltd. | Reconfigurable semiconductor device |
| JP6250548B2 (ja) * | 2012-11-20 | 2017-12-20 | 太陽誘電株式会社 | 再構成可能な半導体装置の論理構成方法 |
| US9762865B2 (en) * | 2013-03-15 | 2017-09-12 | James Carey | Video identification and analytical recognition system |
| US9425800B2 (en) | 2013-04-02 | 2016-08-23 | Taiyo Yuden Co., Ltd. | Reconfigurable logic device |
| JP6306846B2 (ja) * | 2013-09-16 | 2018-04-04 | 太陽誘電株式会社 | 再構成可能な論理デバイス |
| US9423452B2 (en) | 2013-12-03 | 2016-08-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contactless signal testing |
| US9923561B2 (en) * | 2014-10-22 | 2018-03-20 | Taiyo Yuden Co., Ltd. | Reconfigurable device |
| JP6390683B2 (ja) * | 2016-09-28 | 2018-09-19 | ミツミ電機株式会社 | 半導体集積回路 |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0220923A (ja) * | 1988-07-08 | 1990-01-24 | Fujitsu Ltd | プログラマブル・ロジック・デバイス |
| JPH11238850A (ja) * | 1998-02-19 | 1999-08-31 | Toshiba Corp | 半導体集積回路 |
| JP3471628B2 (ja) | 1998-05-12 | 2003-12-02 | 日本電信電話株式会社 | 書き換え可能な論理回路およびラッチ回路 |
| US6150838A (en) * | 1999-02-25 | 2000-11-21 | Xilinx, Inc. | FPGA configurable logic block with multi-purpose logic/memory circuit |
| US6215327B1 (en) * | 1999-09-01 | 2001-04-10 | The United States Of America As Represented By The Secretary Of The Air Force | Molecular field programmable gate array |
| JP3517839B2 (ja) | 2000-11-29 | 2004-04-12 | 日本電信電話株式会社 | プログラマブルセルアレイ回路 |
| US6331788B1 (en) * | 2001-07-03 | 2001-12-18 | The United States Of America As Represented By The Secretary Of The Air Force | Simplified cellular array structure for programmable Boolean networks |
| US6777977B1 (en) * | 2002-05-01 | 2004-08-17 | Actel Corporation | Three input field programmable gate array logic circuit configurable as a three input look up table, a D-latch or a D flip-flop |
| JP4226383B2 (ja) * | 2003-04-23 | 2009-02-18 | 株式会社ミツトヨ | 測長装置 |
| US7102387B1 (en) * | 2004-12-08 | 2006-09-05 | The United States Of America As Represented By The Secretary Of The Air Force | Periodic computation structure based on 1-input lookup tables |
| US20090290444A1 (en) * | 2005-11-28 | 2009-11-26 | Masayuki Satoh | Semiconductor device |
| US7632745B2 (en) * | 2007-06-30 | 2009-12-15 | Intel Corporation | Hybrid high-k gate dielectric film |
| US8010590B1 (en) * | 2007-07-19 | 2011-08-30 | Xilinx, Inc. | Configurable arithmetic block and a method of implementing a configurable arithmetic block in a device having programmable logic |
| US7816946B1 (en) * | 2008-01-31 | 2010-10-19 | Actel Corporation | Inverting flip-flop for use in field programmable gate arrays |
-
2009
- 2009-03-30 JP JP2009083786A patent/JP5140029B2/ja not_active Expired - Fee Related
-
2010
- 2010-03-24 US US13/255,846 patent/US8283945B2/en not_active Expired - Fee Related
- 2010-03-24 WO PCT/JP2010/055029 patent/WO2010113713A1/ja not_active Ceased
- 2010-03-24 CN CN201080013413.3A patent/CN102369668B/zh not_active Expired - Fee Related
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