US7816946B1 - Inverting flip-flop for use in field programmable gate arrays - Google Patents
Inverting flip-flop for use in field programmable gate arrays Download PDFInfo
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- US7816946B1 US7816946B1 US12/360,948 US36094809A US7816946B1 US 7816946 B1 US7816946 B1 US 7816946B1 US 36094809 A US36094809 A US 36094809A US 7816946 B1 US7816946 B1 US 7816946B1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/1778—Structural details for adapting physical parameters
Abstract
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Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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US12/360,948 US7816946B1 (en) | 2008-01-31 | 2009-01-28 | Inverting flip-flop for use in field programmable gate arrays |
US12/879,306 US7932745B2 (en) | 2008-01-31 | 2010-09-10 | Inverting flip-flop for use in field programmable gate arrays |
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US2501208P | 2008-01-31 | 2008-01-31 | |
US12/360,948 US7816946B1 (en) | 2008-01-31 | 2009-01-28 | Inverting flip-flop for use in field programmable gate arrays |
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US12/879,306 Division US7932745B2 (en) | 2008-01-31 | 2010-09-10 | Inverting flip-flop for use in field programmable gate arrays |
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US7816946B1 true US7816946B1 (en) | 2010-10-19 |
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US12/360,948 Active US7816946B1 (en) | 2008-01-31 | 2009-01-28 | Inverting flip-flop for use in field programmable gate arrays |
US12/879,306 Active US7932745B2 (en) | 2008-01-31 | 2010-09-10 | Inverting flip-flop for use in field programmable gate arrays |
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US12/879,306 Active US7932745B2 (en) | 2008-01-31 | 2010-09-10 | Inverting flip-flop for use in field programmable gate arrays |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100327906A1 (en) * | 2008-01-31 | 2010-12-30 | Actel Corporation | Inverting flip-flop for use in field programmable gate arrays |
US7924053B1 (en) * | 2008-01-30 | 2011-04-12 | Actel Corporation | Clustered field programmable gate array architecture |
US20130019041A1 (en) * | 2011-07-12 | 2013-01-17 | Lsi Corporation | Bit slice round robin arbiter |
US11671099B2 (en) | 2021-05-21 | 2023-06-06 | Microchip Technology Inc. | Logic cell for programmable gate array |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5140029B2 (en) * | 2009-03-30 | 2013-02-06 | 太陽誘電株式会社 | Semiconductor device |
US20130278289A1 (en) * | 2012-04-18 | 2013-10-24 | Te-Tse Jang | Method and Apparatus for Improving Efficiency of Programmable Logic Circuit Using Cascade Configuration |
EP2779456B1 (en) * | 2013-03-15 | 2018-08-29 | Dialog Semiconductor B.V. | Method for reducing overdrive need in mos switching and logic circuit |
Citations (15)
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---|---|---|---|---|
US4638183A (en) | 1984-09-20 | 1987-01-20 | International Business Machines Corporation | Dynamically selectable polarity latch |
US5495182A (en) | 1995-02-28 | 1996-02-27 | Altera Corporation | Fast-fully restoring polarity control circuit |
US5502403A (en) | 1994-12-20 | 1996-03-26 | Cypress Semiconductor Corp. | High speed configuration independent programmable macrocell |
US5583451A (en) | 1993-03-19 | 1996-12-10 | Advanced Micro Devices, Inc. | Polarity control circuit which may be used with a ground bounce limiting buffer |
US5635856A (en) | 1995-10-03 | 1997-06-03 | Cypress Semiconductor Corporation | High speed programmable macrocell with combined path for storage and combinatorial modes |
US5796624A (en) | 1994-09-16 | 1998-08-18 | Research Foundation Of State University Of New York | Method and apparatus for designing circuits for wave pipelining |
US6121797A (en) | 1996-02-01 | 2000-09-19 | Samsung Electronics Co., Ltd. | Energy economized pass-transistor logic circuit and full adder using the same |
USRE37577E1 (en) | 1996-01-11 | 2002-03-12 | Cypress Semiconductor Corporation | High speed configuration independent programmable macrocell |
US6466049B1 (en) * | 2000-09-14 | 2002-10-15 | Xilinx, Inc. | Clock enable control circuit for flip flops |
US6477695B1 (en) | 1998-12-09 | 2002-11-05 | Artisan Components, Inc. | Methods for designing standard cell transistor structures |
US6785875B2 (en) | 2002-08-15 | 2004-08-31 | Fulcrum Microsystems, Inc. | Methods and apparatus for facilitating physical synthesis of an integrated circuit design |
US6993737B1 (en) | 2003-09-11 | 2006-01-31 | Xilinx, Inc. | Leakage power optimization for integrated circuits |
US20070007996A1 (en) | 2003-12-08 | 2007-01-11 | University Of South Florida | A Method and Apparatus for Reducing Leakage in Integrated Circuits |
US20070136706A1 (en) | 2005-09-16 | 2007-06-14 | Qualcomm Incorporated | Exploration Of The Method Of The Interconnect Effort In Nano-Technologies |
US7317332B2 (en) * | 1999-03-04 | 2008-01-08 | Altera Corporation | Interconnection and input/output resources for programmable logic integrated circuit devices |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US37577A (en) * | 1863-02-03 | Improved shipper-lever for looms | ||
US8255854B2 (en) | 2006-09-22 | 2012-08-28 | Actel Corporation | Architecture and method for compensating for disparate signal rise and fall times by using polarity selection to improve timing and power in an integrated circuit |
US7816946B1 (en) * | 2008-01-31 | 2010-10-19 | Actel Corporation | Inverting flip-flop for use in field programmable gate arrays |
-
2009
- 2009-01-28 US US12/360,948 patent/US7816946B1/en active Active
-
2010
- 2010-09-10 US US12/879,306 patent/US7932745B2/en active Active
Patent Citations (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4638183A (en) | 1984-09-20 | 1987-01-20 | International Business Machines Corporation | Dynamically selectable polarity latch |
US5583451A (en) | 1993-03-19 | 1996-12-10 | Advanced Micro Devices, Inc. | Polarity control circuit which may be used with a ground bounce limiting buffer |
US5796624A (en) | 1994-09-16 | 1998-08-18 | Research Foundation Of State University Of New York | Method and apparatus for designing circuits for wave pipelining |
US5502403A (en) | 1994-12-20 | 1996-03-26 | Cypress Semiconductor Corp. | High speed configuration independent programmable macrocell |
US5621338A (en) | 1994-12-20 | 1997-04-15 | Cypress Semiconductor Corp. | High speed configuration independent programmable macrocell |
US5495182A (en) | 1995-02-28 | 1996-02-27 | Altera Corporation | Fast-fully restoring polarity control circuit |
US5635856A (en) | 1995-10-03 | 1997-06-03 | Cypress Semiconductor Corporation | High speed programmable macrocell with combined path for storage and combinatorial modes |
USRE37577E1 (en) | 1996-01-11 | 2002-03-12 | Cypress Semiconductor Corporation | High speed configuration independent programmable macrocell |
US6121797A (en) | 1996-02-01 | 2000-09-19 | Samsung Electronics Co., Ltd. | Energy economized pass-transistor logic circuit and full adder using the same |
US6477695B1 (en) | 1998-12-09 | 2002-11-05 | Artisan Components, Inc. | Methods for designing standard cell transistor structures |
US7317332B2 (en) * | 1999-03-04 | 2008-01-08 | Altera Corporation | Interconnection and input/output resources for programmable logic integrated circuit devices |
US6466049B1 (en) * | 2000-09-14 | 2002-10-15 | Xilinx, Inc. | Clock enable control circuit for flip flops |
US6785875B2 (en) | 2002-08-15 | 2004-08-31 | Fulcrum Microsystems, Inc. | Methods and apparatus for facilitating physical synthesis of an integrated circuit design |
US6993737B1 (en) | 2003-09-11 | 2006-01-31 | Xilinx, Inc. | Leakage power optimization for integrated circuits |
US20070007996A1 (en) | 2003-12-08 | 2007-01-11 | University Of South Florida | A Method and Apparatus for Reducing Leakage in Integrated Circuits |
US20070136706A1 (en) | 2005-09-16 | 2007-06-14 | Qualcomm Incorporated | Exploration Of The Method Of The Interconnect Effort In Nano-Technologies |
Non-Patent Citations (4)
Title |
---|
Anderson, J. H. et al., "Active Leakage Power Optimization for FPGAs", Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate array, 2004, pp. 33-41, Monterey, California, USA. |
Co-pending U.S. Appl. No. 11/859,678, filed Sep. 21, 2007 entitled Architecture and Method for Compensating For Disparate Signal Rise and Fall Times by Using Polarity Selection to Improve Timing and Power in an Integrated Circuit. |
Office Action dated Nov. 17, 2009 in co-pending U.S. Appl. No. 11/859,678, filed Sep. 21, 2007. |
Zhu, Kai, "Post-Route LUT Output Polarity Selection for Timing Optimization", Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, FPGA 2007, Feb. 18-20, 2007, held in Monterey, California, USA, pp. 89-96, ACM Press, 2007. |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7924053B1 (en) * | 2008-01-30 | 2011-04-12 | Actel Corporation | Clustered field programmable gate array architecture |
US20100327906A1 (en) * | 2008-01-31 | 2010-12-30 | Actel Corporation | Inverting flip-flop for use in field programmable gate arrays |
US7932745B2 (en) * | 2008-01-31 | 2011-04-26 | Actel Corporation | Inverting flip-flop for use in field programmable gate arrays |
US20130019041A1 (en) * | 2011-07-12 | 2013-01-17 | Lsi Corporation | Bit slice round robin arbiter |
US11671099B2 (en) | 2021-05-21 | 2023-06-06 | Microchip Technology Inc. | Logic cell for programmable gate array |
Also Published As
Publication number | Publication date |
---|---|
US20100327906A1 (en) | 2010-12-30 |
US7932745B2 (en) | 2011-04-26 |
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