JP2017055332A5 - - Google Patents

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Publication number
JP2017055332A5
JP2017055332A5 JP2015179388A JP2015179388A JP2017055332A5 JP 2017055332 A5 JP2017055332 A5 JP 2017055332A5 JP 2015179388 A JP2015179388 A JP 2015179388A JP 2015179388 A JP2015179388 A JP 2015179388A JP 2017055332 A5 JP2017055332 A5 JP 2017055332A5
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JP
Japan
Prior art keywords
output
latch
input
circuit
inverter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
JP2015179388A
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English (en)
Japanese (ja)
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JP2017055332A (ja
JP6453732B2 (ja
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Priority to JP2015179388A priority Critical patent/JP6453732B2/ja
Priority claimed from JP2015179388A external-priority patent/JP6453732B2/ja
Priority to US15/056,294 priority patent/US9742383B2/en
Publication of JP2017055332A publication Critical patent/JP2017055332A/ja
Priority to US15/645,088 priority patent/US10187043B2/en
Publication of JP2017055332A5 publication Critical patent/JP2017055332A5/ja
Application granted granted Critical
Publication of JP6453732B2 publication Critical patent/JP6453732B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2015179388A 2015-09-11 2015-09-11 半導体集積回路 Expired - Fee Related JP6453732B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2015179388A JP6453732B2 (ja) 2015-09-11 2015-09-11 半導体集積回路
US15/056,294 US9742383B2 (en) 2015-09-11 2016-02-29 Semiconductor integrated circuit
US15/645,088 US10187043B2 (en) 2015-09-11 2017-07-10 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015179388A JP6453732B2 (ja) 2015-09-11 2015-09-11 半導体集積回路

Publications (3)

Publication Number Publication Date
JP2017055332A JP2017055332A (ja) 2017-03-16
JP2017055332A5 true JP2017055332A5 (enExample) 2017-10-19
JP6453732B2 JP6453732B2 (ja) 2019-01-16

Family

ID=58237384

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015179388A Expired - Fee Related JP6453732B2 (ja) 2015-09-11 2015-09-11 半導体集積回路

Country Status (2)

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US (2) US9742383B2 (enExample)
JP (1) JP6453732B2 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6453732B2 (ja) * 2015-09-11 2019-01-16 株式会社東芝 半導体集積回路
CN107317569A (zh) * 2017-06-16 2017-11-03 上海华虹宏力半导体制造有限公司 数据触发器装置
JP6850366B2 (ja) * 2018-01-16 2021-03-31 ヌヴォトンテクノロジージャパン株式会社 半導体集積回路
US10868524B2 (en) * 2018-12-13 2020-12-15 Samsung Electronics Co., Ltd. Semiconductor circuit and semiconductor circuit layout system
KR102627943B1 (ko) * 2018-12-13 2024-01-22 삼성전자주식회사 반도체 회로 및 반도체 회로의 레이아웃 시스템
US11366162B2 (en) * 2020-04-16 2022-06-21 Mediatek Inc. Scan output flip-flop with power saving feature
US12418281B2 (en) * 2024-01-29 2025-09-16 Texas Instruments Incorporated Low area and power multi-bit flip-flop

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60224319A (ja) 1984-04-20 1985-11-08 Seiko Epson Corp フリツプ・フロツプ回路
JPS63224319A (ja) 1987-03-13 1988-09-19 Seiko Instr & Electronics Ltd 分子線エピタキシ−装置
JP3120492B2 (ja) 1991-10-09 2000-12-25 日本電気株式会社 半導体集積回路
JPH05206792A (ja) 1992-01-30 1993-08-13 Nec Ic Microcomput Syst Ltd フリップフロップ回路
JPH0795016A (ja) 1993-09-20 1995-04-07 Fujitsu Ltd フリップフロップ回路及びスキャン回路
JPH09203767A (ja) * 1996-01-24 1997-08-05 Sony Corp スキャン記憶装置およびスキャンパス回路
JPH10177060A (ja) * 1996-12-18 1998-06-30 Kawasaki Steel Corp スキャン回路
JP3420142B2 (ja) 1999-11-11 2003-06-23 Ｎｅｃエレクトロニクス株式会社 スキャンパステスト用のフリップフロップ回路
JP4579370B2 (ja) * 2000-04-24 2010-11-10 ルネサスエレクトロニクス株式会社 スキャンフリップフロップ回路及びこれを用いたスキャンテスト方法
SG86407A1 (en) 2000-06-13 2002-02-19 Texas Instr Singapore Pte Ltd Regenerative tie-high tie-low cell
JP3573703B2 (ja) 2000-10-30 2004-10-06 Ｎｅｃマイクロシステム株式会社 半導体装置の製造方法
JP3587248B2 (ja) 2000-12-20 2004-11-10 日本電気株式会社 スキャン用フリップフロップ
JP3802377B2 (ja) 2001-07-27 2006-07-26 Ｎｅｃエレクトロニクス株式会社 フリップフロップ及びスキャンパス回路
US7137094B2 (en) 2004-04-16 2006-11-14 Taiwan Semiconductor Manufacturing Company Method for reducing layers revision in engineering change order
US7221183B2 (en) 2005-02-23 2007-05-22 Taiwan Semiconductor Manufacturing Company Tie-high and tie-low circuit
US7663851B2 (en) 2005-05-25 2010-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Tie-off circuit with ESD protection features
JP2007170822A (ja) * 2005-12-19 2007-07-05 Sharp Corp フリップフロップ、および半導体集積回路
KR20090027042A (ko) * 2007-09-11 2009-03-16 주식회사 동부하이텍 리텐션 기능을 갖는 ｍｔｃｍｏｓ 플립플롭
US7949988B2 (en) 2008-04-01 2011-05-24 Mediatek Inc. Layout circuit having a combined tie cell
WO2009146241A1 (en) 2008-05-27 2009-12-03 Sandbridge Technologies, Inc. Power saving circuit using a clock buffer and multiple flip-flops
JP4892044B2 (ja) * 2009-08-06 2012-03-07 株式会社東芝 半導体装置
JP2011055224A (ja) 2009-09-01 2011-03-17 Nec Corp フリップフロップ回路
WO2013084364A1 (ja) * 2011-12-09 2013-06-13 富士通株式会社 スキャン回路及び半導体集積回路
JP5875996B2 (ja) 2013-02-13 2016-03-02 株式会社東芝 フリップフロップ回路
US9350327B2 (en) * 2014-09-26 2016-05-24 Texas Instruments Incorporated Flip-flops with low clock power
JP6453732B2 (ja) * 2015-09-11 2019-01-16 株式会社東芝 半導体集積回路

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