JP6453732B2 - 半導体集積回路 - Google Patents

半導体集積回路 Download PDF

Info

Publication number
JP6453732B2
JP6453732B2 JP2015179388A JP2015179388A JP6453732B2 JP 6453732 B2 JP6453732 B2 JP 6453732B2 JP 2015179388 A JP2015179388 A JP 2015179388A JP 2015179388 A JP2015179388 A JP 2015179388A JP 6453732 B2 JP6453732 B2 JP 6453732B2
Authority
JP
Japan
Prior art keywords
output
input
inverter
flop
flip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2015179388A
Other languages
English (en)
Japanese (ja)
Other versions
JP2017055332A (ja
JP2017055332A5 (enExample
Inventor
前野　宗昭
宗昭 前野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Devices and Storage Corp
Original Assignee
Toshiba Corp
Toshiba Electronic Devices and Storage Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Electronic Devices and Storage Corp filed Critical Toshiba Corp
Priority to JP2015179388A priority Critical patent/JP6453732B2/ja
Priority to US15/056,294 priority patent/US9742383B2/en
Publication of JP2017055332A publication Critical patent/JP2017055332A/ja
Priority to US15/645,088 priority patent/US10187043B2/en
Publication of JP2017055332A5 publication Critical patent/JP2017055332A5/ja
Application granted granted Critical
Publication of JP6453732B2 publication Critical patent/JP6453732B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3562—Bistable circuits of the primary-secondary type
    • H03K3/35625—Bistable circuits of the primary-secondary type using complementary field-effect transistors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318541—Scan latches or cell details

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2015179388A 2015-09-11 2015-09-11 半導体集積回路 Expired - Fee Related JP6453732B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2015179388A JP6453732B2 (ja) 2015-09-11 2015-09-11 半導体集積回路
US15/056,294 US9742383B2 (en) 2015-09-11 2016-02-29 Semiconductor integrated circuit
US15/645,088 US10187043B2 (en) 2015-09-11 2017-07-10 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015179388A JP6453732B2 (ja) 2015-09-11 2015-09-11 半導体集積回路

Publications (3)

Publication Number Publication Date
JP2017055332A JP2017055332A (ja) 2017-03-16
JP2017055332A5 JP2017055332A5 (enExample) 2017-10-19
JP6453732B2 true JP6453732B2 (ja) 2019-01-16

Family

ID=58237384

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015179388A Expired - Fee Related JP6453732B2 (ja) 2015-09-11 2015-09-11 半導体集積回路

Country Status (2)

Country Link
US (2) US9742383B2 (enExample)
JP (1) JP6453732B2 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6453732B2 (ja) * 2015-09-11 2019-01-16 株式会社東芝 半導体集積回路
CN107317569A (zh) * 2017-06-16 2017-11-03 上海华虹宏力半导体制造有限公司 数据触发器装置
JP6850366B2 (ja) * 2018-01-16 2021-03-31 ヌヴォトンテクノロジージャパン株式会社 半導体集積回路
US10868524B2 (en) * 2018-12-13 2020-12-15 Samsung Electronics Co., Ltd. Semiconductor circuit and semiconductor circuit layout system
KR102627943B1 (ko) * 2018-12-13 2024-01-22 삼성전자주식회사 반도체 회로 및 반도체 회로의 레이아웃 시스템
US11366162B2 (en) * 2020-04-16 2022-06-21 Mediatek Inc. Scan output flip-flop with power saving feature
US12418281B2 (en) * 2024-01-29 2025-09-16 Texas Instruments Incorporated Low area and power multi-bit flip-flop

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60224319A (ja) 1984-04-20 1985-11-08 Seiko Epson Corp フリツプ・フロツプ回路
JPS63224319A (ja) 1987-03-13 1988-09-19 Seiko Instr & Electronics Ltd 分子線エピタキシ−装置
JP3120492B2 (ja) 1991-10-09 2000-12-25 日本電気株式会社 半導体集積回路
JPH05206792A (ja) 1992-01-30 1993-08-13 Nec Ic Microcomput Syst Ltd フリップフロップ回路
JPH0795016A (ja) 1993-09-20 1995-04-07 Fujitsu Ltd フリップフロップ回路及びスキャン回路
JPH09203767A (ja) * 1996-01-24 1997-08-05 Sony Corp スキャン記憶装置およびスキャンパス回路
JPH10177060A (ja) * 1996-12-18 1998-06-30 Kawasaki Steel Corp スキャン回路
JP3420142B2 (ja) 1999-11-11 2003-06-23 Ｎｅｃエレクトロニクス株式会社 スキャンパステスト用のフリップフロップ回路
JP4579370B2 (ja) * 2000-04-24 2010-11-10 ルネサスエレクトロニクス株式会社 スキャンフリップフロップ回路及びこれを用いたスキャンテスト方法
SG86407A1 (en) 2000-06-13 2002-02-19 Texas Instr Singapore Pte Ltd Regenerative tie-high tie-low cell
JP3573703B2 (ja) 2000-10-30 2004-10-06 Ｎｅｃマイクロシステム株式会社 半導体装置の製造方法
JP3587248B2 (ja) 2000-12-20 2004-11-10 日本電気株式会社 スキャン用フリップフロップ
JP3802377B2 (ja) 2001-07-27 2006-07-26 Ｎｅｃエレクトロニクス株式会社 フリップフロップ及びスキャンパス回路
US7137094B2 (en) 2004-04-16 2006-11-14 Taiwan Semiconductor Manufacturing Company Method for reducing layers revision in engineering change order
US7221183B2 (en) 2005-02-23 2007-05-22 Taiwan Semiconductor Manufacturing Company Tie-high and tie-low circuit
US7663851B2 (en) 2005-05-25 2010-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Tie-off circuit with ESD protection features
JP2007170822A (ja) * 2005-12-19 2007-07-05 Sharp Corp フリップフロップ、および半導体集積回路
KR20090027042A (ko) * 2007-09-11 2009-03-16 주식회사 동부하이텍 리텐션 기능을 갖는 ｍｔｃｍｏｓ 플립플롭
US7949988B2 (en) 2008-04-01 2011-05-24 Mediatek Inc. Layout circuit having a combined tie cell
WO2009146241A1 (en) 2008-05-27 2009-12-03 Sandbridge Technologies, Inc. Power saving circuit using a clock buffer and multiple flip-flops
JP4892044B2 (ja) * 2009-08-06 2012-03-07 株式会社東芝 半導体装置
JP2011055224A (ja) 2009-09-01 2011-03-17 Nec Corp フリップフロップ回路
WO2013084364A1 (ja) * 2011-12-09 2013-06-13 富士通株式会社 スキャン回路及び半導体集積回路
JP5875996B2 (ja) 2013-02-13 2016-03-02 株式会社東芝 フリップフロップ回路
US9350327B2 (en) * 2014-09-26 2016-05-24 Texas Instruments Incorporated Flip-flops with low clock power
JP6453732B2 (ja) * 2015-09-11 2019-01-16 株式会社東芝 半導体集積回路

Also Published As

Publication number Publication date
US9742383B2 (en) 2017-08-22
US10187043B2 (en) 2019-01-22
JP2017055332A (ja) 2017-03-16
US20170310309A1 (en) 2017-10-26
US20170077909A1 (en) 2017-03-16

Similar Documents

Publication Publication Date Title
JP6453732B2 (ja) 半導体集積回路
US20090300448A1 (en) Scan flip-flop device
US7944242B2 (en) Semiconductor integrated circuit having insulated gate field effect transistors
KR20120100385A (ko) 플립-플롭 및 이를 포함하는 반도체 장치
CN101783660A (zh) 触发器以及流水线模数转换器
US10110208B2 (en) Apparatuses and methods for providing a signal with a differential phase mixer
CN111510137A (zh) 时钟电路、计算芯片、算力板和数字货币挖矿机
WO2023207587A1 (zh) 具有多路选择器功能的d触发器
US11855628B2 (en) Power domain change circuit and operating method thereof
US8952739B2 (en) Input circuit
US20100125431A1 (en) Compact test circuit and integrated circuit having the same
JP2016201623A (ja) フリップフロップ回路および半導体集積回路装置
KR20120048965A (ko) 키퍼 회로를 포함하는 플립-플롭
CN113608112A (zh) 扫描输出触发器
JP5807287B2 (ja) 試験可能な不揮発論理ゲート
US7911258B2 (en) Semiconductor integrated circuit device, redundancy system, and redundancy method for latching and transmitting fuse data
JP6850366B2 (ja) 半導体集積回路
CN111092616B (zh) 修复集成电路中建立时间违规的读出放大器触发器和方法
CN114866072A (zh) 低功率触发器
JP4077123B2 (ja) 差動信号出力回路
US6362657B1 (en) Small aperture latch for use with a differential clock
US11177011B2 (en) Bit data shifter
US20150171840A1 (en) Latch circuit and semiconductor integrated circuit
US9964595B2 (en) Register circuit
KR101308099B1 (ko) 단일스테이지 지연 추론적 어드레스 디코더

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170904

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20170904

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20170911

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20170912

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20180524

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20180529

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20180726

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20181113

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20181213

R150 Certificate of patent or registration of utility model

Ref document number: 6453732

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees