JP2009505424A5 - - Google Patents

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JP2009505424A5
JP2009505424A5 JP2008527013A JP2008527013A JP2009505424A5 JP 2009505424 A5 JP2009505424 A5 JP 2009505424A5 JP 2008527013 A JP2008527013 A JP 2008527013A JP 2008527013 A JP2008527013 A JP 2008527013A JP 2009505424 A5 JP2009505424 A5 JP 2009505424A5
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opening
mask
dielectric layer
dry
etching
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JP2008527013A
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JP2009505424A (ja
JP5152674B2 (ja
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Priority claimed from US11/203,141 external-priority patent/US7521705B2/en
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マスク３１６が誘電体層３１４上に形成される。説明されている実施例において、マスク３１６はフォトレジスト（ｐｈｏｔｏｒｅｓｉｓｔ）マスクであり、しかしながら、マスク３１６は、例えば、金属（ｍｅｔａｌ）などのいずれかの他の適切な材料でも代替できる。基板３００へと延びる開口部３１３が誘電体層３１４およびマスク３１６内に形成される。開口部３１３は、この技術分野での既知の技術、例えば、一般的なパターンニングおよびエッチング処理、によって形成される。好ましくは、開口部３１３は、実質的に垂直な側壁を有するように、ドライエッチング（ｄｒｙ ｅｔｃｈ）ビアプロセスによって形成される。
図７に示されるように、開口部３１３が拡幅されて、誘電体層３１４中に開口部３１５が形成される。この開口部３１５は、マスク３１６を通る開口部３１３が誘電体層３１４を通る開口部３１５よりも小さくなるように、マスク３１６の下に拡張する。好ましくは、開口部３１５はウェットエッチングプロセスを用いて形成される。
JP2008527013A 2005-08-15 2006-08-11 再生可能可変抵抗絶縁メモリ装置の形成方法 Expired - Fee Related JP5152674B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/203,141 US7521705B2 (en) 2005-08-15 2005-08-15 Reproducible resistance variable insulating memory devices having a shaped bottom electrode
US11/203,141 2005-08-15
PCT/US2006/031345 WO2007021913A1 (en) 2005-08-15 2006-08-11 Reproducible resistance variable insulating memory devices and methods for forming same

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JP2012207558A Division JP2013048251A (ja) 2005-08-15 2012-09-20 可変抵抗絶縁層を用いたメモリ素子及びそれを有するプロセッサシステム

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JP2009505424A JP2009505424A (ja) 2009-02-05
JP2009505424A5 true JP2009505424A5 (ja) 2012-04-26
JP5152674B2 JP5152674B2 (ja) 2013-02-27

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JP2008527013A Expired - Fee Related JP5152674B2 (ja) 2005-08-15 2006-08-11 再生可能可変抵抗絶縁メモリ装置の形成方法
JP2012207558A Pending JP2013048251A (ja) 2005-08-15 2012-09-20 可変抵抗絶縁層を用いたメモリ素子及びそれを有するプロセッサシステム

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US (4) US7521705B2 (ja)
EP (2) EP1929556B1 (ja)
JP (2) JP5152674B2 (ja)
KR (1) KR100954948B1 (ja)
CN (1) CN101288187B (ja)
AT (1) ATE542251T1 (ja)
TW (1) TWI331794B (ja)
WO (1) WO2007021913A1 (ja)

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