JP2009503809A - 背面対前面バイアプロセス - Google Patents
背面対前面バイアプロセス Download PDFInfo
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- JP2009503809A JP2009503809A JP2008517111A JP2008517111A JP2009503809A JP 2009503809 A JP2009503809 A JP 2009503809A JP 2008517111 A JP2008517111 A JP 2008517111A JP 2008517111 A JP2008517111 A JP 2008517111A JP 2009503809 A JP2009503809 A JP 2009503809A
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Abstract
Description
新規のフォトリソグラフィのパターン化を行って、接点が作製される領域を画成する(図80)。
注:展性層は、スタンドオフ、拡散、キャップおよびバリア層の何れの組み合わせで構成してもよいが、ここでは、展性層は拡散およびキャップ層の組み合わせである。
Claims (14)
- 基板に接触するドープされた半導体材料を含む半導体チップへ実行される方法であって:
a)前記基板の外側から、前記基板の少なくとも一部を通り、前記ドープされた半導体材料に向けて前記基板内に延びる第1バイアであって、壁面と底を有する第1バイアを生成するステップと;
b)前記基板の外側と前記底との間に導電路を生成するために、第1導電性材料を前記第1バイアへ導入するステップと;
c)前記ステップb)に続いて、前記第1バイアにアライメントし、前記半導体チップのドープ部分の外面から前記底まで延びる第2バイアを生成するステップと;
d)前記基板の外側から前記半導体チップのドープ部分の外面まで延びる導電路を生成するために第2導電性材料を前記第2バイアへ導入するステップと;
を備える方法。 - 前記ステップb)に先立ち、前記第1バイアへ第1の電気絶縁材料を導入するステップを備える、
請求項1の方法。 - 前記ステップc)に続き、かつ前記ステップd)に先立ち、前記第1バイアへ第2の電気絶縁材料を導入するステップを備える、
請求項1の方法。 - 前記第1導電性材料を前記第1バイアへ導入するステップが、金属または合金をめっきするステップを含む、
請求項1の方法。 - 前記めっきするステップが電気めっきを行うステップを含む、
請求項4の方法。 - 前記めっきするステップが無電解めっきを行うステップを含む、
請求項4の方法。 - 前記第1導電性材料を前記第1バイアへ導入するステップが、堆積プロセスを用いて金属または合金を堆積するステップを含む、
請求項1の方法。 - 前記第1導電性材料を前記第1バイアへ導入するステップが、前記第1バイア内に2同軸導電体を形成するステップを含む、
請求項1の方法。 - 前記第1導電性材料を前記第1バイアへ導入するステップが、前記第1バイア内に3同軸導電体を形成するステップを含む、
請求項1の方法。 - 前記半導体チップと第2の半導体チップとを、前記第2半導体チップが前記導電路へハイブリッド化された電気接点を持つようにして、スタックすることによりユニットを形成するステップを更に備える、
請求項1の方法。 - 前記第1チップ上のデバイスのデバイス接点から、前記第1および第2導電性材料の一方まで延在する導電性トレースを形成するステップを更に備える、
請求項1の方法。 - 前記第2の導電性材料を前記第2バイアへ導入するステップが、前記第2の導電性材料のめっき用シードとして前記第1の導電性材料を使用するステップを含む、
請求項1の方法。 - 前記第2の導電性材料を前記第2バイアへ導入するステップが、前記シードを電気めっきするステップを含む、
請求項13の方法。 - 前記第2の導電性材料を前記第2バイアへ導入するステップが、前記シードを無電解めっきするステップを含む、
請求項13の方法。
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CN101553906B (zh) | 2011-10-26 |
WO2006138491A2 (en) | 2006-12-28 |
US20070161235A1 (en) | 2007-07-12 |
KR20080028878A (ko) | 2008-04-02 |
KR101088546B1 (ko) | 2011-12-05 |
CN101553906A (zh) | 2009-10-07 |
WO2006138491A3 (en) | 2009-05-07 |
JP5543712B2 (ja) | 2014-07-09 |
US7534722B2 (en) | 2009-05-19 |
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