KR20080028878A - 백-투-프론트 비어 프로세스 - Google Patents
백-투-프론트 비어 프로세스 Download PDFInfo
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- KR20080028878A KR20080028878A KR1020077029389A KR20077029389A KR20080028878A KR 20080028878 A KR20080028878 A KR 20080028878A KR 1020077029389 A KR1020077029389 A KR 1020077029389A KR 20077029389 A KR20077029389 A KR 20077029389A KR 20080028878 A KR20080028878 A KR 20080028878A
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Abstract
Description
Claims (14)
- 기판에 인접한 도핑된 반도체 물질을 포함하는 반도체 칩 상에서 수행되는 방법에 있어서,a) 상기 도핑된 반도체 물질을 향하여 기판의 외측으로부터 기판 내로 연장하는 기판의 적어도 일부를 통해 제1 비어를 생성하는 단계 - 상기 제1 비어는 벽 표면과 바닥부를 가짐 -;b) 상기 기판의 외측 및 바닥부 사이에 전기적 전도성 경로를 생성하기 위하여 제1 전기적 전도성 물질을 상기 제1 비어 내로 도입하는 단계;c), b) 단계 이후에, 상기 반도체 칩의 도핑된 부분의 외부면으로부터 바닥부로 연장하고 상기 제1 비어와 정렬된 제2 비어를 생성하는 단계; 및d) 상기 기판의 외측으로부터 상기 반도체 칩의 도핑된 부분의 외부면으로 연장하는 전기적 전도성 경로를 생성하기 위하여 제2 전기적 전도성 물질을 상기 제2 비어 내로 도입하는 단계를 포함하는 것을 특징으로 하는 방법.
- 제1항에 있어서, b) 단계 이전에, 제1 전기 절연 물질을 상기 제1 비어 내로 도입하는 단계를 더 포함하는 것을 특징으로 하는 방법.
- 제1항에 있어서, c) 단계 이후 및 d) 단계 이전에, 제2 전기 절연 물질을 상 기 제1 비어 내로 도입하는 단계를 더 포함하는 것을 특징으로 하는 방법.
- 제1항에 있어서, 상기 제1 전기적 전도성 물질을 상기 제1 비어에 도입하는 단계는 금속 또는 합금 중의 하나를 도금하는 단계를 포함하는 것을 특징으로 하는 방법.
- 제4항에 있어서, 상기 도금은 전기 도금을 포함하는 것을 특징으로 하는 방법.
- 제4항에 있어서, 상기 도금은 무전해 도금을 포함하는 것을 특징으로 하는 방법.
- 제1항에 있어서, 상기 제1 전기적 전도성 물질을 상기 제1 비어 내로 도입하는 단계는 증착 프로세스를 이용하여 금속 또는 합금 중의 하나를 증착하는 단계를 포함하는 것을 특징으로 하는 방법.
- 제1항에 있어서, 상기 제1 전기 전도성 물질을 상기 제1 비어 내로 도입하는 단계는 상기 제1 비어 내에 동축 도체를 형성하는 단계를 포함하는 것을 특징으로 하는 방법.
- 제1항에 있어서, 상기 제1 전기 전도성 물질을 상기 제1 비어 내로 도입하는 단계는 상기 제1 비어 내에 3축 도체를 형성하는 단계를 포함하는 것을 특징으로 하는 방법.
- 제1항에 있어서, 제2 반도체 칩이 상기 전기적 전도성 경로에 결합된 전기 콘택을 갖도록 제2 반도체 칩과 함께 상기 반도체 칩을 스택함으로써 유닛을 형성하는 단계를 더 포함하는 것을 특징으로 하는 방법.
- 제1항에 있어서, 상기 제1 칩 상의 장치용 장치 콘택으로부터 상기 제1 또는 제2 전기적 전도성 물질 중의 하나로 연장하는 전기적 전도성 트레이스를 형성하는 단계를 더 포함하는 것을 특징으로 하는 방법.
- 제1항에 있어서, 상기 제2 전기적 전도성 물질을 상기 제2 비어 내로 도입하는 단계는 상기 제2 전기적 전도성 물질의 도금을 위한 시드로서 상기 제1 전기적 전도성 물질을 사용하는 단계를 포함하는 것을 특징으로 하는 방법.
- 제12항에 있어서, 상기 제2 전기적 전도성 물질을 상기 제2 비어 내로 도입하는 단계는 상기 시드를 전기 도금하는 단계를 포함하는 것을 특징으로 하는 방법.
- 제12항에 있어서, 상기 제2 전기적 전도성 물질을 상기 제2 비어 내로 도입하는 단계는 상기 시드를 무전해 도금하는 단계를 포함하는 것을 특징으로 하는 방법.
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20150031223A (ko) * | 2012-06-15 | 2015-03-23 | 더 보잉 컴파니 | 마이크로센서 패키지 및 그와 관련된 조립 방법 |
US9281217B1 (en) | 2015-01-05 | 2016-03-08 | SK Hynix Inc. | Method of manufacturing semiconductor memory device |
Families Citing this family (49)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8084866B2 (en) | 2003-12-10 | 2011-12-27 | Micron Technology, Inc. | Microelectronic devices and methods for filling vias in microelectronic devices |
US7091124B2 (en) | 2003-11-13 | 2006-08-15 | Micron Technology, Inc. | Methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices |
US20050247894A1 (en) | 2004-05-05 | 2005-11-10 | Watkins Charles M | Systems and methods for forming apertures in microfeature workpieces |
US7232754B2 (en) | 2004-06-29 | 2007-06-19 | Micron Technology, Inc. | Microelectronic devices and methods for forming interconnects in microelectronic devices |
US7083425B2 (en) | 2004-08-27 | 2006-08-01 | Micron Technology, Inc. | Slanted vias for electrical circuits on circuit boards and other substrates |
US7300857B2 (en) | 2004-09-02 | 2007-11-27 | Micron Technology, Inc. | Through-wafer interconnects for photoimager and memory wafers |
US7271482B2 (en) | 2004-12-30 | 2007-09-18 | Micron Technology, Inc. | Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods |
US7851348B2 (en) | 2005-06-14 | 2010-12-14 | Abhay Misra | Routingless chip architecture |
US7838997B2 (en) | 2005-06-14 | 2010-11-23 | John Trezza | Remote chip attachment |
US7560813B2 (en) | 2005-06-14 | 2009-07-14 | John Trezza | Chip-based thermo-stack |
US7767493B2 (en) | 2005-06-14 | 2010-08-03 | John Trezza | Post & penetration interconnection |
US7989958B2 (en) | 2005-06-14 | 2011-08-02 | Cufer Assett Ltd. L.L.C. | Patterned contact |
US7781886B2 (en) | 2005-06-14 | 2010-08-24 | John Trezza | Electronic chip contact structure |
US20060281303A1 (en) * | 2005-06-14 | 2006-12-14 | John Trezza | Tack & fuse chip bonding |
US7687400B2 (en) | 2005-06-14 | 2010-03-30 | John Trezza | Side stacking apparatus and method |
US8456015B2 (en) | 2005-06-14 | 2013-06-04 | Cufer Asset Ltd. L.L.C. | Triaxial through-chip connection |
US7786592B2 (en) * | 2005-06-14 | 2010-08-31 | John Trezza | Chip capacitive coupling |
US7795134B2 (en) | 2005-06-28 | 2010-09-14 | Micron Technology, Inc. | Conductive interconnect structures and formation methods using supercritical fluids |
US7863187B2 (en) | 2005-09-01 | 2011-01-04 | Micron Technology, Inc. | Microfeature workpieces and methods for forming interconnects in microfeature workpieces |
US7262134B2 (en) | 2005-09-01 | 2007-08-28 | Micron Technology, Inc. | Microfeature workpieces and methods for forming interconnects in microfeature workpieces |
US7749899B2 (en) | 2006-06-01 | 2010-07-06 | Micron Technology, Inc. | Microelectronic workpieces and methods and systems for forming interconnects in microelectronic workpieces |
US7687397B2 (en) * | 2006-06-06 | 2010-03-30 | John Trezza | Front-end processed wafer having through-chip connections |
US7629249B2 (en) | 2006-08-28 | 2009-12-08 | Micron Technology, Inc. | Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods |
US7902643B2 (en) | 2006-08-31 | 2011-03-08 | Micron Technology, Inc. | Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods |
US7670874B2 (en) * | 2007-02-16 | 2010-03-02 | John Trezza | Plated pillar package formation |
SG150410A1 (en) | 2007-08-31 | 2009-03-30 | Micron Technology Inc | Partitioned through-layer via and associated systems and methods |
US7884015B2 (en) | 2007-12-06 | 2011-02-08 | Micron Technology, Inc. | Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods |
JP2009181981A (ja) * | 2008-01-29 | 2009-08-13 | Renesas Technology Corp | 半導体装置の製造方法および半導体装置 |
FR2928032B1 (fr) * | 2008-02-22 | 2011-06-17 | Commissariat Energie Atomique | Composant de connexion muni d'inserts avec cales compensatrices. |
US7973416B2 (en) * | 2008-05-12 | 2011-07-05 | Texas Instruments Incorporated | Thru silicon enabled die stacking scheme |
US8609466B2 (en) | 2009-07-15 | 2013-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cap and substrate electrical connection at wafer level |
US8242591B2 (en) | 2009-08-13 | 2012-08-14 | International Business Machines Corporation | Electrostatic chucking of an insulator handle substrate |
US9082762B2 (en) * | 2009-12-28 | 2015-07-14 | International Business Machines Corporation | Electromigration-resistant under-bump metallization of nickel-iron alloys for Sn-rich solder bumps in Pb-free flip-clip |
US9219023B2 (en) * | 2010-01-19 | 2015-12-22 | Globalfoundries Inc. | 3D chip stack having encapsulated chip-in-chip |
KR101677507B1 (ko) | 2010-09-07 | 2016-11-21 | 삼성전자주식회사 | 반도체 장치의 제조 방법 |
US8313982B2 (en) | 2010-09-20 | 2012-11-20 | Texas Instruments Incorporated | Stacked die assemblies including TSV die |
US8519515B2 (en) * | 2011-04-13 | 2013-08-27 | United Microlectronics Corp. | TSV structure and method for forming the same |
CA2882646A1 (en) * | 2012-09-05 | 2014-03-13 | Research Triangle Institute | Electronic devices utilizing contact pads with protrusions and methods for fabrication |
KR102190382B1 (ko) | 2012-12-20 | 2020-12-11 | 삼성전자주식회사 | 반도체 패키지 |
KR102230011B1 (ko) * | 2013-12-23 | 2021-03-19 | 인텔 코포레이션 | 쓰루 바디 비아 격리된 동축 커패시터 및 그 형성 기술 |
US9252148B2 (en) | 2014-01-22 | 2016-02-02 | Micron Technology, Inc. | Methods and apparatuses with vertical strings of memory cells and support circuitry |
US9123738B1 (en) * | 2014-05-16 | 2015-09-01 | Xilinx, Inc. | Transmission line via structure |
US9318376B1 (en) * | 2014-12-15 | 2016-04-19 | Freescale Semiconductor, Inc. | Through substrate via with diffused conductive component |
JP6489942B2 (ja) * | 2015-05-29 | 2019-03-27 | 東芝メモリ株式会社 | 半導体デバイスの製造方法 |
ES2835719T3 (es) * | 2016-09-22 | 2021-06-23 | Ge Renewable Tech | Dispositivo y método combinados de extrusión de polvo y enfriamiento |
US9991215B1 (en) * | 2017-01-19 | 2018-06-05 | Nanya Technology Corporation | Semiconductor structure with through substrate via and manufacturing method thereof |
US10566253B2 (en) | 2017-11-30 | 2020-02-18 | Nanya Technology Corporation | Electronic device and electrical testing method thereof |
US11557545B2 (en) * | 2018-12-04 | 2023-01-17 | Qorvo Us, Inc. | Monolithic microwave integrated circuit (MMIC) with embedded transmission line (ETL) ground shielding |
US10950519B2 (en) * | 2019-05-31 | 2021-03-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit package and method |
Family Cites Families (140)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3312878A (en) * | 1965-06-01 | 1967-04-04 | Ibm | High speed packaging of miniaturized circuit modules |
US3720309A (en) * | 1971-12-07 | 1973-03-13 | Teledyne Inc | Method and apparatus for sorting semiconductor dice |
US4915494A (en) * | 1988-07-06 | 1990-04-10 | Harris Corporation | Carbon-carbon mirror for space applications |
US5089880A (en) * | 1989-06-07 | 1992-02-18 | Amdahl Corporation | Pressurized interconnection system for semiconductor chips |
US5399898A (en) * | 1992-07-17 | 1995-03-21 | Lsi Logic Corporation | Multi-chip semiconductor arrangements using flip chip dies |
US5089055A (en) * | 1989-12-12 | 1992-02-18 | Takashi Nakamura | Survivable solar power-generating systems for use with spacecraft |
JPH0831617B2 (ja) | 1990-04-18 | 1996-03-27 | 三菱電機株式会社 | 太陽電池及びその製造方法 |
JP2918307B2 (ja) | 1990-08-07 | 1999-07-12 | 沖電気工業株式会社 | 半導体記憶素子 |
JPH0817880B2 (ja) * | 1990-11-28 | 1996-02-28 | 帝人株式会社 | プレスクッション材 |
KR940006696B1 (ko) * | 1991-01-16 | 1994-07-25 | 금성일렉트론 주식회사 | 반도체 소자의 격리막 형성방법 |
JPH0594993A (ja) * | 1991-10-02 | 1993-04-16 | Mitsubishi Electric Corp | 半導体素子 |
US5308784A (en) * | 1991-10-02 | 1994-05-03 | Samsung Electronics Co., Ltd. | Semiconductor device and method for making the same |
US5427834A (en) | 1991-10-31 | 1995-06-27 | Idm Enterprises | Waterproof textile |
US5603847A (en) * | 1993-04-07 | 1997-02-18 | Zycon Corporation | Annular circuit components coupled with printed circuit board through-hole |
GB9400384D0 (en) | 1994-01-11 | 1994-03-09 | Inmos Ltd | Circuit connection in an electrical assembly |
US5470787A (en) | 1994-05-02 | 1995-11-28 | Motorola, Inc. | Semiconductor device solder bump having intrinsic potential for forming an extended eutectic region and method for making and using the same |
JPH0837395A (ja) | 1994-07-21 | 1996-02-06 | Matsushita Electric Ind Co Ltd | 半導体チップ供給装置および供給方法 |
US5523628A (en) * | 1994-08-05 | 1996-06-04 | Hughes Aircraft Company | Apparatus and method for protecting metal bumped integrated circuit chips during processing and for providing mechanical support to interconnected chips |
US5587119A (en) | 1994-09-14 | 1996-12-24 | E-Systems, Inc. | Method for manufacturing a coaxial interconnect |
DE4433845A1 (de) | 1994-09-22 | 1996-03-28 | Fraunhofer Ges Forschung | Verfahren zur Herstellung einer dreidimensionalen integrierten Schaltung |
US5598965A (en) * | 1994-11-03 | 1997-02-04 | Scheu; William E. | Integrated circuit, electronic component chip removal and replacement system |
US5608264A (en) * | 1995-06-05 | 1997-03-04 | Harris Corporation | Surface mountable integrated circuit with conductive vias |
US5814889A (en) | 1995-06-05 | 1998-09-29 | Harris Corporation | Intergrated circuit with coaxial isolation and method |
US5635014A (en) * | 1995-06-19 | 1997-06-03 | Gr Systems | Press apparatus and methods for fusing overlapped thermoplastic sheet materials |
JP3498877B2 (ja) * | 1995-12-05 | 2004-02-23 | 株式会社東芝 | 半導体製造装置および半導体装置の製造方法 |
JP2739855B2 (ja) | 1995-12-14 | 1998-04-15 | 日本電気株式会社 | 半導体装置およびその製造方法 |
US5973396A (en) | 1996-02-16 | 1999-10-26 | Micron Technology, Inc. | Surface mount IC using silicon vias in an area array format or same size as die array |
US5727834A (en) * | 1996-03-22 | 1998-03-17 | Weselowski; James | Safety attachment for a lifting hook |
US6310484B1 (en) * | 1996-04-01 | 2001-10-30 | Micron Technology, Inc. | Semiconductor test interconnect with variable flexure contacts |
US5872338A (en) | 1996-04-10 | 1999-02-16 | Prolinx Labs Corporation | Multilayer board having insulating isolation rings |
US5793116A (en) | 1996-05-29 | 1998-08-11 | Mcnc | Microelectronic packaging using arched solder columns |
JP2790122B2 (ja) * | 1996-05-31 | 1998-08-27 | 日本電気株式会社 | 積層回路基板 |
GB2316225A (en) * | 1996-08-06 | 1998-02-18 | Northern Telecom Ltd | Semiconductor photodetector packaging |
JP3176307B2 (ja) * | 1997-03-03 | 2001-06-18 | 日本電気株式会社 | 集積回路装置の実装構造およびその製造方法 |
JP3920399B2 (ja) * | 1997-04-25 | 2007-05-30 | 株式会社東芝 | マルチチップ半導体装置用チップの位置合わせ方法、およびマルチチップ半導体装置の製造方法・製造装置 |
JPH10335383A (ja) | 1997-05-28 | 1998-12-18 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
JPH11166935A (ja) | 1997-09-25 | 1999-06-22 | Canon Inc | 光検出または照射用の光プローブと該プローブを備えた近視野光学顕微鏡、及該光プローブの製造方法とその製造に用いる基板 |
US6620731B1 (en) * | 1997-12-18 | 2003-09-16 | Micron Technology, Inc. | Method for fabricating semiconductor components and interconnects with contacts on opposing sides |
US6075710A (en) * | 1998-02-11 | 2000-06-13 | Express Packaging Systems, Inc. | Low-cost surface-mount compatible land-grid array (LGA) chip scale package (CSP) for packaging solder-bumped flip chips |
JP3102405B2 (ja) * | 1998-02-13 | 2000-10-23 | 日本電気株式会社 | 半導体装置の製造方法 |
JPH11251316A (ja) * | 1998-03-02 | 1999-09-17 | Toshiba Corp | マルチチップ半導体装置の製造方法 |
US5962922A (en) | 1998-03-18 | 1999-10-05 | Wang; Bily | Cavity grid array integrated circuit package |
US6222276B1 (en) * | 1998-04-07 | 2001-04-24 | International Business Machines Corporation | Through-chip conductors for low inductance chip-to-chip integration and off-chip connections |
TW434756B (en) * | 1998-06-01 | 2001-05-16 | Hitachi Ltd | Semiconductor device and its manufacturing method |
US7107666B2 (en) | 1998-07-23 | 2006-09-19 | Bh Electronics | Method of manufacturing an ultra-miniature magnetic device |
US6118181A (en) * | 1998-07-29 | 2000-09-12 | Agilent Technologies, Inc. | System and method for bonding wafers |
US6121576A (en) | 1998-09-02 | 2000-09-19 | Micron Technology, Inc. | Method and process of contact to a heat softened solder ball array |
US6380023B2 (en) * | 1998-09-02 | 2002-04-30 | Micron Technology, Inc. | Methods of forming contacts, methods of contacting lines, methods of operating integrated circuitry, and integrated circuits |
US6122187A (en) | 1998-11-23 | 2000-09-19 | Micron Technology, Inc. | Stacked integrated circuits |
JP4590052B2 (ja) * | 1998-12-04 | 2010-12-01 | キヤノン株式会社 | 太陽電池屋根の構造、太陽光発電装置及び建築物 |
JP3847494B2 (ja) | 1998-12-14 | 2006-11-22 | シャープ株式会社 | 二次元画像検出器の製造方法 |
JP2000223653A (ja) * | 1999-02-02 | 2000-08-11 | Rohm Co Ltd | チップ・オン・チップ構造の半導体装置およびそれに用いる半導体チップ |
US6207475B1 (en) * | 1999-03-30 | 2001-03-27 | Industrial Technology Research Institute | Method for dispensing underfill and devices formed |
WO2000062652A1 (en) * | 1999-04-20 | 2000-10-26 | Ian Coats Maccoll | Waterproof blanket with integrated storage bag |
US6225206B1 (en) * | 1999-05-10 | 2001-05-01 | International Business Machines Corporation | Flip chip C4 extension structure and process |
JP2000349101A (ja) * | 1999-06-07 | 2000-12-15 | Lintec Corp | 転写用テープおよびその使用方法 |
US6316737B1 (en) | 1999-09-09 | 2001-11-13 | Vlt Corporation | Making a connection between a component and a circuit board |
US6135635A (en) | 1999-10-07 | 2000-10-24 | Miller; Jeffrey | Convertible bag and barrier device |
US6283693B1 (en) * | 1999-11-12 | 2001-09-04 | General Semiconductor, Inc. | Method and apparatus for semiconductor chip handling |
US6756594B2 (en) * | 2000-01-28 | 2004-06-29 | California Institute Of Technology | Micromachined tuned-band hot bolometer emitter |
JP3386029B2 (ja) | 2000-02-09 | 2003-03-10 | 日本電気株式会社 | フリップチップ型半導体装置及びその製造方法 |
JP3394947B2 (ja) * | 2000-02-24 | 2003-04-07 | 日東電工株式会社 | 粘着テープおよび粘着テープ基材 |
US6446317B1 (en) * | 2000-03-31 | 2002-09-10 | Intel Corporation | Hybrid capacitor and method of fabrication therefor |
EP1223612A4 (en) * | 2000-05-12 | 2005-06-29 | Matsushita Electric Ind Co Ltd | PCB FOR SEMICONDUCTOR COMPONENTS, THEIR MANUFACTURING METHOD AND MANUFACTURING OF THE FITTING PLANT FOR THE PCB |
JP2002043502A (ja) * | 2000-07-25 | 2002-02-08 | Toshiba Corp | マルチチップ半導体装置、ならびにマルチチップ半導体装置用チップ及びその製造方法 |
US6938783B2 (en) | 2000-07-26 | 2005-09-06 | Amerasia International Technology, Inc. | Carrier tape |
TW525417B (en) * | 2000-08-11 | 2003-03-21 | Ind Tech Res Inst | Composite through hole structure |
US6577013B1 (en) * | 2000-09-05 | 2003-06-10 | Amkor Technology, Inc. | Chip size semiconductor packages with stacked dies |
US7262082B1 (en) * | 2000-10-13 | 2007-08-28 | Bridge Semiconductor Corporation | Method of making a three-dimensional stacked semiconductor package with a metal pillar and a conductive interconnect in an encapsulant aperture |
US6740576B1 (en) * | 2000-10-13 | 2004-05-25 | Bridge Semiconductor Corporation | Method of making a contact terminal with a plated metal peripheral sidewall portion for a semiconductor chip assembly |
JP2002134545A (ja) | 2000-10-26 | 2002-05-10 | Oki Electric Ind Co Ltd | 半導体集積回路チップ及び基板、並びにその製造方法 |
JP4608763B2 (ja) * | 2000-11-09 | 2011-01-12 | 日本電気株式会社 | 半導体装置 |
EP1217656A1 (en) * | 2000-12-20 | 2002-06-26 | STMicroelectronics S.r.l. | Process for manufacturing components in a semiconductor material with reduction in the starting wafer thickness |
US6557192B2 (en) * | 2001-01-02 | 2003-05-06 | Patent Category Corp. | Sleeping bag with enhancements |
US6737740B2 (en) * | 2001-02-08 | 2004-05-18 | Micron Technology, Inc. | High performance silicon contact for flip chip |
US7242099B2 (en) * | 2001-03-05 | 2007-07-10 | Megica Corporation | Chip package with multiple chips connected by bumps |
JP4118029B2 (ja) | 2001-03-09 | 2008-07-16 | 富士通株式会社 | 半導体集積回路装置とその製造方法 |
JP2002289900A (ja) * | 2001-03-23 | 2002-10-04 | Canon Inc | 集光型太陽電池モジュール及び集光型太陽光発電システム |
WO2002084631A1 (fr) * | 2001-04-11 | 2002-10-24 | Sony Corporation | Procede de transfert d'element, procede de disposition d'element mettant en oeuvre ce procede et procede de production d'un appareil d'affichage d'image |
TW561805B (en) * | 2001-05-16 | 2003-11-11 | Unimicron Technology Corp | Fabrication method of micro-via |
JP2002359386A (ja) * | 2001-05-31 | 2002-12-13 | Canon Inc | 太陽電池ストリング、太陽電池アレイ及び太陽光発電システム |
US6451626B1 (en) * | 2001-07-27 | 2002-09-17 | Charles W.C. Lin | Three-dimensional stacked semiconductor package |
US6635960B2 (en) | 2001-08-30 | 2003-10-21 | Micron Technology, Inc. | Angled edge connections for multichip structures |
US6686654B2 (en) * | 2001-08-31 | 2004-02-03 | Micron Technology, Inc. | Multiple chip stack structure and cooling system |
DE20115945U1 (de) * | 2001-09-27 | 2001-12-13 | Heimbach Gmbh Thomas Josef | Preßpolster |
JP3976541B2 (ja) | 2001-10-23 | 2007-09-19 | 富士通株式会社 | 半導体チップの剥離方法及び装置 |
US6717045B2 (en) * | 2001-10-23 | 2004-04-06 | Leon L. C. Chen | Photovoltaic array module design for solar electric power generation systems |
ITTO20011038A1 (it) * | 2001-10-30 | 2003-04-30 | St Microelectronics Srl | Procedimento per la fabbricazione di una fetta semiconduttrice integrante dispositivi elettronici e una struttura per il disaccoppiamento el |
JP3495727B2 (ja) * | 2001-11-07 | 2004-02-09 | 新光電気工業株式会社 | 半導体パッケージおよびその製造方法 |
US6617507B2 (en) * | 2001-11-16 | 2003-09-09 | First Solar, Llc | Photovoltaic array |
US6834971B2 (en) | 2001-12-04 | 2004-12-28 | The United States Of America As Represented By The Secretary Of The Army | Low-backscatter aperture structure |
US6599778B2 (en) * | 2001-12-19 | 2003-07-29 | International Business Machines Corporation | Chip and wafer integration process using vertical connections |
US6590278B1 (en) * | 2002-01-08 | 2003-07-08 | International Business Machines Corporation | Electronic package |
KR100415282B1 (ko) * | 2002-02-06 | 2004-01-16 | 삼성전자주식회사 | 반도체 소자용 듀얼 다이 접착 장치 |
US6635970B2 (en) * | 2002-02-06 | 2003-10-21 | International Business Machines Corporation | Power distribution design method for stacked flip-chip packages |
US6889427B2 (en) * | 2002-02-15 | 2005-05-10 | Freescale Semiconductor, Inc. | Process for disengaging semiconductor die from an adhesive film |
US6770822B2 (en) * | 2002-02-22 | 2004-08-03 | Bridgewave Communications, Inc. | High frequency device packages and methods |
US6660548B2 (en) * | 2002-03-27 | 2003-12-09 | Intel Corporation | Packaging of multiple active optical devices |
EP2560199B1 (en) * | 2002-04-05 | 2016-08-03 | STMicroelectronics S.r.l. | Process for manufacturing a through insulated interconnection in a body of semiconductor material |
US7135777B2 (en) | 2002-05-03 | 2006-11-14 | Georgia Tech Research Corporation | Devices having compliant wafer-level input/output interconnections and packages using pillars and methods of fabrication thereof |
US6939789B2 (en) | 2002-05-13 | 2005-09-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of wafer level chip scale packaging |
US6689949B2 (en) * | 2002-05-17 | 2004-02-10 | United Innovations, Inc. | Concentrating photovoltaic cavity converters for extreme solar-to-electric conversion efficiencies |
JP2004014657A (ja) * | 2002-06-05 | 2004-01-15 | Toshiba Corp | 半導体チップおよびその製造方法、ならびに三次元積層半導体装置 |
US6704953B2 (en) * | 2002-06-05 | 2004-03-16 | Zelma Lee Fishman | Combination sleeping bag and mat for infants and children |
SG111069A1 (en) * | 2002-06-18 | 2005-05-30 | Micron Technology Inc | Semiconductor devices including peripherally located bond pads, assemblies, packages, and methods |
JP3679786B2 (ja) * | 2002-06-25 | 2005-08-03 | 松下電器産業株式会社 | 半導体装置の製造方法 |
US6919642B2 (en) * | 2002-07-05 | 2005-07-19 | Industrial Technology Research Institute | Method for bonding IC chips to substrates incorporating dummy bumps and non-conductive adhesive and structures formed |
US7023347B2 (en) * | 2002-08-02 | 2006-04-04 | Symbol Technologies, Inc. | Method and system for forming a die frame and for transferring dies therewith |
US6818818B2 (en) | 2002-08-13 | 2004-11-16 | Esmond T. Goei | Concentrating solar energy receiver |
US6986377B2 (en) * | 2002-09-30 | 2006-01-17 | Illinois Tool Works Inc. | Method and apparatus for guiding and sealing split-flange zipper tape to bag making film |
SG111972A1 (en) * | 2002-10-17 | 2005-06-29 | Agency Science Tech & Res | Wafer-level package for micro-electro-mechanical systems |
US7015590B2 (en) * | 2003-01-10 | 2006-03-21 | Samsung Electronics Co., Ltd. | Reinforced solder bump structure and method for forming a reinforced solder bump |
US7013509B2 (en) * | 2003-03-28 | 2006-03-21 | Hickman Robert J | Easy on/easy off pillow and blanket cover |
US6841883B1 (en) * | 2003-03-31 | 2005-01-11 | Micron Technology, Inc. | Multi-dice chip scale semiconductor components and wafer level methods of fabrication |
JP3891299B2 (ja) * | 2003-05-06 | 2007-03-14 | セイコーエプソン株式会社 | 半導体装置の製造方法、半導体装置、半導体デバイス、電子機器 |
TWI229930B (en) * | 2003-06-09 | 2005-03-21 | Advanced Semiconductor Eng | Chip structure |
JP2005026405A (ja) * | 2003-07-01 | 2005-01-27 | Sharp Corp | 貫通電極構造およびその製造方法、半導体チップならびにマルチチップ半導体装置 |
JP4069028B2 (ja) * | 2003-07-16 | 2008-03-26 | 株式会社フジクラ | 貫通電極付き基板、その製造方法及び電子デバイス |
US20050046034A1 (en) * | 2003-09-03 | 2005-03-03 | Micron Technology, Inc. | Apparatus and method for high density multi-chip structures |
US20050104027A1 (en) * | 2003-10-17 | 2005-05-19 | Lazarev Pavel I. | Three-dimensional integrated circuit with integrated heat sinks |
US7276787B2 (en) * | 2003-12-05 | 2007-10-02 | International Business Machines Corporation | Silicon chip carrier with conductive through-vias and method for fabricating same |
US6992824B1 (en) * | 2003-12-27 | 2006-01-31 | Motamedi Manouchehr E | Efficient wave propagation for terahertz imaging and sensing |
KR100569590B1 (ko) * | 2003-12-30 | 2006-04-10 | 매그나칩 반도체 유한회사 | 고주파 반도체 장치 및 그 제조방법 |
TWI254995B (en) * | 2004-01-30 | 2006-05-11 | Phoenix Prec Technology Corp | Presolder structure formed on semiconductor package substrate and method for fabricating the same |
JP4074862B2 (ja) * | 2004-03-24 | 2008-04-16 | ローム株式会社 | 半導体装置の製造方法、半導体装置、および半導体チップ |
JP4439976B2 (ja) * | 2004-03-31 | 2010-03-24 | Necエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US7144759B1 (en) | 2004-04-02 | 2006-12-05 | Celerity Research Pte. Ltd. | Technology partitioning for advanced flip-chip packaging |
JP2006019455A (ja) * | 2004-06-30 | 2006-01-19 | Nec Electronics Corp | 半導体装置およびその製造方法 |
KR20070058445A (ko) * | 2004-07-02 | 2007-06-08 | 스트라스바흐, 인코포레이티드 | 웨이퍼 처리 방법 및 시스템 |
US7157310B2 (en) * | 2004-09-01 | 2007-01-02 | Micron Technology, Inc. | Methods for packaging microfeature devices and microfeature devices formed by such methods |
US7326629B2 (en) * | 2004-09-10 | 2008-02-05 | Agency For Science, Technology And Research | Method of stacking thin substrates by transfer bonding |
JP4813035B2 (ja) * | 2004-10-01 | 2011-11-09 | 新光電気工業株式会社 | 貫通電極付基板の製造方法 |
US9466595B2 (en) * | 2004-10-04 | 2016-10-11 | Intel Corporation | Fabrication of stacked die and structures formed thereby |
US20060070704A1 (en) * | 2004-10-06 | 2006-04-06 | Tropicana Products, Inc. | Vaccum support and transfer of flexible material |
KR100498708B1 (ko) | 2004-11-08 | 2005-07-01 | 옵토팩 주식회사 | 반도체 소자용 전자패키지 및 그 패키징 방법 |
JP4057017B2 (ja) * | 2005-01-31 | 2008-03-05 | 富士通株式会社 | 電子装置及びその製造方法 |
US7170183B1 (en) * | 2005-05-13 | 2007-01-30 | Amkor Technology, Inc. | Wafer level stacked package |
US7989958B2 (en) * | 2005-06-14 | 2011-08-02 | Cufer Assett Ltd. L.L.C. | Patterned contact |
JP4758699B2 (ja) * | 2005-07-21 | 2011-08-31 | コンビ株式会社 | ベビーラック用クッション |
US7528494B2 (en) * | 2005-11-03 | 2009-05-05 | International Business Machines Corporation | Accessible chip stack and process of manufacturing thereof |
-
2006
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20150031223A (ko) * | 2012-06-15 | 2015-03-23 | 더 보잉 컴파니 | 마이크로센서 패키지 및 그와 관련된 조립 방법 |
US9281217B1 (en) | 2015-01-05 | 2016-03-08 | SK Hynix Inc. | Method of manufacturing semiconductor memory device |
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CN101553906B (zh) | 2011-10-26 |
WO2006138491A2 (en) | 2006-12-28 |
US20070161235A1 (en) | 2007-07-12 |
KR101088546B1 (ko) | 2011-12-05 |
CN101553906A (zh) | 2009-10-07 |
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