JP2009135453A - 半導体装置の作製方法、半導体装置及び電子機器 - Google Patents

半導体装置の作製方法、半導体装置及び電子機器 Download PDF

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Publication number
JP2009135453A
JP2009135453A JP2008273215A JP2008273215A JP2009135453A JP 2009135453 A JP2009135453 A JP 2009135453A JP 2008273215 A JP2008273215 A JP 2008273215A JP 2008273215 A JP2008273215 A JP 2008273215A JP 2009135453 A JP2009135453 A JP 2009135453A
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Prior art keywords
layer
region
semiconductor layer
substrate
single crystal
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JP2008273215A
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Japanese (ja)
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JP2009135453A5 (enExample
Inventor
Akihisa Shimomura
明久 下村
Junpei Momo
純平 桃
Fumito Isaka
史人 井坂
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to JP2008273215A priority Critical patent/JP2009135453A/ja
Publication of JP2009135453A publication Critical patent/JP2009135453A/ja
Publication of JP2009135453A5 publication Critical patent/JP2009135453A5/ja
Withdrawn legal-status Critical Current

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    • H10P90/1916—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H10W10/181—

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Electroluminescent Light Sources (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Recrystallisation Techniques (AREA)
JP2008273215A 2007-10-30 2008-10-23 半導体装置の作製方法、半導体装置及び電子機器 Withdrawn JP2009135453A (ja)

Priority Applications (1)

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JP2008273215A JP2009135453A (ja) 2007-10-30 2008-10-23 半導体装置の作製方法、半導体装置及び電子機器

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JP2007281631 2007-10-30
JP2008273215A JP2009135453A (ja) 2007-10-30 2008-10-23 半導体装置の作製方法、半導体装置及び電子機器

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JP2009135453A true JP2009135453A (ja) 2009-06-18
JP2009135453A5 JP2009135453A5 (enExample) 2011-11-17

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US (1) US8435871B2 (enExample)
JP (1) JP2009135453A (enExample)

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KR101240008B1 (ko) * 2009-11-11 2013-03-06 실트로닉 아게 반도체 웨이퍼를 연마하는 방법
JP2014029992A (ja) * 2012-06-25 2014-02-13 Semiconductor Energy Lab Co Ltd 機能性基板の作製方法および半導体装置の作製方法
JP2014107393A (ja) * 2012-11-27 2014-06-09 Mitsubishi Heavy Ind Ltd 常温接合デバイス、常温接合デバイスを有するウェハおよび常温接合方法

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JP5503876B2 (ja) * 2008-01-24 2014-05-28 株式会社半導体エネルギー研究所 半導体基板の製造方法
DE102011002236A1 (de) * 2011-04-21 2012-10-25 Dritte Patentportfolio Beteiligungsgesellschaft Mbh & Co.Kg Verfahren zur Herstellung einer polykristallinen Schicht
JP5464192B2 (ja) * 2011-09-29 2014-04-09 株式会社デンソー 半導体装置の製造方法
US9472776B2 (en) 2011-10-14 2016-10-18 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing sealed structure including welded glass frits
JP2013101923A (ja) 2011-10-21 2013-05-23 Semiconductor Energy Lab Co Ltd 分散組成物の加熱方法、及びガラスパターンの形成方法
US9799829B2 (en) * 2014-07-25 2017-10-24 Semiconductor Energy Laboratory Co., Ltd. Separation method, light-emitting device, module, and electronic device
US10224233B2 (en) 2014-11-18 2019-03-05 Globalwafers Co., Ltd. High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed by He-N2 co-implantation
EP4170705A3 (en) 2014-11-18 2023-10-18 GlobalWafers Co., Ltd. High resistivity semiconductor-on-insulator wafer and a method of manufacturing
EP3367424B1 (en) 2015-03-03 2022-10-19 GlobalWafers Co., Ltd. Charge trapping polycrystalline silicon films on silicon substrates with controllable film stress
EP3739620B1 (en) 2015-06-01 2022-02-16 GlobalWafers Co., Ltd. A silicon germanium-on-insulator structure
SG10201913407TA (en) 2015-11-20 2020-03-30 Globalwafers Co Ltd Manufacturing method of smoothing a semiconductor surface
JP6416140B2 (ja) * 2016-02-12 2018-10-31 信越化学工業株式会社 多結晶シリコン棒および多結晶シリコン棒の選別方法
WO2017155808A1 (en) * 2016-03-07 2017-09-14 Sunedison Semiconductor Limited Semiconductor on insulator structure comprising a plasma nitride layer and method of manufacture thereof
US11848227B2 (en) * 2016-03-07 2023-12-19 Globalwafers Co., Ltd. Method of manufacturing a semiconductor on insulator structure by a pressurized bond treatment
WO2017155806A1 (en) * 2016-03-07 2017-09-14 Sunedison Semiconductor Limited Semiconductor on insulator structure comprising a plasma oxide layer and method of manufacture thereof
SG11201810486VA (en) 2016-06-08 2018-12-28 Globalwafers Co Ltd High resistivity single crystal silicon ingot and wafer having improved mechanical strength
US10269617B2 (en) 2016-06-22 2019-04-23 Globalwafers Co., Ltd. High resistivity silicon-on-insulator substrate comprising an isolation region
EP4210092A1 (en) 2018-06-08 2023-07-12 GlobalWafers Co., Ltd. Method for transfer of a thin layer of silicon
JP7647146B2 (ja) * 2021-02-17 2025-03-18 富士電機株式会社 炭化珪素半導体装置および炭化珪素半導体装置の製造方法
CN120962514B (zh) * 2025-10-23 2026-01-06 苏州大学 一种基于数控路径规划与过程优化的光学元件成形方法

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Cited By (6)

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KR101240008B1 (ko) * 2009-11-11 2013-03-06 실트로닉 아게 반도체 웨이퍼를 연마하는 방법
KR20120127236A (ko) * 2011-05-12 2012-11-21 가부시키가이샤 한도오따이 에네루기 켄큐쇼 발광 장치 및 발광 장치를 이용한 전자 기기
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JP2014029992A (ja) * 2012-06-25 2014-02-13 Semiconductor Energy Lab Co Ltd 機能性基板の作製方法および半導体装置の作製方法
JP2014107393A (ja) * 2012-11-27 2014-06-09 Mitsubishi Heavy Ind Ltd 常温接合デバイス、常温接合デバイスを有するウェハおよび常温接合方法

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US20090117716A1 (en) 2009-05-07

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