JP2008515241A - 相互接続要素の構造体および製造方法と相互接続要素を含む多層配線基板 - Google Patents
相互接続要素の構造体および製造方法と相互接続要素を含む多層配線基板 Download PDFInfo
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- 239000000956 alloy Substances 0.000 description 2
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- 229910052782 aluminium Inorganic materials 0.000 description 2
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- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
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- H05K3/46—Manufacturing multilayer circuits
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Abstract
Description
本願は、2004年10月1日出願の日本国特許出願2004−289722に基づくものであり、その優先権を主張し、その内容全体を引用することにより本明細書の一部をなすものとする。
本発明は、特に、例えば集積回路(「IC」または「チップ」))のような超小型電子ユニットのパッケージングにおける超小型電子部品用の相互接続構造と、他の相互接続構造、例えば、配線基板を含むプリント回路版のような回路パネルとに関する。
Claims (22)
- 第1主表面と、該第1主表面から離隔した第2主表面と、該第1主表面から内部へと延びる複数の凹部とを有する誘電体要素と、
前記複数の凹部に埋め込まれた複数の金属トレースであって、前記第1主表面と実質的に面一の外面と、該外面から離隔した内面とを有する複数の金属トレースと、
前記複数の金属トレースの前記内面から前記誘電体要素を貫通して延びる複数のポストであって、前記第2主表面に露出する頂部を有する前記複数のポストと
を含んでなる相互接続要素。 - 前記複数の金属トレースの前記外面と接触するボンディング金属層をさらに含む請求項1に記載の相互接続要素。
- 前記複数のポストの各々が、各々の相互接続ピラーがそこから延びる前記複数の金属トレースの1つの前記外面の表面積より大きい外面表面積を有する請求項1に記載の相互接続要素。
- 前記誘電体要素が熱可塑性プラスチックを含む請求項1に記載の相互接続要素。
- 前記複数の金属トレースが銅を含み、前記複数のポストが銅を含む請求項1に記載の相互接続要素。
- 前記複数のポストが前記第2主表面から突出している請求項1に記載の相互接続要素。
- 各々の前記ポストが、前記複数の金属トレースから延びる第1金属を含む基部構造を含み、前記各々の前記ポストが、前記第1金属の前記頂部の上に重なるボンド金属をさらに含む請求項6に記載の相互接続要素。
- 前記第1金属が第1融点を有し、前記ボンド金属が前記第1融点より低い第2融点を有する請求項7に記載の相互接続要素。
- 複数の相互接続要素を含む多層相互接続要素であって、各相互接続要素は請求項1に記載されたものであり、前記複数の相互接続要素のうちの第1の要素の前記複数のポストが、前記複数の相互接続要素のうちの第2の要素の前記複数の金属トレースの前記外面に接合される多層相互接続要素。
- 前記複数の相互接続要素のうちの前記第1の要素の前記複数のポストと、前記複数の相互接続要素のうちの前記第2の要素の前記複数の金属トレースとの間に配置されたボンド金属をさらに含む請求項9に記載の多層相互接続要素。
- 前記複数の金属トレースが第1金属を含み、前記複数のポストが第2金属を含み、前記相互接続要素が、前記複数のポストおよび前記複数の金属トレースの各々の間に配置された第3金属をさらに含み、前記第3金属が、前記第2金属を侵すエッチング液によって侵されない組成を有する請求項1に記載の相互接続要素。
- 前記第1金属および前記第2金属が同一金属である請求項11に記載の相互接続要素。
- 相互接続要素の製造方法であって、前記相互接続要素は請求項2に記載されたものであり、
前記複数の金属トレースを含む前記金属層が、キャリア層上に重なるマスク層を介して前記キャリア層上にボンド金属層を選択的に堆積し、前記マスク層を介して前記ボンド金属層上に第2金属層をメッキし、その後に前記マスク層を除去し、前記複数の金属トレースを含む前記金属層上に第2マスク層を作製することによって作製されるステップと、
前記複数のポストが、前記第2マスク層内の開口中に金属をメッキすることによって形成されるステップと、
前記誘電体要素が、層間絶縁層を作製し、前記層間コンタクトピラーの露出面上に接続性を向上するための低融点金属層を作製することによって設けられるステップと
を含む、相互接続要素の製造方法。 - 複数の金属トレースを含む金属層をキャリア層の上に重ねて作製するステップと、
前記金属層および前記キャリア層の上に重ねて誘電体要素を設けるステップであって、前記複数の金属トレースの外面および前記誘電体要素の第1主表面が前記キャリア層に隣接し、前記複数の金属トレースの内面が前記外面から離隔する前記誘電体要素の凹部内に配置されるように構成され、前記誘電体要素が前記第1主表面から離隔する第2主表面を有するステップと、
前記複数の金属トレースの前記内面から少なくとも前記誘電体要素の前記第2主表面まで延びる複数の金属ポストを設けるステップと、
前記キャリア層を除去して、前記誘電体要素の前記第1主表面および前記複数の金属トレースの前記外面を露出させるステップと
を含む、相互接続要素の製造方法。 - 前記複数の金属トレースの前記外面が、前記誘電体要素の前記第1主表面と実質的に面一である請求項14に記載の相互接続要素の製造方法。
- 前記キャリア層が金属を含み、前記複数の金属トレースが、フォトレジストの層に開口をパターン形成し、前記開口内に前記複数の金属トレースをメッキすることによって形成される請求項14に記載の相互接続要素の製造方法。
- 前記複数の金属トレースを前記開口内にメッキする前に、前記キャリア層を除去する前記ステップ中に前記複数の金属トレースが侵されることを、前記キャリア層を除去する前記ステップ中に前記エッチング抵抗層が防止するように、前記キャリア層上にエッチング抵抗層を設けるステップをさらに含む請求項16に記載の相互接続要素の製造方法。
- 前記複数の金属ポストを設けるステップが、前記複数の金属トレースの前記内面の上に重なる金属の層をエッチングすることを含み、前記誘電体要素を設ける前記ステップが、前記複数の金属ポストが前記複数の金属トレースに前記内面から延びるように設けられた後に、前記誘電体要素を形成することを含む請求項14に記載の相互接続要素の製造方法。
- 請求項14に記載された相互接続要素の製造方法を含む、多層相互接続要素の製造方法であって、
前記複数の相互接続要素のうちの第1の要素の前記複数のポストを前記複数の相互接続要素のうちの第2の要素の前記複数の金属トレースの前記外面に同時に接合するステップと、前記相互接続要素のうちの第1の要素の誘電体要素の前記第1主表面を、前記相互接続要素のうちの第2の要素の誘電体要素の第2主表面に接合するステップとをさらに含む多層相互接続要素の製造方法。 - 前記同時に接合するステップが、前記複数の相互接続要素のうちの前記第2の要素の前記複数のポストを前記複数の相互接続要素のうちの第3の要素の前記複数の金属トレースの前記外面に接合する請求項19に記載の多層相互接続要素の製造方法。
- 前記同時に接合するステップが、前記複数の相互接続要素のうちの前記第1の要素の前記複数のポストと前記複数の相互接続要素のうちの前記第2の要素の前記複数の金属トレースとの間に配置されたボンド金属の融着と、前記複数の相互接続要素のうちの前記第2の要素の前記複数のポストと前記複数の相互接続要素のうちの前記第3の要素の前記複数の金属トレースとの間に配置されたボンド金属の融着とを同時に行なうことを含む請求項20に記載の多層相互接続要素の製造方法。
- 金属から作られた複数の配線層が、埋め込まれた状態の層間絶縁層の1つの主要表面上に、前記配線層の主要表面が前記層間絶縁層の前記1つの主要表面と面一になるように作製され、層間コンタクトピラーが、前記層間絶縁層を貫通して、前記層間絶縁層のもう1つの主表面へと到達しそこに露出されるように、前記複数の配線層のもう1つの主表面上の配線層の少なくとも一部分の上に金属から作製され、接続性を向上するための低融点金属層が前記層間コンタクトピラーの露出表面上に作製されるステップと、
1つの配線板の配線層が別の配線板の層間コンタクトピラーと接触し、あるいは1つの配線板の層間コンタクトピラーが別の配線板の層間コンタクトピラーと接触するように、前記作製された複数の配線板が前記層間コンタクトピラーを介して位置合せされた状態にあるときに、隣接する配線板の層間絶縁層同士が融着して一体化されると共に、接続するときに接続性を向上するための低融点金属層を介して熱および圧力を加えることにより、前記接続性を向上するための前記低融点金属層を介して、1つの配線板の配線層が別の配線板の層間コンタクトピラーと接続し、あるいは1つの配線板の層間コンタクトピラーが別の配線板の層間コンタクトピラーに接続されるように、前記複数の作製された配線板が積み重ねて接合されるステップと
を含む、複数の配線板を含む多層配線基板の製造方法。
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Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5310743B2 (ja) * | 2008-12-22 | 2013-10-09 | 富士通株式会社 | 電子部品の製造方法 |
JP2014022715A (ja) * | 2012-07-13 | 2014-02-03 | Samsung Electro-Mechanics Co Ltd | コアレス基板及びその製造方法 |
JP2014082436A (ja) * | 2012-10-15 | 2014-05-08 | Zhuhai Advanced Chip Carriers & Electronic Substrates Solutions Technologies Co Ltd | 誘電厚の向上された制御を備えた多層電子構造体 |
KR20170002322A (ko) * | 2015-06-29 | 2017-01-06 | 삼성전기주식회사 | 다층기판 및 다층기판 제조방법 |
KR101776299B1 (ko) * | 2010-07-02 | 2017-09-07 | 엘지이노텍 주식회사 | 인쇄회로기판 및 그 제조방법 |
KR20190044428A (ko) * | 2017-10-20 | 2019-04-30 | 삼성전기주식회사 | 인쇄회로기판 |
KR20190044420A (ko) * | 2017-10-20 | 2019-04-30 | 삼성전기주식회사 | 인쇄회로기판 |
US10455708B2 (en) | 2015-06-29 | 2019-10-22 | Samsung Electro-Mechanics Co., Ltd. | Multilayered substrate and method for manufacturing the same |
WO2022186037A1 (ja) * | 2021-03-04 | 2022-09-09 | Tdk株式会社 | 多層配線基板及びその製造方法 |
TWI778105B (zh) * | 2017-12-04 | 2022-09-21 | 南韓商三星電機股份有限公司 | 印刷電路板 |
Families Citing this family (37)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7993972B2 (en) * | 2008-03-04 | 2011-08-09 | Stats Chippac, Ltd. | Wafer level die integration and method therefor |
JP2007311642A (ja) * | 2006-05-19 | 2007-11-29 | Sharp Corp | 多層プリント配線板の製造方法 |
US7682972B2 (en) * | 2006-06-01 | 2010-03-23 | Amitec-Advanced Multilayer Interconnect Technoloiges Ltd. | Advanced multilayer coreless support structures and method for their fabrication |
WO2008001915A1 (fr) * | 2006-06-30 | 2008-01-03 | Nec Corporation | Carte de câblage, dispositif à semi-conducteurs l'utilisant et leurs procédés de fabrication |
KR100757910B1 (ko) * | 2006-07-06 | 2007-09-11 | 삼성전기주식회사 | 매립패턴기판 및 그 제조방법 |
KR100894178B1 (ko) * | 2007-09-28 | 2009-04-22 | 삼성전기주식회사 | 인쇄회로기판 제조방법 |
JP5289880B2 (ja) * | 2007-10-12 | 2013-09-11 | 新光電気工業株式会社 | 配線基板 |
TW201032687A (en) * | 2009-02-27 | 2010-09-01 | Hon Hai Prec Ind Co Ltd | Method for leveling surface of LGA substrate |
JP5677179B2 (ja) * | 2011-04-20 | 2015-02-25 | 株式会社フジクラ | 多層回路基板およびその製造方法 |
JP6065359B2 (ja) * | 2011-11-24 | 2017-01-25 | 凸版印刷株式会社 | 貫通電極付き配線基板の製造方法 |
CN104254917B (zh) | 2012-03-26 | 2019-04-09 | 先进封装技术私人有限公司 | 用于半导体封装的多层基底 |
US9440135B2 (en) * | 2012-05-29 | 2016-09-13 | Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. | Multilayer electronic structures with integral vias extending in in-plane direction |
US8866286B2 (en) * | 2012-12-13 | 2014-10-21 | Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. | Single layer coreless substrate |
NL2010077C2 (en) | 2013-01-02 | 2014-07-03 | Univ Delft Tech | Through-polymer via (tpv) and method to manufacture such a via. |
WO2014121300A2 (en) * | 2013-02-04 | 2014-08-07 | American Semiconductor, Inc. | Photonic data transfer assembly |
US20140264938A1 (en) * | 2013-03-14 | 2014-09-18 | Douglas R. Hackler, Sr. | Flexible Interconnect |
JP6150587B2 (ja) * | 2013-03-29 | 2017-06-21 | 東京応化工業株式会社 | パターン形成方法、構造体、櫛型電極の製造方法、及び二次電池 |
US9049791B2 (en) * | 2013-06-07 | 2015-06-02 | Zhuhai Advanced Chip Carriers & Electronic Substrates Solutions Technologies Co. Ltd. | Terminations and couplings between chips and substrates |
CN104244614A (zh) * | 2013-06-21 | 2014-12-24 | 富葵精密组件(深圳)有限公司 | 多层电路板及其制作方法 |
USRE49652E1 (en) | 2013-12-16 | 2023-09-12 | Qualcomm Incorporated | Power saving techniques in computing devices |
JP2016143725A (ja) * | 2015-01-30 | 2016-08-08 | イビデン株式会社 | プリント配線板およびその製造方法 |
JP2016143727A (ja) * | 2015-01-30 | 2016-08-08 | イビデン株式会社 | プリント配線板およびその製造方法 |
JP6932475B2 (ja) * | 2015-03-26 | 2021-09-08 | 住友ベークライト株式会社 | 有機樹脂基板の製造方法、有機樹脂基板および半導体装置 |
US10535633B2 (en) | 2015-07-02 | 2020-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chip package having die structures of different heights and method of forming same |
US9806058B2 (en) * | 2015-07-02 | 2017-10-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chip package having die structures of different heights and method of forming same |
KR102473406B1 (ko) * | 2015-10-23 | 2022-12-02 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
US10257932B2 (en) * | 2016-02-16 | 2019-04-09 | Microsoft Technology Licensing, Llc. | Laser diode chip on printed circuit board |
CN205807211U (zh) * | 2016-06-20 | 2016-12-14 | 冯霞 | 用于容器的发光装置 |
WO2018079198A1 (ja) * | 2016-10-28 | 2018-05-03 | 株式会社村田製作所 | 樹脂回路基板 |
US10593563B2 (en) * | 2017-04-13 | 2020-03-17 | Invensas Corporation | Fan-out wafer level package with resist vias |
CN109729639B (zh) | 2018-12-24 | 2020-11-20 | 奥特斯科技(重庆)有限公司 | 在无芯基板上包括柱体的部件承载件 |
JP7238548B2 (ja) * | 2019-03-29 | 2023-03-14 | Tdk株式会社 | 多層基板用絶縁シート、多層基板および多層基板の製造方法 |
JP7455516B2 (ja) * | 2019-03-29 | 2024-03-26 | Tdk株式会社 | 素子内蔵基板およびその製造方法 |
CN111970810A (zh) * | 2019-05-20 | 2020-11-20 | 庆鼎精密电子(淮安)有限公司 | 多层树脂基板及其制作方法 |
US10905007B1 (en) * | 2019-07-01 | 2021-01-26 | Qorvo Us, Inc. | Contact pads for electronic substrates and related methods |
JP2019204974A (ja) * | 2019-08-21 | 2019-11-28 | 住友ベークライト株式会社 | 有機樹脂基板の製造方法、有機樹脂基板および半導体装置 |
JP7424218B2 (ja) * | 2020-06-12 | 2024-01-30 | トヨタ自動車株式会社 | 配線基板の製造方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07170069A (ja) * | 1993-09-27 | 1995-07-04 | Rogers Corp | 多層回路の製造法 |
JP2002033580A (ja) * | 2000-05-11 | 2002-01-31 | Sumitomo Bakelite Co Ltd | 多層配線板およびその製造方法 |
JP2002176265A (ja) * | 2000-09-28 | 2002-06-21 | Sumitomo Bakelite Co Ltd | 多層配線板およびその製造方法 |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02265243A (ja) | 1989-04-05 | 1990-10-30 | Nec Corp | 多層配線およびその形成方法 |
US5072075A (en) | 1989-06-28 | 1991-12-10 | Digital Equipment Corporation | Double-sided hybrid high density circuit board and method of making same |
US5011580A (en) | 1989-10-24 | 1991-04-30 | Microelectronics And Computer Technology Corporation | Method of reworking an electrical multilayer interconnect |
US5185502A (en) * | 1989-12-01 | 1993-02-09 | Cray Research, Inc. | High power, high density interconnect apparatus for integrated circuits |
US5046238A (en) * | 1990-03-15 | 1991-09-10 | Rogers Corporation | Method of manufacturing a multilayer circuit board |
US5118385A (en) * | 1991-05-28 | 1992-06-02 | Microelectronics And Computer Technology Corporation | Multilayer electrical interconnect fabrication with few process steps |
EP1981317A3 (en) * | 1996-01-11 | 2008-10-29 | Ibiden Co., Ltd. | Multilayer printed wiring board and manufacturing method thereof |
US6262478B1 (en) | 1997-04-08 | 2001-07-17 | Amitec-Advanced Multilayer Interconnect Technologies Ltd. | Electronic interconnect structure and method for manufacturing it |
US6534855B1 (en) * | 1997-08-22 | 2003-03-18 | Micron Technology, Inc. | Wireless communications system and method of making |
US6261941B1 (en) | 1998-02-12 | 2001-07-17 | Georgia Tech Research Corp. | Method for manufacturing a multilayer wiring substrate |
TW585813B (en) * | 1998-07-23 | 2004-05-01 | Toyo Kohan Co Ltd | Clad board for printed-circuit board, multi-layered printed-circuit board, and the fabrication method |
IL128200A (en) | 1999-01-24 | 2003-11-23 | Amitec Advanced Multilayer Int | Chip carrier substrate |
CN1176567C (zh) * | 1999-03-03 | 2004-11-17 | 株式会社大和工业 | 制造多层布线板的方法 |
JP4794714B2 (ja) | 2000-02-08 | 2011-10-19 | ソニー株式会社 | 半導体集積回路装置とその製造方法 |
US6555906B2 (en) | 2000-12-15 | 2003-04-29 | Intel Corporation | Microelectronic package having a bumpless laminated interconnection layer |
US6861757B2 (en) | 2001-09-03 | 2005-03-01 | Nec Corporation | Interconnecting substrate for carrying semiconductor device, method of producing thereof and package of semiconductor device |
US7474538B2 (en) | 2002-05-27 | 2009-01-06 | Nec Corporation | Semiconductor device mounting board, method of manufacturing the same, method of inspecting the same, and semiconductor package |
TW530377B (en) * | 2002-05-28 | 2003-05-01 | Via Tech Inc | Structure of laminated substrate with high integration and method of production thereof |
US6780673B2 (en) * | 2002-06-12 | 2004-08-24 | Texas Instruments Incorporated | Method of forming a semiconductor device package using a plate layer surrounding contact pads |
US7260890B2 (en) * | 2002-06-26 | 2007-08-28 | Georgia Tech Research Corporation | Methods for fabricating three-dimensional all organic interconnect structures |
US7052932B2 (en) * | 2004-02-24 | 2006-05-30 | Chartered Semiconductor Manufacturing Ltd. | Oxygen doped SiC for Cu barrier and etch stop layer in dual damascene fabrication |
US7251884B2 (en) | 2004-04-26 | 2007-08-07 | Formfactor, Inc. | Method to build robust mechanical structures on substrate surfaces |
US7145238B1 (en) | 2004-05-05 | 2006-12-05 | Amkor Technology, Inc. | Semiconductor package and substrate having multi-level vias |
-
2004
- 2004-10-01 JP JP2004289722A patent/JP2006108211A/ja active Pending
-
2005
- 2005-09-30 CN CN2005800388158A patent/CN101076883B/zh not_active Expired - Fee Related
- 2005-09-30 KR KR1020077009477A patent/KR20070059186A/ko not_active Application Discontinuation
- 2005-09-30 US US11/239,744 patent/US7923828B2/en not_active Expired - Fee Related
- 2005-09-30 JP JP2007534852A patent/JP5084509B2/ja not_active Expired - Fee Related
- 2005-09-30 WO PCT/US2005/035459 patent/WO2006039633A2/en active Application Filing
-
2011
- 2011-04-12 US US13/085,126 patent/US8859420B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07170069A (ja) * | 1993-09-27 | 1995-07-04 | Rogers Corp | 多層回路の製造法 |
JP2002033580A (ja) * | 2000-05-11 | 2002-01-31 | Sumitomo Bakelite Co Ltd | 多層配線板およびその製造方法 |
JP2002176265A (ja) * | 2000-09-28 | 2002-06-21 | Sumitomo Bakelite Co Ltd | 多層配線板およびその製造方法 |
Cited By (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5310743B2 (ja) * | 2008-12-22 | 2013-10-09 | 富士通株式会社 | 電子部品の製造方法 |
US8704106B2 (en) | 2008-12-22 | 2014-04-22 | Fujitsu Limited | Ferroelectric component and manufacturing the same |
KR101776299B1 (ko) * | 2010-07-02 | 2017-09-07 | 엘지이노텍 주식회사 | 인쇄회로기판 및 그 제조방법 |
JP2014022715A (ja) * | 2012-07-13 | 2014-02-03 | Samsung Electro-Mechanics Co Ltd | コアレス基板及びその製造方法 |
JP2014082436A (ja) * | 2012-10-15 | 2014-05-08 | Zhuhai Advanced Chip Carriers & Electronic Substrates Solutions Technologies Co Ltd | 誘電厚の向上された制御を備えた多層電子構造体 |
KR20170002322A (ko) * | 2015-06-29 | 2017-01-06 | 삼성전기주식회사 | 다층기판 및 다층기판 제조방법 |
KR101947052B1 (ko) * | 2015-06-29 | 2019-02-12 | 삼성전기주식회사 | 다층기판 및 다층기판 제조방법 |
US10455708B2 (en) | 2015-06-29 | 2019-10-22 | Samsung Electro-Mechanics Co., Ltd. | Multilayered substrate and method for manufacturing the same |
KR20190044420A (ko) * | 2017-10-20 | 2019-04-30 | 삼성전기주식회사 | 인쇄회로기판 |
KR20190044428A (ko) * | 2017-10-20 | 2019-04-30 | 삼성전기주식회사 | 인쇄회로기판 |
KR102442386B1 (ko) * | 2017-10-20 | 2022-09-14 | 삼성전기주식회사 | 인쇄회로기판 |
KR102483613B1 (ko) * | 2017-10-20 | 2023-01-02 | 삼성전기주식회사 | 인쇄회로기판 |
TWI793139B (zh) * | 2017-10-20 | 2023-02-21 | 南韓商三星電機股份有限公司 | 印刷電路板 |
TWI813580B (zh) * | 2017-10-20 | 2023-09-01 | 南韓商三星電機股份有限公司 | 印刷電路板 |
TWI778105B (zh) * | 2017-12-04 | 2022-09-21 | 南韓商三星電機股份有限公司 | 印刷電路板 |
WO2022186037A1 (ja) * | 2021-03-04 | 2022-09-09 | Tdk株式会社 | 多層配線基板及びその製造方法 |
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KR20070059186A (ko) | 2007-06-11 |
JP5084509B2 (ja) | 2012-11-28 |
WO2006039633A3 (en) | 2006-08-24 |
WO2006039633A2 (en) | 2006-04-13 |
CN101076883A (zh) | 2007-11-21 |
CN101076883B (zh) | 2011-01-19 |
US20060079127A1 (en) | 2006-04-13 |
US8859420B2 (en) | 2014-10-14 |
US7923828B2 (en) | 2011-04-12 |
JP2006108211A (ja) | 2006-04-20 |
US20110252637A1 (en) | 2011-10-20 |
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