JP2008034427A - 半導体装置及びその製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 69
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 238000000034 method Methods 0.000 claims description 17
- 239000012535 impurity Substances 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 2
- 238000009751 slip forming Methods 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 23
- 229910052814 silicon oxide Inorganic materials 0.000 description 23
- 229910052581 Si3N4 Inorganic materials 0.000 description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 15
- 230000015572 biosynthetic process Effects 0.000 description 12
- 239000010410 layer Substances 0.000 description 9
- 150000004767 nitrides Chemical class 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/056—Making the transistor the transistor being a FinFET
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- Insulated Gate Type Field-Effect Transistor (AREA)
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Abstract
【解決手段】半導体基板100に形成されたSTI領域103と、STI領域103に囲まれた活性領域と、活性領域を横切るように一方向に形成されたゲート電極12とを備え、半導体基板100は、活性領域とゲート電極12とが重なる領域において、活性領域の半導体基板100に活性領域の長軸方向と平行に形成された二つのゲートトレンチ108及び二つのゲートトレンチ108の間に位置し半導体基板100の一部であるフィン状部100fを有し、ゲート電極12は二つのゲートトレンチ108内に埋め込まれ且つフィン状部100f上にも形成され、フィン状部100fがチャネル領域となっているフィントランジスタを備える。これにより、チャネル領域の幅がゲート長よりも短いフィントランジスタが得られる。
【選択図】図13
Description
11 活性領域
12 ゲート電極
14 ソース領域(コンタクト領域)
15 ドレイン領域(コンタクト領域)
16 チャネル領域
100 半導体基板
100f フィン状部
101 パッド酸化膜
102,113 シリコン窒化膜
103,106 シリコン酸化膜
104 開口
105 窒化膜サイドウォール
107 フォトレジスト
108 ゲートトレンチ
109 犠牲酸化膜
110 ゲート酸化膜
111 DOPOS膜
112 W/WN/WSi膜
114 サイドウォール絶縁膜
115 コンタクト領域
116 層間絶縁膜
117 コンタクトホール
118 コンタクトプラグ
200a,200b 活性領域
201a,201b ゲート領域
202a,202b コンタクト領域
Claims (10)
- ゲート電極下のチャネル領域の幅がゲート長よりも短いフィントランジスタを備えることを特徴とする半導体装置。
- 前記ゲート電極は、半導体基板に間隔を開けて形成された二つのゲートトレンチ内及び前記二つのゲートトレンチによって挟まれることによりフィン状に形成された半導体基板の一部の上に連続的に形成され、前記半導体基板の前記一部が前記チャネル領域であることを特徴とする請求項1に記載の半導体装置。
- 前記チャネル領域の両側にソース領域及びドレイン領域が形成され、前記ソース領域及びドレイン領域の幅が前記チャネル領域の幅より広いことを特徴とする請求項1又は2に記載の半導体装置。
- 半導体基板に形成されたSTI(Shallow Trench Isolation)領域と、
前記STI領域に囲まれた活性領域と、
前記活性領域を横切るように一方向に形成されたゲート電極とを備え、
前記半導体基板は、前記活性領域と前記ゲート電極とが重なる領域において、前記活性領域の半導体基板に前記活性領域の長軸方向と平行に形成された二つのゲートトレンチ及び前記二つのゲートトレンチの間に位置し半導体基板の一部であるフィン状部を有し、
前記ゲート電極は前記二つのゲートトレンチ内に埋め込まれ且つ前記フィン状部上にも形成され、
前記フィン状部がチャネル領域となっているフィントランジスタを備えることを特徴とする半導体装置。 - 前記チャネル領域の幅がゲート長よりも短いことを特徴とする請求項4に記載の半導体装置。
- 少なくとも前記フィン状部の上面及び側面にゲート絶縁膜が形成されていることを特徴とする請求項4又は5に記載の半導体装置。
- 半導体基板上に活性領域となる領域を覆いSTI領域となる領域を露出する開口を有するマスク層を形成する工程と、
前記マスク層を用いて前記STI用のトレンチを形成する工程と、
前記マスク層を除去することなく前記トレンチ及び前記マスク層の前記開口に第1絶縁膜を形成する工程と、
前記マスク層を選択的に除去することにより、前記第1絶縁膜に前記マスク層に対応した第2の開口を形成する工程と、
前記第2の開口の内壁にサイドウォール絶縁膜を形成する工程と、
前記サイドウォール絶縁膜が形成された前記第2の開口に第2絶縁膜を形成する工程と、
ゲート電極が形成される領域の前記サイドウォール絶縁膜を選択的に除去する工程と、
前記第1及び第2絶縁膜をマスクとして前記半導体基板の前記ゲート電極が形成される領域に二つのゲートトレンチを形成するとともに、前記二つのゲートトレンチに挟まれた前記半導体基板の一部でありチャネル領域となるフィン状部を形成する工程と、
少なくとも前記フィン状部の上面及び側面にゲート絶縁膜を形成する工程と、
前記二つのゲートトレンチを埋め込み且つ前記フィン状部の上を覆うゲート電極を形成する工程とを備えることを特徴とする半導体装置の製造方法。 - 前記チャネル領域の幅がゲート長よりも短いことを特徴とする請求項7に記載の半導体装置の製造方法。
- 前記ゲート電極をマスクとして前記半導体基板に不純物をイオン注入することにより、ソース領域及びドレイン領域を形成する工程と、前記ソース及びドレイン領域の表面に前記ゲート絶縁膜形成時に同時に形成されたゲート絶縁膜を除去し、前記ソース及びドレイン領域の表面にコンタクト領域を形成する工程をさらに含むことを特徴とする請求項7又は8に記載の半導体装置の製造方法。
- 前記コンタクト領域の幅が前記チャネル領域の幅より広いことを特徴とする請求項7乃至9のいずれか一項に記載の半導体装置の製造方法。
Priority Applications (3)
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JP2006202937A JP4552908B2 (ja) | 2006-07-26 | 2006-07-26 | 半導体装置の製造方法 |
US11/822,591 US20080023757A1 (en) | 2006-07-26 | 2007-07-09 | Semiconductor device having fin-field effect transistor and manufacturing method thereof |
US12/822,862 US7867856B2 (en) | 2006-07-26 | 2010-06-24 | Method of manufacturing a semiconductor device having fin-field effect transistor |
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JP2006202937A JP4552908B2 (ja) | 2006-07-26 | 2006-07-26 | 半導体装置の製造方法 |
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JP2008034427A true JP2008034427A (ja) | 2008-02-14 |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011151272A (ja) * | 2010-01-22 | 2011-08-04 | Toshiba Corp | 半導体装置及びその製造方法 |
US9818649B2 (en) | 2014-10-17 | 2017-11-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and structure for FinFET isolation |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8866254B2 (en) * | 2008-02-19 | 2014-10-21 | Micron Technology, Inc. | Devices including fin transistors robust to gate shorts and methods of making the same |
JP5555211B2 (ja) | 2011-09-06 | 2014-07-23 | 株式会社東芝 | 半導体装置及びその製造方法 |
US9466669B2 (en) | 2014-05-05 | 2016-10-11 | Samsung Electronics Co., Ltd. | Multiple channel length finFETs with same physical gate length |
US10559690B2 (en) | 2014-09-18 | 2020-02-11 | International Business Machines Corporation | Embedded source/drain structure for tall FinFET and method of formation |
US9634125B2 (en) * | 2014-09-18 | 2017-04-25 | United Microelectronics Corporation | Fin field effect transistor device and fabrication method thereof |
US11075286B2 (en) * | 2016-12-12 | 2021-07-27 | Intel Corporation | Hybrid finfet structure with bulk source/drain regions |
KR102605621B1 (ko) * | 2019-01-25 | 2023-11-23 | 삼성전자주식회사 | 매립 게이트 전극들을 가지는 반도체 소자의 제조 방법 |
US11502163B2 (en) * | 2019-10-23 | 2022-11-15 | Nanya Technology Corporation | Semiconductor structure and fabrication method thereof |
Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5710973A (en) * | 1980-06-24 | 1982-01-20 | Agency Of Ind Science & Technol | Semiconductor device |
JPH07131009A (ja) * | 1993-11-04 | 1995-05-19 | Toshiba Corp | 半導体装置及びその製造方法 |
JPH08181323A (ja) * | 1994-12-27 | 1996-07-12 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP2002151688A (ja) * | 2000-08-28 | 2002-05-24 | Mitsubishi Electric Corp | Mos型半導体装置およびその製造方法 |
JP2003101013A (ja) * | 2001-09-26 | 2003-04-04 | Sharp Corp | 半導体装置およびその製造方法および集積回路および半導体システム |
JP2004128494A (ja) * | 2002-10-01 | 2004-04-22 | Internatl Business Mach Corp <Ibm> | ダマシン法ゲートによるマルチ・メサ型mosfet |
WO2004084292A1 (en) * | 2003-03-20 | 2004-09-30 | Matsushita Electric Industrial Co., Ltd. | Finfet-type semiconductor device and method for fabricating the same |
JP2005086024A (ja) * | 2003-09-09 | 2005-03-31 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2006012924A (ja) * | 2004-06-22 | 2006-01-12 | Sharp Corp | 電界効果トランジスタおよびその製造方法 |
WO2006006438A1 (ja) * | 2004-07-12 | 2006-01-19 | Nec Corporation | 半導体装置及びその製造方法 |
JP2009544150A (ja) * | 2006-07-14 | 2009-12-10 | マイクロン テクノロジー, インク. | 解像度以下のケイ素フィーチャおよびそれを形成するための方法 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4237344B2 (ja) * | 1998-09-29 | 2009-03-11 | 株式会社東芝 | 半導体装置及びその製造方法 |
US20020011612A1 (en) * | 2000-07-31 | 2002-01-31 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
US6800910B2 (en) | 2002-09-30 | 2004-10-05 | Advanced Micro Devices, Inc. | FinFET device incorporating strained silicon in the channel region |
US6764884B1 (en) * | 2003-04-03 | 2004-07-20 | Advanced Micro Devices, Inc. | Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device |
US6943405B2 (en) * | 2003-07-01 | 2005-09-13 | International Business Machines Corporation | Integrated circuit having pairs of parallel complementary FinFETs |
KR100518602B1 (ko) * | 2003-12-03 | 2005-10-04 | 삼성전자주식회사 | 돌출된 형태의 채널을 갖는 모스 트랜지스터 및 그 제조방법 |
US6967175B1 (en) * | 2003-12-04 | 2005-11-22 | Advanced Micro Devices, Inc. | Damascene gate semiconductor processing with local thinning of channel region |
KR100598099B1 (ko) * | 2004-02-24 | 2006-07-07 | 삼성전자주식회사 | 다마신 게이트를 갖는 수직 채널 핀 전계효과 트랜지스터 및 그 제조방법 |
US7154118B2 (en) * | 2004-03-31 | 2006-12-26 | Intel Corporation | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication |
JP2005310921A (ja) | 2004-04-19 | 2005-11-04 | Okayama Prefecture | Mos型半導体装置及びその製造方法 |
KR100605104B1 (ko) * | 2004-05-04 | 2006-07-26 | 삼성전자주식회사 | 핀-펫 소자 및 그 제조 방법 |
JP2006013303A (ja) * | 2004-06-29 | 2006-01-12 | Toshiba Corp | 半導体装置及びその製造方法 |
KR100555573B1 (ko) * | 2004-09-10 | 2006-03-03 | 삼성전자주식회사 | Seg막에 의해 확장된 접합영역을 갖는 반도체 소자 및그의 제조방법 |
-
2006
- 2006-07-26 JP JP2006202937A patent/JP4552908B2/ja active Active
-
2007
- 2007-07-09 US US11/822,591 patent/US20080023757A1/en not_active Abandoned
-
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- 2010-06-24 US US12/822,862 patent/US7867856B2/en active Active
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5710973A (en) * | 1980-06-24 | 1982-01-20 | Agency Of Ind Science & Technol | Semiconductor device |
JPH07131009A (ja) * | 1993-11-04 | 1995-05-19 | Toshiba Corp | 半導体装置及びその製造方法 |
JPH08181323A (ja) * | 1994-12-27 | 1996-07-12 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP2002151688A (ja) * | 2000-08-28 | 2002-05-24 | Mitsubishi Electric Corp | Mos型半導体装置およびその製造方法 |
JP2003101013A (ja) * | 2001-09-26 | 2003-04-04 | Sharp Corp | 半導体装置およびその製造方法および集積回路および半導体システム |
JP2004128494A (ja) * | 2002-10-01 | 2004-04-22 | Internatl Business Mach Corp <Ibm> | ダマシン法ゲートによるマルチ・メサ型mosfet |
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JP2006012924A (ja) * | 2004-06-22 | 2006-01-12 | Sharp Corp | 電界効果トランジスタおよびその製造方法 |
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JP2009544150A (ja) * | 2006-07-14 | 2009-12-10 | マイクロン テクノロジー, インク. | 解像度以下のケイ素フィーチャおよびそれを形成するための方法 |
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JP2011151272A (ja) * | 2010-01-22 | 2011-08-04 | Toshiba Corp | 半導体装置及びその製造方法 |
US8242568B2 (en) | 2010-01-22 | 2012-08-14 | Kabushiki Kaisha Toshiba | Semiconductor device and fabrication method thereof |
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US10522414B2 (en) | 2014-10-17 | 2019-12-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and structure for FinFET isolation |
US10867865B2 (en) | 2014-10-17 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and structure for FinFET isolation |
US11605564B2 (en) | 2014-10-17 | 2023-03-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and structure for FinFET isolation |
Also Published As
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US20100261328A1 (en) | 2010-10-14 |
JP4552908B2 (ja) | 2010-09-29 |
US20080023757A1 (en) | 2008-01-31 |
US7867856B2 (en) | 2011-01-11 |
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