JP2006012924A - 電界効果トランジスタおよびその製造方法 - Google Patents
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Abstract
【解決手段】 シリコン基板1上に、フィン形状に突出して形成されたフィン部3、5を設ける。フィン部3、5のチャネル領域部を被覆したゲート誘電体8を設ける。ゲート誘電体8によってチャネル領域部から絶縁されて、上記チャネル領域部上に形成されたゲート電極4を設ける。シリコン基板1上を覆う絶縁体層2を設ける。フィン部3、5は、シリコン基板1から絶縁体層2を貫通して絶縁体層2の表面より突出して延びるように形成されている。
【選択図】 図1
Description
本発明に係るフィン型のFETの実施の第一形態は、図1に示すように、P型の伝導性を備えたシリコン(半導体)基板1上に、シリコン基板1上から外方に向かって突出してフィン形状に形成されたフィン部3、5を有する、金属−絶縁体−半導体のFETである。上記シリコン基板1の素材としては、半導体装置に使用できる半導体材料であればよく、例えば、ゲルマニウムや、シリコン−ゲルマニウムや、ガリウム−砒素といったものが挙げられる。また、上記フィン形状とは、シリコン基板1の表面方向に沿った水平断面が、帯状であり、かつ、シリコン基板1の表面方向に対し直交する方向の垂直断面が、帯状であるものをいう。
本実施の第二形態では、図5に示すように、ソース領域部5およびドレイン領域部3が、絶縁体層2上において、その表面方向に沿って広がって延びているソース領域拡張部5aおよびドレイン領域拡張部3aを有している。このような実施の第二形態に係るFETの、バルクシリコンウエハ基板1’上での製造プロセスについて説明する。このFETの製造技術は、特に、ゲートアレイまたはメモリ装置などのトランジスタアレイの形成に好適に応用できる。また、バルクシリコンウエハ基板1’は、最終プロセスにて、必要に応じて分割されて、前記シリコン基板1となるものである。
1)バルクシリコンウエハ基板1'上にダブルゲートやトリゲートのFETの実現を簡便化できて、その結果、製造コストがより低くなる。
2)バルク制御されたバルクシリコンウエハ基板1'において完全空乏層を形成して動作するフィン型のFETを形成できる。その結果、閾値下の傾斜がほぼ理想的になり、OFF状態漏電流が低減される。それゆえ、上記FETを用いたLSIの待機電流を低くできる。
3)ソース領域部5およびドレイン領域部3の接合エリアを小さくできて、寄生容量と放電とが低減されて、上記寄生容量や放電による特性劣化を回避できる。
2 絶縁体層
3 ドレイン領域部(フィン部)
4 ゲート電極(フィン部)
5 ソース領域部(フィン部)
8 ゲート誘電体(ゲート誘電体薄膜)
Claims (19)
- 半導体基板上に、フィン形状に突出して形成されたフィン部を有する、金属−絶縁体−半導体の電界効果トランジスタであって、
前記フィン部に、チャネル領域部と、チャネル領域部を挟んでそれぞれ形成されたソース領域部およびドレイン領域部と、
上記フィン部のチャネル領域部を被覆したゲート誘電体薄膜と、
上記ゲート誘電体薄膜によってチャネル領域部から絶縁されて、上記チャネル領域部上に形成されたゲート電極と、
上記半導体基板上を覆う絶縁体層とを含み、
上記フィン部は、上記半導体基板から上記絶縁体層を貫通して上記絶縁体層の表面より突出して延びるように形成されている、ことを特徴とする電界効果トランジスタ。 - 前記チャネル領域部の幅は、上記絶縁体層の表面より突出したフィン部の高さの等倍から2倍までである、請求項1に記載の電界効果トランジスタ。
- 前記チャネル領域部は、半導体基板の表面に対して基本的には90度に近い角度を形成する少なくとも2つの互いにほぼ平行な各平坦面を備えている、請求項1または2に記載の電界効果トランジスタ。
- 前記ゲート電極は、上記チャネル領域部に対し跨ぐように形成されている、請求項1ないし3の何れか1項に記載の電界効果トランジスタ。
- 前記ソース領域部およびドレイン領域部が絶縁体層上にて広がるように形成されている、請求項1ないし4の何れか1項に記載の電界効果トランジスタ。
- 前記半導体基板と接触しているソース領域部/ドレイン領域部の各エリアは、前記半導体基板から突出しているソース領域部/ドレイン領域部の合計エリアよりも小さい、請求項1ないし5の何れか1項に記載の電界効果トランジスタ。
- 前記半導体基板はシリコン基板である、請求項1ないし6の何れか1項に記載の電界効果トランジスタ。
- 前記絶縁体層の表面より突出したフィン部の高さは、100nm〜500nmである、請求項1ないし7の何れか1項に記載の電界効果トランジスタ。
- 前記チャネル領域部の幅は、ゲート電極幅によって決定されている、請求項1ないし8の何れか1項に記載の電界効果トランジスタ。
- 前記フィン部のチャネル領域部の幅は、10nm〜300nmである、請求項1ないし9の何れか1項に記載の電界効果トランジスタ。
- 前記絶縁体層は、厚さ50nm〜1000nmである、請求項1ないし10の何れか1項に記載の電界効果トランジスタ。
- 誘電性絶縁部層によって被覆されているバルク半導体ウエハ基板上に島状の各活性エリアを互いに隣り合うようにそれぞれ設定し、
バルク半導体ウエハ基板の表面上において、上記各活性エリアを電界効果トランジスタの本体領域をフィン部の形状で突出するように露出させて形成するために、上記誘電性絶縁部層を厚さ方向にエッチバックして絶縁体層を形成し、
上記本体領域を、トランジスタの閾値電圧を規定するために十分な不純物原子によってドープしてチャネル領域部を形成し、
上記チャネル領域部上にゲート絶縁膜を堆積または熱成長により形成し、
上記ゲート絶縁膜上に電極材料を堆積させパターン化してゲート電極を形成し、
続いて、ゲート電極を自己整合マスクとして使用して、ゲート電極によって覆われていないフィン部に対し、チャネル領域部の伝導性型とは反対の伝導性型である不純物原子によってドープすることによってソース領域部およびドレイン領域部を形成する、電界効果トランジスタの製造方法。 - 前記バルク半導体ウエハ基板の表面上において、LOCOS、STI、または、トレンチ絶縁部などの誘電性絶縁部層を形成して、前記各活性エリア間を絶縁する、請求項12に記載の電界効果トランジスタの製造方法。
- 前記フィン部のチャネル領域部の幅およびドーピング濃度を、印加されるゲート電極電圧の作用によって、上記チャネル領域部の全体が空乏化するように調節する、請求項12または13に記載の電界効果トランジスタの製造方法。
- 前記フィン部を、100nm〜500nmの高さ分、前記絶縁体層の表面より突出するように形成する、請求項12ないし14の何れか1項に記載の電界効果トランジスタの製造方法。
- 前記フィン部のチャネル領域部を、10nm〜300nmの幅に形成する、請求項12ないし15の何れか1項に記載の電界効果トランジスタの製造方法。
- 前記誘電性絶縁部から絶縁体層を厚さ50nm〜1000nmに残すことにより、前記各活性エリア間を絶縁する、請求項12ないし16の何れか1項に記載の電界効果トランジスタの製造方法。
- 前記ソース領域部およびドレイン領域部を絶縁体層上に広がっているエリアを有するように形成し、
前記バルク半導体ウエハ基板と接触しているソース領域部/ドレイン領域部の各エリアは、絶縁層から突出しているソース領域部/ドレイン領域部の合計エリアよりも小さく設定する、請求項12ないし17の何れか1項に記載の電界効果トランジスタの製造方法。 - 前記広がっているエリアのソース領域部/ドレイン領域部を、側方シリコンエピタキシャル成長によって形成する、請求項18に記載の電界効果トランジスタの製造方法。
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JP2004184182A JP4675585B2 (ja) | 2004-06-22 | 2004-06-22 | 電界効果トランジスタ |
US11/157,077 US7453124B2 (en) | 2004-06-22 | 2005-06-21 | Field effect transistor and fabrication method thereof |
KR1020050053378A KR100714775B1 (ko) | 2004-06-22 | 2005-06-21 | 전계효과트랜지스터 및 그 제조방법 |
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JP2011527124A (ja) * | 2008-07-06 | 2011-10-20 | アイメック | 半導体構造のドープ方法およびその半導体デバイス |
WO2013094430A1 (ja) * | 2011-12-19 | 2013-06-27 | ソニー株式会社 | 固体撮像装置、固体撮像装置の製造方法、および電子機器 |
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KR100714775B1 (ko) | 2007-05-04 |
US20050282342A1 (en) | 2005-12-22 |
TW200625646A (en) | 2006-07-16 |
KR20060046490A (ko) | 2006-05-17 |
JP4675585B2 (ja) | 2011-04-27 |
US7453124B2 (en) | 2008-11-18 |
TWI281750B (en) | 2007-05-21 |
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