US20080023757A1 - Semiconductor device having fin-field effect transistor and manufacturing method thereof - Google Patents

Semiconductor device having fin-field effect transistor and manufacturing method thereof Download PDF

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Publication number
US20080023757A1
US20080023757A1 US11/822,591 US82259107A US2008023757A1 US 20080023757 A1 US20080023757 A1 US 20080023757A1 US 82259107 A US82259107 A US 82259107A US 2008023757 A1 US2008023757 A1 US 2008023757A1
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region
gate
fin
semiconductor device
insulating film
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US11/822,591
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English (en)
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Hiroshi Kujirai
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Micron Memory Japan Ltd
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Elpida Memory Inc
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Assigned to ELPIDA MEMORY, INC. reassignment ELPIDA MEMORY, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KUJIRAI, HIROSHI
Publication of US20080023757A1 publication Critical patent/US20080023757A1/en
Priority to US12/822,862 priority Critical patent/US7867856B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/056—Making the transistor the transistor being a FinFET

Definitions

  • the present invention relates to a semiconductor device and a manufacturing method thereof, and particularly relates to a semiconductor device including a fin field effect transistor and a method of manufacturing the semiconductor method.
  • a gate length of a memory cell transistor is inevitably reduced.
  • the gate length is smaller, then the short channel effect of the transistor disadvantageously becomes more conspicuous, and sub-threshold current is disadvantageously increased.
  • substrate concentration is increased to suppress the short channel effect and the increase of the sub-threshold current, junction leakage increases. Due to this, the DRAM is confronted with a serious problem of deterioration in refresh characteristics.
  • fin-FET fin field effect transistor
  • the fin-FET is expected to be able to realize acceleration of operating rate, increase in ON-current, reduction in power consumption and the like, as compared with a planer transistor.
  • FIG. 14A is a generally plan view of a conventional fin-FET.
  • FIG. 14B is a generally plan view of a fin-FET according to a related art.
  • FIG. 14A shows an active region 200 a , gate regions 201 a , and contact regions 202 a in a standard fin-FET.
  • FIG. 14B shows thinned contact regions, i.e., an active region 200 b , gate regions 201 b , and contact regions 202 b .
  • the active region 200 a shown in FIG. 14A is shown around the active region 200 b by a broken line for comparison with FIG. 14A .
  • the ON-current can be increased because the contact regions 202 a can be secured to be sufficiently large.
  • the short channel effect cannot be suppressed sufficiently because a channel width Wa is large, i.e., larger than a gate length Lga.
  • the fin-FET shown in FIG. 14A there is proposed a method of narrowing a channel width Wb by forming the thinned active region 200 b as shown in FIG. 14B .
  • a gate length Lgb is larger than the channel width Wb, so that the short channel effect can be suppressed.
  • the fin-FET shown in FIG. 14B has the following problems. Not only the channel width Wb but also a width of each contact region 202 b is narrowed. As a result, a contact resistance is increased and ON-current is reduced accordingly.
  • a semiconductor device comprising a fin-shaped channel region and a gate electrode, wherein the channel region located under the gate electrode has a width smaller than a gate length.
  • a semiconductor device comprising an element isolation region formed in a semiconductor substrate; an active region surrounded by the element isolation region and elongated to a first direction; a gate electrode formed in a second direction crossing the first direction; two gate trenches formed in the semiconductor substrate located at a cross region of the active region and the gate electrode, the two gate trenches being elongated to the first direction in parallel; and a fin-shaped part that is a part of the semiconductor substrate and located between the two gate trenches, wherein the gate electrode is buried in the gate trenches and formed on the fin-shaped part, thereby the fin-shaped part serves as a cannel region.
  • the method of manufacturing the semiconductor device according to the present invention includes:
  • a mask layer on a semiconductor substrate, the mask layer covering up a region to serve as an active region and including an opening for exposing a region to serve as an STI region;
  • the width of the channel region under the gate electrode can be made smaller than the gate length.
  • the present invention can realize both suppression of the short channel effect and the increase of the ON-current for the fin field effect transistor by making the width of the channel region under the gate electrode smaller than the gate length.
  • FIGS. 1A and 1B are plan views for explaining a semiconductor device according to an embodiment of the present invention.
  • FIG. 2 is a cross-sectional view showing one process (patterning of a pad oxide film 101 and a silicon nitride film 102 ) in the method of manufacturing the semiconductor device according to the embodiment of the present invention
  • FIG. 3 is a cross-sectional view showing one process (formation of trenches 10 t for STI) in the method of manufacturing the semiconductor device according to the embodiment of the present invention
  • FIG. 4 is a cross-sectional view showing one process (formation of a silicon oxide film 103 ) in the method of manufacturing the semiconductor device according to the embodiment of the present invention
  • FIG. 5 is a cross-sectional view showing one process (formation of an opening 104 ) in the method of manufacturing the semiconductor device according to the embodiment of the present invention
  • FIG. 6 is a cross-sectional view showing one process (formation of a silicon nitride film sidewall 105 ) in the method of manufacturing the semiconductor device according to the embodiment of the present invention
  • FIG. 7 is a plan view showing a state of FIG. 6 in the method of manufacturing a semiconductor device according to the embodiment from above;
  • FIG. 8 is a cross-sectional view showing one process (formation of a silicon oxide film 106 ) in the method of manufacturing the semiconductor device according to the embodiment of the present invention.
  • FIG. 9 is a cross-sectional view showing one process (selectively etching of the silicon nitride film 105 ) in the method of manufacturing the semiconductor device according to the embodiment of the present invention.
  • FIG. 10 is a cross-sectional view showing one process (formation of gate trenches 108 ) in the method of manufacturing the semiconductor device according to the embodiment of the present invention.
  • FIG. 11 is a cross-sectional view showing one process (formation of a sacrificial oxide film 109 ) in the method of manufacturing the semiconductor device according to the embodiment of the present invention.
  • FIG. 12 is a cross-sectional view showing one process (formation of a gate oxide film 110 , formation of a gate electrode 12 and formation of a source region 14 and drain region 15 ) in the method of manufacturing the semiconductor device according to the embodiment of the present invention
  • FIG. 13 is a cross-sectional view showing one process (selectively removing of the silicon oxide film 110 and formation of contact plugs 118 ) in the method of manufacturing the semiconductor device according to the embodiment of the present invention
  • FIG. 14A is a generally plan view of a conventional fin-FET and FIG. 14B is a generally plan view of a fin-FET according to a related art;
  • FIG. 15 is a block diagram showing a data processing system using the DRAM that the present invention is applied.
  • a configuration of the memory cell transistor in the DRAM formed according to the embodiment of the present invention will first be described in detail.
  • FIG. 1A is a plan view showing an STI region (an element isolation region) 10 and a plurality of active regions 11 separated from one another by the STI region 10 in a memory cell region according to the embodiment. Generally, a plurality of active regions are arranged almost equally in the memory cell region. The same is true for the embodiment as shown in FIG. 1A .
  • FIG. 1B is a plan view showing one of the active regions 11 shown in FIG. 1A and the STI region 11 around the active region 11 .
  • Gate trenches 12 are formed in one direction to cross the active region 11 .
  • a source region 14 and drain regions 15 (each of which is also referred to as “contact region”) are formed in both ends of the active region 11 and between the two gate electrodes 12 .
  • the source region and the drain region are often reversed depending on whether a read-in operation or a read-out operation is performed.
  • a central region is the source region 14
  • regions on both sides of the central region are the drain regions 15
  • the memory cell transistor is an N-channel transistor.
  • a channel region 16 having a width W smaller than a gate length Lg is formed under each of the gate electrodes 12 .
  • width W of the channel region 16 By making the width W of the channel region 16 smaller than the gate length Lg, it is possible to suppress the short channel effect, to secure sufficiently large magnitudes for the contact regions 14 and 15 , and to prevent reduction in ON-current.
  • FIGS. 2 to 6 and 8 to 14 are step views schematically showing steps of manufacturing the semiconductor device according to the embodiment.
  • three cross sectional views from the left correspond to a section A-A′, a section B-B′, and a section C-C′ taken along a line A-A′, a line B-B′, and a line C-C′ of FIG. 1B , respectively.
  • a pad oxide film 101 having a thickness of about 9 nm and a silicon nitride film 102 having a thickness of about 120 nm are formed on the semiconductor substrate 100 .
  • the pad oxide film 101 and the silicon nitride film 102 are dry-etched and patterned into shape corresponding to the active region 11 shown in FIGS. 1A and 1B by well-known photolithography.
  • the silicon oxide film 101 and the silicon nitride film 102 serve as a mask layer covering up a region to serve as the active region 11 and including opening for exposing an STI formation region.
  • a surface of the semiconductor substrate 100 is slightly etched as shown in the section A-A′ and the section B-B′.
  • an STI trench 10 t having a depth of about 250 nm are formed in the semiconductor substrate 13 .
  • an upper surface of the silicon nitride film 102 is chipped by about 50 nm.
  • a silicon oxide film 103 having a thickness of about 400 nm is formed on an entire surface including interior of the trench lot by HDP-CVD (High Density Plasma-Chemical Vapor Deposition) Thereafter, the silicon oxide film 103 is polished and removed by CMP (Chemical Mechanical Polishing) while using the silicon nitride film 102 as a stopper.
  • HDP-CVD High Density Plasma-Chemical Vapor Deposition
  • a native oxide film is removed by wet etching.
  • the silicon nitride film 102 is removed by wet etching using a hot phosphoric acid at about 160° C.
  • an opening 104 corresponding to the active region 11 is formed on the pad oxide film 101 .
  • a height from the surface of the semiconductor substrate 100 to a surface of the silicon oxide film 103 is preferably equal to or smaller than 70 nm.
  • etch-back is performed, thereby forming a silicon nitride film sidewall 105 on an inner side surface of the opening 104 .
  • FIG. 7 is a plan view showing a state of FIG. 6 from above. As shown in FIG. 7 , the silicon nitride film sidewall 105 is formed along an inner periphery of the active region 11 and an interior of the silicon nitride film sidewall 105 corresponds to the opening 104 .
  • a silicon oxide film 106 having a thickness of about 100 nm is formed on the entire surface including the opening 104 surrounded by the silicon nitride film sidewall 105 (see FIG. 6 )
  • the CMP is performed using the silicon nitride film side wall 105 as a stopper. By doing so, a silicon oxide film 106 is buried in the opening 104 .
  • a photoresist including openings for exposing regions in which the gate electrodes 12 are to be formed (see FIG. 1B ) (that is, a photoresist patterned to open the regions in which the gate electrodes 12 are to be formed) 107 is formed, and the silicon nitride film 105 is selectively removed by dry etching.
  • surfaces of the silicon oxide films 103 and 106 are also etched.
  • corners of the silicon oxide films 106 and 103 are chipped because the corners are etched more easily.
  • etching for silicon oxide films is performed so as to remove the pad oxide film 101 exposed between the silicon oxide films 103 and 106 .
  • gate trenches 108 each having a depth of about 100 nm are formed in the semiconductor substrate 100 by isotropic etching.
  • an etch rate of etching the semiconductor substrate 100 is preferably about 1.5 times as fast as that of etching the oxide films 103 and 106 .
  • the silicon oxide films 103 and 106 are also etched.
  • the two trenches 108 and a fin-shaped part 100 f that is a part of the semiconductor substrate 100 held between the two gate trenches 108 are formed on the semiconductor substrate 100 .
  • sacrificial oxidation is performed to form a sacrificial oxide film 109 .
  • the silicon nitride film 105 is removed by wet etching and then the silicon oxide films 103 and 106 are wet-etched, thereby removing the surfaces of the silicon oxide films 103 and 106 , the pad oxide film 101 , and the sacrificial oxide film 109 .
  • a silicon oxide film (gate oxide film) 110 having a thickness of about 6 nm is formed as a gate insulating film.
  • the gate oxide film 110 is formed to cover up both side surfaces and an upper surface of the fin-shaped part 100 f of the semiconductor substrate 100 .
  • a doped polysilicon (DOPOS) film 111 having a thickness of about 100 nm is formed on the entire surface including interiors of the two gate trenches 108 .
  • a W/WN/WSi film 112 including a stack of a tungsten silicide (WSi) film, a tungsten nitride (WN) film, and a tungsten (W) film and a having a thickness of about 70 nm, and a silicon nitride film 113 having a thickness of about 140 nm are formed on the DOPOS film 111 in this order.
  • multilayer films of the DOPOS film 111 , the W/WN/WSi film 112 , and the silicon nitride film 113 are patterned.
  • the gate electrodes 12 each having a part of an electrode material buried in the gate trenches 108 are completed.
  • LDD Lightly Doped Drain
  • impurity ions are implanted into the semiconductor substrate 100 , thereby forming the source and drain regions 14 and 15 .
  • an interlayer insulating film 116 is formed.
  • contact holes 117 are opened in the interlayer insulating film 116 , and contact plugs 118 are formed in the respective contact holes 117 .
  • memory cell capacitors, wirings and the like are formed by ordinary method, thus completing the DRAM.
  • the width of each channel region is made smaller than the gate length in the fin field effect transistor, whereby the short channel effect can be suppressed. Furthermore, magnitudes of the contact regions (source and drain regions) do not depend on the width of each channel region. It is, therefore, possible to secure necessary areas for the contact regions (source and drain regions) and prevent reduction in the ON-current.
  • the present invention can preferably apply to the semiconductor memory device, especially a DRAM.
  • FIG. 15 is a block diagram showing a data processing system using the DRAM that the present invention is applied.
  • the data processing system 300 shown in FIG. 15 includes a data processor 320 and a DRAM 330 that the present invention is applied are connected to each other via a system bus 310 .
  • the data processor 320 can be selected from at least a microprocessor (MPU) and a digital signal processor (DSP).
  • MPU microprocessor
  • DSP digital signal processor
  • FIG. 15 although the data processor 320 and the DRAM 330 are connected via the system bus 310 in order to simplify the diagram, they can be connected via not the system bus 310 but a local bus.
  • FIG. 15 although only one set of system bus 310 is employed in the data processing system 300 in order to simplify the diagram, a serial bus or a parallel bus connected to the system bus 310 via connectors can be provided. As shown in FIG. 15 , a storage device 340 , an I/O device 350 , and a ROM 360 are connected to the system bus 310 . However, they are not essential element for the data processing system 300 .
  • the storage device 340 can be selected from at least a hard disk drive, an optical disk drive, and flash memory device.
  • the I/O device 350 can be selected from a display device such as a liquid crystal display (LCD) and an input device such as a key board or a mouse.
  • the I/O device 350 can consists of either input or output device. Further, although each one element is provided as shown in FIG. 15 , two or more same elements can be provided in the data processing system.
  • the present invention is not limited to the memory but is applicable to logic-related devices.

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090206443A1 (en) * 2008-02-19 2009-08-20 Micron Technology, Inc. Devices including fin transistors robust to gate shorts and methods of making the same
US8860104B2 (en) 2011-09-06 2014-10-14 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing same
US20200243375A1 (en) * 2019-01-25 2020-07-30 Samsung Electronics Co., Ltd. Method of manufacturing semiconductor device having buried gate electrodes
US20220102484A1 (en) * 2019-10-23 2022-03-31 Nanya Technology Corporation Method of fabricating semiconductor structure

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5166458B2 (ja) * 2010-01-22 2013-03-21 株式会社東芝 半導体装置及びその製造方法
US9466669B2 (en) 2014-05-05 2016-10-11 Samsung Electronics Co., Ltd. Multiple channel length finFETs with same physical gate length
US10559690B2 (en) 2014-09-18 2020-02-11 International Business Machines Corporation Embedded source/drain structure for tall FinFET and method of formation
US9634125B2 (en) * 2014-09-18 2017-04-25 United Microelectronics Corporation Fin field effect transistor device and fabrication method thereof
US9490176B2 (en) 2014-10-17 2016-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method and structure for FinFET isolation
WO2018111223A1 (en) * 2016-12-12 2018-06-21 Intel Corporation Hybrid finfet structure with bulk source/drain regions

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020011612A1 (en) * 2000-07-31 2002-01-31 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US6764884B1 (en) * 2003-04-03 2004-07-20 Advanced Micro Devices, Inc. Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device
US6800910B2 (en) * 2002-09-30 2004-10-05 Advanced Micro Devices, Inc. FinFET device incorporating strained silicon in the channel region
US20050051825A1 (en) * 2003-09-09 2005-03-10 Makoto Fujiwara Semiconductor device and manufacturing method thereof
US20050136617A1 (en) * 2003-12-03 2005-06-23 Young-Chul Jang MOS transistor having protruded-shape channel and method of fabricating the same
US20050186742A1 (en) * 2004-02-24 2005-08-25 Chang-Woo Oh Vertical channel fin field-effect transistors having increased source/drain contact area and methods for fabricating the same
US6967175B1 (en) * 2003-12-04 2005-11-22 Advanced Micro Devices, Inc. Damascene gate semiconductor processing with local thinning of channel region
US7323375B2 (en) * 2004-05-04 2008-01-29 Samsung Electronics Co., Ltd. Fin field effect transistor device and method of fabricating the same
US7453124B2 (en) * 2004-06-22 2008-11-18 Sharp Kabushiki Kaisha Field effect transistor and fabrication method thereof

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5710973A (en) * 1980-06-24 1982-01-20 Agency Of Ind Science & Technol Semiconductor device
JPH07131009A (ja) * 1993-11-04 1995-05-19 Toshiba Corp 半導体装置及びその製造方法
JPH08181323A (ja) * 1994-12-27 1996-07-12 Hitachi Ltd 半導体装置及びその製造方法
JP4237344B2 (ja) * 1998-09-29 2009-03-11 株式会社東芝 半導体装置及びその製造方法
JP2002151688A (ja) * 2000-08-28 2002-05-24 Mitsubishi Electric Corp Ｍｏｓ型半導体装置およびその製造方法
JP4870291B2 (ja) * 2001-09-26 2012-02-08 シャープ株式会社 半導体装置およびその製造方法および集積回路および半導体システム
US6818952B2 (en) * 2002-10-01 2004-11-16 International Business Machines Corporation Damascene gate multi-mesa MOSFET
JP4922753B2 (ja) * 2003-03-20 2012-04-25 パナソニック株式会社 半導体装置およびその製造方法
US6943405B2 (en) * 2003-07-01 2005-09-13 International Business Machines Corporation Integrated circuit having pairs of parallel complementary FinFETs
US7154118B2 (en) * 2004-03-31 2006-12-26 Intel Corporation Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
JP2005310921A (ja) 2004-04-19 2005-11-04 Okayama Prefecture Ｍｏｓ型半導体装置及びその製造方法
JP2006013303A (ja) * 2004-06-29 2006-01-12 Toshiba Corp 半導体装置及びその製造方法
WO2006006438A1 (ja) * 2004-07-12 2006-01-19 Nec Corporation 半導体装置及びその製造方法
KR100555573B1 (ko) * 2004-09-10 2006-03-03 삼성전자주식회사 Ｓｅｇ막에 의해 확장된 접합영역을 갖는 반도체 소자 및그의 제조방법
US7678648B2 (en) * 2006-07-14 2010-03-16 Micron Technology, Inc. Subresolution silicon features and methods for forming the same

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020011612A1 (en) * 2000-07-31 2002-01-31 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US6800910B2 (en) * 2002-09-30 2004-10-05 Advanced Micro Devices, Inc. FinFET device incorporating strained silicon in the channel region
US6764884B1 (en) * 2003-04-03 2004-07-20 Advanced Micro Devices, Inc. Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device
US20050051825A1 (en) * 2003-09-09 2005-03-10 Makoto Fujiwara Semiconductor device and manufacturing method thereof
US7129550B2 (en) * 2003-09-09 2006-10-31 Kabushiki Kaisha Toshiba Fin-shaped semiconductor device
US20050136617A1 (en) * 2003-12-03 2005-06-23 Young-Chul Jang MOS transistor having protruded-shape channel and method of fabricating the same
US6967175B1 (en) * 2003-12-04 2005-11-22 Advanced Micro Devices, Inc. Damascene gate semiconductor processing with local thinning of channel region
US20050186742A1 (en) * 2004-02-24 2005-08-25 Chang-Woo Oh Vertical channel fin field-effect transistors having increased source/drain contact area and methods for fabricating the same
US7323375B2 (en) * 2004-05-04 2008-01-29 Samsung Electronics Co., Ltd. Fin field effect transistor device and method of fabricating the same
US7453124B2 (en) * 2004-06-22 2008-11-18 Sharp Kabushiki Kaisha Field effect transistor and fabrication method thereof

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090206443A1 (en) * 2008-02-19 2009-08-20 Micron Technology, Inc. Devices including fin transistors robust to gate shorts and methods of making the same
WO2009105317A1 (en) * 2008-02-19 2009-08-27 Micron Technology, Inc. Devices including fin transistors robust to gate shorts and methods of making the same
TWI408752B (zh) * 2008-02-19 2013-09-11 Micron Technology Inc 具有耐閘極短路之鰭式電晶體之元件及其製造方法
US8866254B2 (en) * 2008-02-19 2014-10-21 Micron Technology, Inc. Devices including fin transistors robust to gate shorts and methods of making the same
US9087721B2 (en) 2008-02-19 2015-07-21 Micron Technology, Inc. Devices including fin transistors robust to gate shorts and methods of making the same
US8860104B2 (en) 2011-09-06 2014-10-14 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing same
US20200243375A1 (en) * 2019-01-25 2020-07-30 Samsung Electronics Co., Ltd. Method of manufacturing semiconductor device having buried gate electrodes
US10930544B2 (en) * 2019-01-25 2021-02-23 Samsung Electronics Co., Ltd. Method of manufacturing semiconductor device having buried gate electrodes
US11670537B2 (en) 2019-01-25 2023-06-06 Samsung Electronics Co., Ltd. Method of manufacturing semiconductor device having buried gate electrodes
US20220102484A1 (en) * 2019-10-23 2022-03-31 Nanya Technology Corporation Method of fabricating semiconductor structure
US11848353B2 (en) * 2019-10-23 2023-12-19 Nanya Technology Corporation Method of fabricating semiconductor structure

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