JP2008021796A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP2008021796A JP2008021796A JP2006191830A JP2006191830A JP2008021796A JP 2008021796 A JP2008021796 A JP 2008021796A JP 2006191830 A JP2006191830 A JP 2006191830A JP 2006191830 A JP2006191830 A JP 2006191830A JP 2008021796 A JP2008021796 A JP 2008021796A
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- semiconductor chip
- electrode
- semiconductor device
- external connection
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Abstract
【解決手段】 ダイパッド11a上にIGBTを形成した半導体チップ15とダイオードを形成した半導体チップ16とを搭載する。そして、この半導体チップ15と半導体チップ16とをクリップ20を用いて接続する。クリップ20は、半導体チップ15に形成されたボンディングパッドと平面的に重ならないように配置する。半導体チップ15に形成されたボンディングパッドは、電極とワイヤ28を用いて接続されている。
【選択図】 図4
Description
クリップを用いる構造が開示されている。そして、IGBT用の検知回路が設けられており、この検知回路の端子とIGBTを形成した半導体チップのボンディングパッドとはワイヤを介して接続されている。このとき、ボンディングパッドの直上には、クリップが形成されている。すなわち、ワイヤで接続するボンディングパッド上にクリップが形成されている。ここで、クリップとボンディングパッドとは平面的に重なる領域に配置されているが、クリップと半導体チップの間にスペーサを挟むことにより、ボンディングパッドに接続するワイヤとクリップとが接触しないように構成されている。
本実施の形態1における半導体装置は、例えば、ハイブリッド車などに使用される3相モータの駆動回路に使用されるものである。図1は、本実施の形態1における3相モータの回路図を示す図である。図1において、3相モータ回路は、3相モータ1、パワー半導体装置2、制御回路3を有している。3相モータ1は、位相の異なる3相の電圧により駆動するように構成されている。パワー半導体装置2には、3相に対応してIGBT4とダイオード5が設けられている。すなわち、各単相において、電源電位(Vcc)と3相モータの入力電位との間にIGBT4とダイオード5が逆並列に接続されており、3相モータの入力電位と接地電位(GND)との間にもIGBT4とダイオード5が逆並列に接続されている。すなわち、単相ごとに2つのIGBT4と2つのダイオード5が設けられており、3相で6つのIGBT4と6つのダイオード5が設けられている。そして、個々のIGBT4のゲート電極には、制御回路3が接続されており、この制御回路3によって、IGBT4が制御されるようになっている。このように構成された3相モータの駆動回路において、制御回路3でパワー半導体装置2を構成するIGBT4を流れる電流を制御することにより、3相モータ1を回転させるようになっている。
本実施の形態2では、半導体チップ上に搭載するクリップにおいて、半導体チップに接触するクリップの部分の厚さをその他のクリップの部分の厚さよりも厚くする例について説明する。
本実施の形態3では、半導体装置の樹脂部から引き出されている電極の引き出し位置を変える例について説明する。
半導体装置10の占有面積を低減することができ、半導体装置10の小型化を図ることができる。したがって、本実施の形態3の変形例によれば、半導体装置10の小型化を図ることができるので、半導体装置10を実装基板に実装する密度を向上することができる。
本実施の形態4は、半導体装置の樹脂部と樹脂部から引き出される電極との間に発生するストレスを緩和できる例について説明する。
本実施の形態5は、クリップの外部接続用エミッタ電極との接合部に凸形状の突起を設ける一方、この突起に対応した孔を外部接続用エミッタ電極に設ける例について説明する。
本実施の形態6は、クリップの半導体チップと接触する面側に突起を設ける例について説明する。
本実施の形態7は、放熱効率の向上を図ることができる半導体装置の例について説明する。図54は、本実施の形態7における半導体装置10を示す断面図である。図54に示す本実施の形態7における半導体装置10が前記実施の形態1と異なる点は、クリップ98の上面が樹脂11から露出している点にある。すなわち、半導体チップ15および半導体チップ16上に半田18を介してクリップ98が形成されているが、このクリップ98の上面(半導体チップと接触している面とは反対側の面)が樹脂11から露出している。したがって、本実施の形態7では、ダイパッド11aの下面(裏面)が樹脂11から露出しているとともに、クリップ98の上面が樹脂11から露出していることになる。このように樹脂11からダイパッド11aあるいはクリップ98が露出しているので、半導体装置10の放熱効率を向上させることができる。特に、高出力の半導体装置10であると発生する熱量も多くなるが、本実施の形態7によれば、樹脂11の上下面から熱伝導率の高いダイパッド11aおよびクリップ98が露出しているので、放熱効率を向上させることができる。つまり、高出力の半導体装置10であっても放熱効率を向上できるので、半導体装置10の信頼性向上を図ることができる。
本実施の形態8は半導体装置を実装基板に実装する工程を簡略化できる例について説明する。
2 パワー半導体装置
3 制御回路
4 IGBT
5 ダイオード
10 半導体装置
11 樹脂
11a ダイパッド
12 外部接続用コレクタ電極
12a ねじ止め用開口部
13 外部接続用エミッタ電極
13a ねじ止め用開口部
14 信号電極
15 半導体チップ
16 半導体チップ
17 半田
18 半田
20 クリップ
21 温度検知用電極
22 温度検知用電極
23 外部接続用ゲート電極
24 ケルビン検知用電極
25 電流検知用電極
26 ケルビン検知用電極
27 半田
28 ワイヤ
29 下金型
30 上金型
40 エミッタ電極
41 ボンディングパッド
41a カソード
42 ボンディングパッド
42a アノード電極
43 ボンディングパッド
43a ゲート電極
44 ボンディングパッド
44a コモンエミッタ電極
45 ボンディングパッド
45a センスエミッタ電極
46 コレクタ電極
50 IGBT
51 検知用IGBT
52 温度検知用ダイオード
54 p+型半導体領域
55 n+型半導体領域
56 n−型半導体領域
57 p型半導体領域
58 n+型半導体領域
59 トレンチ溝
60 ゲート絶縁膜
61 n+型半導体領域
62 アノード電極
63 カソード
64 n+型半導体領域
65 n−型半導体領域
66 p型半導体領域
67 p−型半導体領域
68 領域
70 リードフレーム材料
71 厚板領域
72 薄板領域
73 薄板領域
74 リードフレーム
75 リード
76 ダイパッド領域
77 厚板領域
78 薄板領域
80 金型
80a ゲート
85 筐体
86 絶縁層
87 配線基板
88 ねじ
89 ヒートシンク
90 信号処理基板
91 クリップ
92 実装基板
93 ねじ
94 U字部
95 突起
96 孔
97 突起
98 クリップ
99 実装基板
100 押さえ板
101 突起
102 ねじ
103 ねじ
Claims (21)
- IGBTを形成した第1半導体チップとダイオードを形成した第2半導体チップを含む半導体装置であって、
(a)前記第1半導体チップおよび前記第2半導体チップが搭載されたダイパッドと、
(b)前記ダイパッドと一体的に形成された外部接続用コレクタ電極と、
(c)前記IGBTの主面に配置されたエミッタ電極と前記ダイオードの主面に配置されたアノード電極を接続する板状電極と、
(d)前記板状電極と接続する外部接続用エミッタ電極と、
(e)前記IGBTのゲート電極に接続する外部接続用ゲート電極と、
(f)前記IGBTの状態を検知するために設けられた複数の検知用電極と、
(g)前記IGBTを形成した前記第1半導体チップにある複数のボンディングパッドの一部と前記検知用電極、前記複数のボンディングパッドの一部と前記外部接続用ゲート電極とを接続する複数のワイヤとを備え、
前記板状電極と平面的に重ならない領域に前記第1半導体チップの前記複数のボンディングパッドが形成されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置であって、
前記板状電極の直下に前記複数のワイヤが配置されていないことを特徴とする半導体装置。 - 請求項1記載の半導体装置であって、
前記第1半導体チップあるいは前記第2半導体チップに接触している前記板状電極の接触領域の位置よりも、前記第1半導体チップと前記第2半導体チップの間にある前記板状電極のチップ間領域の位置が前記ダイパッドから離れていることを特徴とする半導体装置。 - 請求項1記載の半導体装置であって、
前記板状電極は前記第1半導体チップと前記第2半導体チップの間に位置している部分が上方に突起していることを特徴とする半導体装置。 - 請求項1記載の半導体装置であって、
前記外部接続用エミッタ電極は、前記ダイパッドの第1辺側に形成され、
前記外部接続用コレクタ電極は、前記ダイパッドの前記第1辺側と対向する第2辺側に形成され、
前記外部接続用ゲート電極および複数の前記検知用電極の一部は、前記ダイパッドの前記第1辺側に形成され、複数の前記検知用電極の一部は、前記ダイパッドの前記第2辺側に形成されていることを特徴とする半導体装置。 - 請求項5記載の半導体装置であって、
前記ダイパッドの前記第2辺側に形成されている前記検知用電極は、前記外部接続用コレクタ電極と電気的に接続されていることを特徴とする半導体装置。 - 請求項5記載の半導体装置であって、
前記ダイパッドの前記第1辺側に形成されている前記検知用電極および前記外部接続用ゲート電極は、前記第1半導体チップに形成されている前記複数のボンディングパッドのそれぞれと前記複数のワイヤのそれぞれを用いて接続されていることを特徴とする半導体装置。 - 請求項5記載の半導体装置であって、
前記IGBTを形成した前記第1半導体チップは、前記ダイオードを形成した前記第2半導体チップよりも、前記ダイパッドの前記第1辺に近い側に配置されていることを特徴とする半導体装置。 - 請求項5記載の半導体装置であって、
前記外部接続用エミッタ電極の中心線と前記外部接続用コレクタ電極の中心線とは、一直線上に配置されていないことを特徴とする半導体装置。 - 請求項9記載の半導体装置であって、
前記外部接続用エミッタ電極と前記外部接続用コレクタ電極には、それぞれねじ止め用開口部が形成されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置であって、
複数の前記検知用電極には、前記IGBTを流れる電流を検知する電流検知用電極と前記IGBTの温度を検知する温度検知用電極が含まれることを特徴とする半導体装置。 - 請求項11記載の半導体装置であって、
前記電流検知用電極と前記温度検知用電極の間に前記外部接続用エミッタ電極が形成されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置であって、
前記ダイパッドは、樹脂封止されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置であって、
前記板状電極と前記外部接続用エミッタ電極とは、別々の構造体より構成されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置であって、
前記第1半導体チップと前記第2半導体チップが並んでいる方向とは直交する方向において、前記板状電極の幅は、前記第1半導体チップの幅よりも小さいことを特徴とする半導体装置。 - (a)リードフレームのダイパッド上の第1領域および第2領域にそれぞれ第1半田を形成する工程と、
(b)前記第1半田を形成した前記ダイパッド上の前記第1領域に、エミッタ電極を上にしてIGBTを形成した第1半導体チップを搭載する工程と、
(c)前記第1半田を形成した前記ダイパッド上の前記第2領域に、アノード電極を上にしてダイオードを形成した第2半導体チップを搭載する工程と、
(d)前記(c)工程後、前記第1半導体チップおよび前記第2半導体チップ上に第2半田を形成する工程と、
(e)前記第1半導体チップ上と前記第2半導体チップ上に跨るように板状電極を搭載して、前記第1半導体チップの前記エミッタ電極と前記第2半導体チップの前記アノード電極とを前記第2半田を介して接続する工程と、
(f)前記(e)工程後、熱処理を行い、前記第1半田を溶融して固着することにより、前記ダイパッドと前記第1半導体チップおよび前記第2半導体チップを接続し、前記第2半田を溶融して固着することにより、前記第1半導体チップおよび前記第2半導体チップと前記板状電極を接続する工程と、
(g)前記(f)工程後、前記第1半導体チップの前記板状電極と平面的に重ならない領域に形成されている複数のボンディングパッドと複数のリードとを複数のワイヤを用いて接続する工程とを備えることを特徴とする半導体装置の製造方法。 - 請求項16記載の半導体装置の製造方法であって、
前記(f)工程の前記熱処理は一括リフロー処理であることを特徴とする半導体装置の製造方法。 - 請求項16記載の半導体装置の製造方法であって、
前記板状電極は、前記第1半導体チップあるいは前記第2半導体チップに接触している前記板状電極の第1領域の位置よりも、前記第1半導体チップと前記第2半導体チップの間にある前記板状電極の第2領域の位置が前記ダイパッドから離れている形状をしていることを特徴とする半導体装置の製造方法。 - 請求項16記載の半導体装置の製造方法であって、
前記複数のリードには、前記IGBTの状態を検知するための検知用電極および前記IGBTの外部接続用ゲート電極が含まれていることを特徴とする半導体装置の製造方法。 - 請求項16記載の半導体装置の製造方法であって、さらに、
(h)前記(g)工程後、樹脂封止する工程を備え、
前記(h)工程は、前記第1半導体チップと前記第2半導体チップが並んでいる方向で、かつ、前記第1半導体チップよりも前記第2半導体チップに近い側から樹脂を流入することを特徴とする半導体装置の製造方法。 - 請求項16記載の半導体装置の製造方法であって、
前記第1半田と前記第2半田とは同一の材料から形成されていることを特徴とする半導体装置の製造方法。
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