JP2007511071A - セルフアラインされたダマシンゲート - Google Patents

セルフアラインされたダマシンゲート Download PDF

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Publication number
JP2007511071A
JP2007511071A JP2006538035A JP2006538035A JP2007511071A JP 2007511071 A JP2007511071 A JP 2007511071A JP 2006538035 A JP2006538035 A JP 2006538035A JP 2006538035 A JP2006538035 A JP 2006538035A JP 2007511071 A JP2007511071 A JP 2007511071A
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JP
Japan
Prior art keywords
fin
gate
region
forming
mosfet
Prior art date
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Pending
Application number
JP2006538035A
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English (en)
Japanese (ja)
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JP2007511071A5 (enExample
Inventor
イー． タベリー サイラス
エス． アーメッド シブリー
エス． ブイノスキ マシュー
ダクシナ−マーフィー スリカンテスワラ
クリボカピク ゾラン
ワン ハイホン
ヤン チ−ユ
ユ ビン
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JP2007511071A publication Critical patent/JP2007511071A/ja
Publication of JP2007511071A5 publication Critical patent/JP2007511071A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H10D30/0245—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET] by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)
JP2006538035A 2003-11-04 2004-10-08 セルフアラインされたダマシンゲート Pending JP2007511071A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/699,887 US7029958B2 (en) 2003-11-04 2003-11-04 Self aligned damascene gate
PCT/US2004/033251 WO2005048339A1 (en) 2003-11-04 2004-10-08 Self aligned damascene gate

Publications (2)

Publication Number Publication Date
JP2007511071A true JP2007511071A (ja) 2007-04-26
JP2007511071A5 JP2007511071A5 (enExample) 2007-11-29

Family

ID=34573288

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006538035A Pending JP2007511071A (ja) 2003-11-04 2004-10-08 セルフアラインされたダマシンゲート

Country Status (8)

Country Link
US (1) US7029958B2 (enExample)
JP (1) JP2007511071A (enExample)
KR (1) KR101112046B1 (enExample)
CN (1) CN100524655C (enExample)
DE (1) DE112004002107B4 (enExample)
GB (1) GB2424517B (enExample)
TW (1) TWI376803B (enExample)
WO (1) WO2005048339A1 (enExample)

Cited By (4)

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Publication number Priority date Publication date Assignee Title
JP2008300816A (ja) * 2007-05-29 2008-12-11 Nanya Technology Corp 自己整合式ＦｉｎＦＥＴ装置の製作方法
JP2009544150A (ja) * 2006-07-14 2009-12-10 マイクロン テクノロジー， インク． 解像度以下のケイ素フィーチャおよびそれを形成するための方法
JP5170958B2 (ja) * 2004-01-30 2013-03-27 ルネサスエレクトロニクス株式会社 電界効果型トランジスタおよびその製造方法
JP2013161920A (ja) * 2012-02-03 2013-08-19 Toshiba Corp 不揮発性半導体記憶装置及びその製造方法

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US6686231B1 (en) * 2002-12-06 2004-02-03 Advanced Micro Devices, Inc. Damascene gate process with sacrificial oxide in semiconductor devices
US7041542B2 (en) * 2004-01-12 2006-05-09 Advanced Micro Devices, Inc. Damascene tri-gate FinFET
KR100598099B1 (ko) * 2004-02-24 2006-07-07 삼성전자주식회사 다마신 게이트를 갖는 수직 채널 핀 전계효과 트랜지스터 및 그 제조방법
US7084018B1 (en) 2004-05-05 2006-08-01 Advanced Micro Devices, Inc. Sacrificial oxide for minimizing box undercut in damascene FinFET
WO2006076151A2 (en) * 2004-12-21 2006-07-20 Carnegie Mellon University Lithography and associated methods, devices, and systems
US7858481B2 (en) 2005-06-15 2010-12-28 Intel Corporation Method for fabricating transistor with thinned channel
US7352034B2 (en) * 2005-08-25 2008-04-01 International Business Machines Corporation Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures
US20090321830A1 (en) * 2006-05-15 2009-12-31 Carnegie Mellon University Integrated circuit device, system, and method of fabrication
US7772048B2 (en) * 2007-02-23 2010-08-10 Freescale Semiconductor, Inc. Forming semiconductor fins using a sacrificial fin
US8518767B2 (en) * 2007-02-28 2013-08-27 International Business Machines Corporation FinFET with reduced gate to fin overlay sensitivity
US7902000B2 (en) * 2008-06-04 2011-03-08 International Business Machines Corporation MugFET with stub source and drain regions
JP5404812B2 (ja) * 2009-12-04 2014-02-05 株式会社東芝 半導体装置の製造方法
CN102129982A (zh) * 2010-12-29 2011-07-20 北京大学深圳研究生院 半导体精细图形及鳍形场效应管的fin体的制作方法
CN102956484B (zh) * 2011-08-22 2016-03-30 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
US8569822B2 (en) * 2011-11-02 2013-10-29 Macronix International Co., Ltd. Memory structure
TWI467577B (zh) * 2011-11-02 2015-01-01 Macronix Int Co Ltd 記憶體結構及其製造方法
CN113345952B (zh) 2011-12-22 2025-05-13 英特尔公司 具有颈状半导体主体的半导体器件以及形成不同宽度的半导体主体的方法
US20130200459A1 (en) * 2012-02-02 2013-08-08 International Business Machines Corporation Strained channel for depleted channel semiconductor devices
CN103594342B (zh) * 2012-08-13 2016-03-16 中芯国际集成电路制造(上海)有限公司 形成鳍部的方法和形成鳍式场效应晶体管的方法
CN104465347A (zh) * 2013-09-24 2015-03-25 北大方正集团有限公司 多晶硅表面处理方法及系统
US9653584B2 (en) * 2013-12-23 2017-05-16 Intel Corporation Pre-sculpting of Si fin elements prior to cladding for transistor channel applications
US9711645B2 (en) 2013-12-26 2017-07-18 International Business Machines Corporation Method and structure for multigate FinFET device epi-extension junction control by hydrogen treatment
TWI620234B (zh) * 2014-07-08 2018-04-01 聯華電子股份有限公司 一種製作半導體元件的方法
CN105762071B (zh) * 2014-12-17 2019-06-21 中国科学院微电子研究所 鳍式场效应晶体管及其鳍的制造方法
US10424664B2 (en) * 2016-12-14 2019-09-24 Globalfoundries Inc. Poly gate extension source to body contact

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Publication number Priority date Publication date Assignee Title
JPH0286126A (ja) * 1988-07-11 1990-03-27 Philips Gloeilampenfab:Nv 臭化水素によるシリコンの反応性イオンエッチング
JPH0467681A (ja) * 1990-07-09 1992-03-03 Sony Corp Ｍｉｓ型半導体装置
JPH04303929A (ja) * 1991-01-29 1992-10-27 Micron Technol Inc シリコン基板をトレンチ・エッチングするための方法
JP2000173995A (ja) * 1998-12-03 2000-06-23 Matsushita Electric Ind Co Ltd プラズマエッチング装置およびプラズマエッチング方法
JP2001508937A (ja) * 1996-03-05 2001-07-03 ザ リージェンツ オブ ザ ユニヴァーシティー オブ カリフォルニア プラスチック基板上に薄膜トランジスタを形成させる方法
JP2002025916A (ja) * 2000-07-11 2002-01-25 Toyota Central Res & Dev Lab Inc ヘテロ構造基板およびその製造方法
JP2002270850A (ja) * 2001-03-13 2002-09-20 National Institute Of Advanced Industrial & Technology 二重ゲート電界効果トランジスタ
JP2002270851A (ja) * 2001-03-13 2002-09-20 National Institute Of Advanced Industrial & Technology 半導体装置の製造方法

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US5757038A (en) 1995-11-06 1998-05-26 International Business Machines Corporation Self-aligned dual gate MOSFET with an ultranarrow channel
US6329124B1 (en) * 1999-05-26 2001-12-11 Advanced Micro Devices Method to produce high density memory cells and small spaces by using nitride spacer
US6514378B1 (en) * 2000-03-31 2003-02-04 Lam Research Corporation Method for improving uniformity and reducing etch rate variation of etching polysilicon
US6350696B1 (en) * 2000-09-28 2002-02-26 Advanced Micro Devices, Inc. Spacer etch method for semiconductor device
US7163864B1 (en) 2000-10-18 2007-01-16 International Business Machines Corporation Method of fabricating semiconductor side wall fin
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US6300182B1 (en) 2000-12-11 2001-10-09 Advanced Micro Devices, Inc. Field effect transistor having dual gates with asymmetrical doping for reduced threshold voltage
US6475869B1 (en) 2001-02-26 2002-11-05 Advanced Micro Devices, Inc. Method of forming a double gate transistor having an epitaxial silicon/germanium channel region
US6630388B2 (en) * 2001-03-13 2003-10-07 National Institute Of Advanced Industrial Science And Technology Double-gate field-effect transistor, integrated circuit using the transistor and method of manufacturing the same
US6514849B1 (en) * 2001-04-02 2003-02-04 Advanced Micro Devices, Inc. Method of forming smaller contact size using a spacer hard mask
US6458662B1 (en) 2001-04-04 2002-10-01 Advanced Micro Devices, Inc. Method of fabricating a semiconductor device having an asymmetrical dual-gate silicon-germanium (SiGe) channel MOSFET and a device thereby formed
KR100431489B1 (ko) * 2001-09-04 2004-05-12 한국과학기술원 플래쉬 메모리 소자 및 제조방법
US6657259B2 (en) * 2001-12-04 2003-12-02 International Business Machines Corporation Multiple-plane FinFET CMOS
US6583469B1 (en) * 2002-01-28 2003-06-24 International Business Machines Corporation Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same
US6657252B2 (en) * 2002-03-19 2003-12-02 International Business Machines Corporation FinFET CMOS with NVRAM capability
US6642090B1 (en) * 2002-06-03 2003-11-04 International Business Machines Corporation Fin FET devices from bulk semiconductor and method for forming
US6770516B2 (en) * 2002-09-05 2004-08-03 Taiwan Semiconductor Manufacturing Company Method of forming an N channel and P channel FINFET device on the same semiconductor substrate
US6706571B1 (en) * 2002-10-22 2004-03-16 Advanced Micro Devices, Inc. Method for forming multiple structures in a semiconductor device
US6709982B1 (en) * 2002-11-26 2004-03-23 Advanced Micro Devices, Inc. Double spacer FinFET formation
US6645797B1 (en) * 2002-12-06 2003-11-11 Advanced Micro Devices, Inc. Method for forming fins in a FinFET device using sacrificial carbon layer
US6864164B1 (en) * 2002-12-17 2005-03-08 Advanced Micro Devices, Inc. Finfet gate formation using reverse trim of dummy gate
US6762483B1 (en) * 2003-01-23 2004-07-13 Advanced Micro Devices, Inc. Narrow fin FinFET
US6764884B1 (en) * 2003-04-03 2004-07-20 Advanced Micro Devices, Inc. Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device
US6903967B2 (en) * 2003-05-22 2005-06-07 Freescale Semiconductor, Inc. Memory with charge storage locations and adjacent gate structures
US6855582B1 (en) * 2003-06-12 2005-02-15 Advanced Micro Devices, Inc. FinFET gate formation using reverse trim and oxide polish
US6911383B2 (en) * 2003-06-26 2005-06-28 International Business Machines Corporation Hybrid planar and finFET CMOS devices
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Patent Citations (8)

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Publication number Priority date Publication date Assignee Title
JPH0286126A (ja) * 1988-07-11 1990-03-27 Philips Gloeilampenfab:Nv 臭化水素によるシリコンの反応性イオンエッチング
JPH0467681A (ja) * 1990-07-09 1992-03-03 Sony Corp Ｍｉｓ型半導体装置
JPH04303929A (ja) * 1991-01-29 1992-10-27 Micron Technol Inc シリコン基板をトレンチ・エッチングするための方法
JP2001508937A (ja) * 1996-03-05 2001-07-03 ザ リージェンツ オブ ザ ユニヴァーシティー オブ カリフォルニア プラスチック基板上に薄膜トランジスタを形成させる方法
JP2000173995A (ja) * 1998-12-03 2000-06-23 Matsushita Electric Ind Co Ltd プラズマエッチング装置およびプラズマエッチング方法
JP2002025916A (ja) * 2000-07-11 2002-01-25 Toyota Central Res & Dev Lab Inc ヘテロ構造基板およびその製造方法
JP2002270850A (ja) * 2001-03-13 2002-09-20 National Institute Of Advanced Industrial & Technology 二重ゲート電界効果トランジスタ
JP2002270851A (ja) * 2001-03-13 2002-09-20 National Institute Of Advanced Industrial & Technology 半導体装置の製造方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5170958B2 (ja) * 2004-01-30 2013-03-27 ルネサスエレクトロニクス株式会社 電界効果型トランジスタおよびその製造方法
JP2009544150A (ja) * 2006-07-14 2009-12-10 マイクロン テクノロジー， インク． 解像度以下のケイ素フィーチャおよびそれを形成するための方法
US8981444B2 (en) 2006-07-14 2015-03-17 Round Rock Research, Llc Subresolution silicon features and methods for forming the same
JP2008300816A (ja) * 2007-05-29 2008-12-11 Nanya Technology Corp 自己整合式ＦｉｎＦＥＴ装置の製作方法
JP2013161920A (ja) * 2012-02-03 2013-08-19 Toshiba Corp 不揮発性半導体記憶装置及びその製造方法
US9117848B2 (en) 2012-02-03 2015-08-25 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and method of manufacturing the same

Also Published As

Publication number Publication date
TWI376803B (en) 2012-11-11
US20050104091A1 (en) 2005-05-19
KR20060108629A (ko) 2006-10-18
TW200524159A (en) 2005-07-16
GB2424517B (en) 2007-07-11
CN100524655C (zh) 2009-08-05
GB2424517A (en) 2006-09-27
CN1883041A (zh) 2006-12-20
US7029958B2 (en) 2006-04-18
DE112004002107B4 (de) 2010-05-06
KR101112046B1 (ko) 2012-02-27
GB0610759D0 (en) 2006-07-12
WO2005048339A1 (en) 2005-05-26
DE112004002107T5 (de) 2006-12-14

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