KR101112046B1 - 자기 정렬된 다마신 게이트 - Google Patents

자기 정렬된 다마신 게이트 Download PDF

Info

Publication number
KR101112046B1
KR101112046B1 KR1020067008094A KR20067008094A KR101112046B1 KR 101112046 B1 KR101112046 B1 KR 101112046B1 KR 1020067008094 A KR1020067008094 A KR 1020067008094A KR 20067008094 A KR20067008094 A KR 20067008094A KR 101112046 B1 KR101112046 B1 KR 101112046B1
Authority
KR
South Korea
Prior art keywords
fin
forming
gate
region
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020067008094A
Other languages
English (en)
Korean (ko)
Other versions
KR20060108629A (ko
Inventor
사이러스 이. 태버리
쉬브리 에스. 아메드
매튜 에스. 바이노스키
스리칸테스바라 다크쉬나-머피
피크 조란 크리보카
하이홍 왕
치-유 양
빈 유
Original Assignee
글로벌파운드리즈 인크.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 글로벌파운드리즈 인크. filed Critical 글로벌파운드리즈 인크.
Publication of KR20060108629A publication Critical patent/KR20060108629A/ko
Application granted granted Critical
Publication of KR101112046B1 publication Critical patent/KR101112046B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/62Fin field-effect transistors [FinFET]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H10D30/0245Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET] by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/791Arrangements for exerting mechanical stress on the crystal lattice of the channel regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)
KR1020067008094A 2003-11-04 2004-10-08 자기 정렬된 다마신 게이트 Expired - Fee Related KR101112046B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/699,887 US7029958B2 (en) 2003-11-04 2003-11-04 Self aligned damascene gate
US10/699,887 2003-11-04
PCT/US2004/033251 WO2005048339A1 (en) 2003-11-04 2004-10-08 Self aligned damascene gate

Publications (2)

Publication Number Publication Date
KR20060108629A KR20060108629A (ko) 2006-10-18
KR101112046B1 true KR101112046B1 (ko) 2012-02-27

Family

ID=34573288

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020067008094A Expired - Fee Related KR101112046B1 (ko) 2003-11-04 2004-10-08 자기 정렬된 다마신 게이트

Country Status (8)

Country Link
US (1) US7029958B2 (enExample)
JP (1) JP2007511071A (enExample)
KR (1) KR101112046B1 (enExample)
CN (1) CN100524655C (enExample)
DE (1) DE112004002107B4 (enExample)
GB (1) GB2424517B (enExample)
TW (1) TWI376803B (enExample)
WO (1) WO2005048339A1 (enExample)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6686231B1 (en) * 2002-12-06 2004-02-03 Advanced Micro Devices, Inc. Damascene gate process with sacrificial oxide in semiconductor devices
US7041542B2 (en) * 2004-01-12 2006-05-09 Advanced Micro Devices, Inc. Damascene tri-gate FinFET
WO2005074035A1 (ja) * 2004-01-30 2005-08-11 Nec Corporation 電界効果型トランジスタおよびその製造方法
KR100598099B1 (ko) * 2004-02-24 2006-07-07 삼성전자주식회사 다마신 게이트를 갖는 수직 채널 핀 전계효과 트랜지스터 및 그 제조방법
US7084018B1 (en) 2004-05-05 2006-08-01 Advanced Micro Devices, Inc. Sacrificial oxide for minimizing box undercut in damascene FinFET
WO2006076151A2 (en) * 2004-12-21 2006-07-20 Carnegie Mellon University Lithography and associated methods, devices, and systems
US7858481B2 (en) 2005-06-15 2010-12-28 Intel Corporation Method for fabricating transistor with thinned channel
US7352034B2 (en) * 2005-08-25 2008-04-01 International Business Machines Corporation Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures
US20090321830A1 (en) * 2006-05-15 2009-12-31 Carnegie Mellon University Integrated circuit device, system, and method of fabrication
US7678648B2 (en) * 2006-07-14 2010-03-16 Micron Technology, Inc. Subresolution silicon features and methods for forming the same
US7772048B2 (en) * 2007-02-23 2010-08-10 Freescale Semiconductor, Inc. Forming semiconductor fins using a sacrificial fin
US8518767B2 (en) * 2007-02-28 2013-08-27 International Business Machines Corporation FinFET with reduced gate to fin overlay sensitivity
TW200847292A (en) * 2007-05-29 2008-12-01 Nanya Technology Corp Method of manufacturing a self-aligned FinFET device
US7902000B2 (en) * 2008-06-04 2011-03-08 International Business Machines Corporation MugFET with stub source and drain regions
JP5404812B2 (ja) * 2009-12-04 2014-02-05 株式会社東芝 半導体装置の製造方法
CN102129982A (zh) * 2010-12-29 2011-07-20 北京大学深圳研究生院 半导体精细图形及鳍形场效应管的fin体的制作方法
CN102956484B (zh) * 2011-08-22 2016-03-30 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
US8569822B2 (en) * 2011-11-02 2013-10-29 Macronix International Co., Ltd. Memory structure
TWI467577B (zh) * 2011-11-02 2015-01-01 Macronix Int Co Ltd 記憶體結構及其製造方法
CN113345952B (zh) 2011-12-22 2025-05-13 英特尔公司 具有颈状半导体主体的半导体器件以及形成不同宽度的半导体主体的方法
US20130200459A1 (en) * 2012-02-02 2013-08-08 International Business Machines Corporation Strained channel for depleted channel semiconductor devices
JP5624567B2 (ja) * 2012-02-03 2014-11-12 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
CN103594342B (zh) * 2012-08-13 2016-03-16 中芯国际集成电路制造(上海)有限公司 形成鳍部的方法和形成鳍式场效应晶体管的方法
CN104465347A (zh) * 2013-09-24 2015-03-25 北大方正集团有限公司 多晶硅表面处理方法及系统
US9653584B2 (en) * 2013-12-23 2017-05-16 Intel Corporation Pre-sculpting of Si fin elements prior to cladding for transistor channel applications
US9711645B2 (en) 2013-12-26 2017-07-18 International Business Machines Corporation Method and structure for multigate FinFET device epi-extension junction control by hydrogen treatment
TWI620234B (zh) * 2014-07-08 2018-04-01 聯華電子股份有限公司 一種製作半導體元件的方法
CN105762071B (zh) * 2014-12-17 2019-06-21 中国科学院微电子研究所 鳍式场效应晶体管及其鳍的制造方法
US10424664B2 (en) * 2016-12-14 2019-09-24 Globalfoundries Inc. Poly gate extension source to body contact

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020130354A1 (en) * 2001-03-13 2002-09-19 National Inst. Of Advanced Ind. Science And Tech. Double-gate field-effect transistor, integrated circuit using the transistor and method of manufacturing the same
US20020140039A1 (en) 2000-11-13 2002-10-03 International Business Machines Corporation Double gate trench transistor
US6583469B1 (en) * 2002-01-28 2003-06-24 International Business Machines Corporation Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5007982A (en) * 1988-07-11 1991-04-16 North American Philips Corporation Reactive ion etching of silicon with hydrogen bromide
JP2969832B2 (ja) * 1990-07-09 1999-11-02 ソニー株式会社 Mis型半導体装置
JPH04303929A (ja) * 1991-01-29 1992-10-27 Micron Technol Inc シリコン基板をトレンチ・エッチングするための方法
US5757038A (en) 1995-11-06 1998-05-26 International Business Machines Corporation Self-aligned dual gate MOSFET with an ultranarrow channel
US5817550A (en) * 1996-03-05 1998-10-06 Regents Of The University Of California Method for formation of thin film transistors on plastic substrates
JP3695184B2 (ja) * 1998-12-03 2005-09-14 松下電器産業株式会社 プラズマエッチング装置およびプラズマエッチング方法
US6329124B1 (en) * 1999-05-26 2001-12-11 Advanced Micro Devices Method to produce high density memory cells and small spaces by using nitride spacer
US6514378B1 (en) * 2000-03-31 2003-02-04 Lam Research Corporation Method for improving uniformity and reducing etch rate variation of etching polysilicon
JP2002025916A (ja) * 2000-07-11 2002-01-25 Toyota Central Res & Dev Lab Inc ヘテロ構造基板およびその製造方法
US6350696B1 (en) * 2000-09-28 2002-02-26 Advanced Micro Devices, Inc. Spacer etch method for semiconductor device
US7163864B1 (en) 2000-10-18 2007-01-16 International Business Machines Corporation Method of fabricating semiconductor side wall fin
US6300182B1 (en) 2000-12-11 2001-10-09 Advanced Micro Devices, Inc. Field effect transistor having dual gates with asymmetrical doping for reduced threshold voltage
US6475869B1 (en) 2001-02-26 2002-11-05 Advanced Micro Devices, Inc. Method of forming a double gate transistor having an epitaxial silicon/germanium channel region
JP3543117B2 (ja) * 2001-03-13 2004-07-14 独立行政法人産業技術総合研究所 二重ゲート電界効果トランジスタ
JP3488916B2 (ja) * 2001-03-13 2004-01-19 独立行政法人産業技術総合研究所 半導体装置の製造方法
US6514849B1 (en) * 2001-04-02 2003-02-04 Advanced Micro Devices, Inc. Method of forming smaller contact size using a spacer hard mask
US6458662B1 (en) 2001-04-04 2002-10-01 Advanced Micro Devices, Inc. Method of fabricating a semiconductor device having an asymmetrical dual-gate silicon-germanium (SiGe) channel MOSFET and a device thereby formed
KR100431489B1 (ko) * 2001-09-04 2004-05-12 한국과학기술원 플래쉬 메모리 소자 및 제조방법
US6657259B2 (en) * 2001-12-04 2003-12-02 International Business Machines Corporation Multiple-plane FinFET CMOS
US6657252B2 (en) * 2002-03-19 2003-12-02 International Business Machines Corporation FinFET CMOS with NVRAM capability
US6642090B1 (en) * 2002-06-03 2003-11-04 International Business Machines Corporation Fin FET devices from bulk semiconductor and method for forming
US6770516B2 (en) * 2002-09-05 2004-08-03 Taiwan Semiconductor Manufacturing Company Method of forming an N channel and P channel FINFET device on the same semiconductor substrate
US6706571B1 (en) * 2002-10-22 2004-03-16 Advanced Micro Devices, Inc. Method for forming multiple structures in a semiconductor device
US6709982B1 (en) * 2002-11-26 2004-03-23 Advanced Micro Devices, Inc. Double spacer FinFET formation
US6645797B1 (en) * 2002-12-06 2003-11-11 Advanced Micro Devices, Inc. Method for forming fins in a FinFET device using sacrificial carbon layer
US6864164B1 (en) * 2002-12-17 2005-03-08 Advanced Micro Devices, Inc. Finfet gate formation using reverse trim of dummy gate
US6762483B1 (en) * 2003-01-23 2004-07-13 Advanced Micro Devices, Inc. Narrow fin FinFET
US6764884B1 (en) * 2003-04-03 2004-07-20 Advanced Micro Devices, Inc. Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device
US6903967B2 (en) * 2003-05-22 2005-06-07 Freescale Semiconductor, Inc. Memory with charge storage locations and adjacent gate structures
US6855582B1 (en) * 2003-06-12 2005-02-15 Advanced Micro Devices, Inc. FinFET gate formation using reverse trim and oxide polish
US6911383B2 (en) * 2003-06-26 2005-06-28 International Business Machines Corporation Hybrid planar and finFET CMOS devices
US6787476B1 (en) * 2003-08-04 2004-09-07 Advanced Micro Devices, Inc. Etch stop layer for etching FinFET gate over a large topography

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020140039A1 (en) 2000-11-13 2002-10-03 International Business Machines Corporation Double gate trench transistor
US20020130354A1 (en) * 2001-03-13 2002-09-19 National Inst. Of Advanced Ind. Science And Tech. Double-gate field-effect transistor, integrated circuit using the transistor and method of manufacturing the same
US6583469B1 (en) * 2002-01-28 2003-06-24 International Business Machines Corporation Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same

Also Published As

Publication number Publication date
TWI376803B (en) 2012-11-11
US20050104091A1 (en) 2005-05-19
KR20060108629A (ko) 2006-10-18
TW200524159A (en) 2005-07-16
GB2424517B (en) 2007-07-11
CN100524655C (zh) 2009-08-05
GB2424517A (en) 2006-09-27
JP2007511071A (ja) 2007-04-26
CN1883041A (zh) 2006-12-20
US7029958B2 (en) 2006-04-18
DE112004002107B4 (de) 2010-05-06
GB0610759D0 (en) 2006-07-12
WO2005048339A1 (en) 2005-05-26
DE112004002107T5 (de) 2006-12-14

Similar Documents

Publication Publication Date Title
KR101112046B1 (ko) 자기 정렬된 다마신 게이트
US11581421B2 (en) Semiconductor device and method of manufacturing the same
CN100413039C (zh) 形成FinFET装置中的栅极以及薄化该FinFET装置的沟道区中的鳍的方法
US6852576B2 (en) Method for forming structures in finfet devices
US6645797B1 (en) Method for forming fins in a FinFET device using sacrificial carbon layer
CN100505182C (zh) 磨平栅极材料以改善半导体装置中的栅极特征尺寸的方法
JP5057649B2 (ja) ダブルおよびトリプルゲートmosfetデバイス、およびこれらのmosfetデバイスを製造する方法
TWI711076B (zh) 鰭片型場效應電晶體及用於製造其的方法
US6998301B1 (en) Method for forming a tri-gate MOSFET
US8008136B2 (en) Fully silicided gate structure for FinFET devices
JP2007501524A (ja) 全体的な設計目標を達成すべく、半導体デバイス中のキャリア移動度の可変な半導体デバイス
JP5270093B2 (ja) ダマシンプロセスにより形成されるトライゲートFinFET
US20250308998A1 (en) Metal gate process and related structure
US7041601B1 (en) Method of manufacturing metal gate MOSFET with strained channel
US20060261414A1 (en) Fin field effect transistors (FinFETs) and methods for making the same
US7105391B2 (en) Planar pedestal multi gate device
US7091068B1 (en) Planarizing sacrificial oxide to improve gate critical dimension in semiconductor devices
US6995438B1 (en) Semiconductor device with fully silicided source/drain and damascence metal gate
CN114551240B (zh) 半导体结构的形成方法

Legal Events

Date Code Title Description
E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

N231 Notification of change of applicant
PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

FPAY Annual fee payment

Payment date: 20150106

Year of fee payment: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

FPAY Annual fee payment

Payment date: 20160104

Year of fee payment: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

FPAY Annual fee payment

Payment date: 20170102

Year of fee payment: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20180128

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20180128

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000