CN100524655C - 自动对准镶嵌栅极 - Google Patents

自动对准镶嵌栅极 Download PDF

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Publication number
CN100524655C
CN100524655C CNB2004800337151A CN200480033715A CN100524655C CN 100524655 C CN100524655 C CN 100524655C CN B2004800337151 A CNB2004800337151 A CN B2004800337151A CN 200480033715 A CN200480033715 A CN 200480033715A CN 100524655 C CN100524655 C CN 100524655C
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CN
China
Prior art keywords
fin
gate
forming
etching
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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CNB2004800337151A
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English (en)
Chinese (zh)
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CN1883041A (zh
Inventor
C·E·塔贝里
S·S·艾哈迈德
M·S·拜诺斯基
S·达克希纳-墨菲
Z·克里沃卡皮奇
汪海宏
C-Y·杨
俞斌
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GlobalFoundries US Inc
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Advanced Micro Devices Inc
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Publication of CN1883041A publication Critical patent/CN1883041A/zh
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Publication of CN100524655C publication Critical patent/CN100524655C/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H10D30/0245—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET] by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)
CNB2004800337151A 2003-11-04 2004-10-08 自动对准镶嵌栅极 Expired - Lifetime CN100524655C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/699,887 US7029958B2 (en) 2003-11-04 2003-11-04 Self aligned damascene gate
US10/699,887 2003-11-04

Publications (2)

Publication Number Publication Date
CN1883041A CN1883041A (zh) 2006-12-20
CN100524655C true CN100524655C (zh) 2009-08-05

Family

ID=34573288

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2004800337151A Expired - Lifetime CN100524655C (zh) 2003-11-04 2004-10-08 自动对准镶嵌栅极

Country Status (8)

Country Link
US (1) US7029958B2 (enExample)
JP (1) JP2007511071A (enExample)
KR (1) KR101112046B1 (enExample)
CN (1) CN100524655C (enExample)
DE (1) DE112004002107B4 (enExample)
GB (1) GB2424517B (enExample)
TW (1) TWI376803B (enExample)
WO (1) WO2005048339A1 (enExample)

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US7084018B1 (en) 2004-05-05 2006-08-01 Advanced Micro Devices, Inc. Sacrificial oxide for minimizing box undercut in damascene FinFET
WO2006076151A2 (en) * 2004-12-21 2006-07-20 Carnegie Mellon University Lithography and associated methods, devices, and systems
US7858481B2 (en) 2005-06-15 2010-12-28 Intel Corporation Method for fabricating transistor with thinned channel
US7352034B2 (en) * 2005-08-25 2008-04-01 International Business Machines Corporation Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures
US20090321830A1 (en) * 2006-05-15 2009-12-31 Carnegie Mellon University Integrated circuit device, system, and method of fabrication
US7678648B2 (en) * 2006-07-14 2010-03-16 Micron Technology, Inc. Subresolution silicon features and methods for forming the same
US7772048B2 (en) * 2007-02-23 2010-08-10 Freescale Semiconductor, Inc. Forming semiconductor fins using a sacrificial fin
US8518767B2 (en) * 2007-02-28 2013-08-27 International Business Machines Corporation FinFET with reduced gate to fin overlay sensitivity
TW200847292A (en) * 2007-05-29 2008-12-01 Nanya Technology Corp Method of manufacturing a self-aligned FinFET device
US7902000B2 (en) * 2008-06-04 2011-03-08 International Business Machines Corporation MugFET with stub source and drain regions
JP5404812B2 (ja) * 2009-12-04 2014-02-05 株式会社東芝 半導体装置の製造方法
CN102129982A (zh) * 2010-12-29 2011-07-20 北京大学深圳研究生院 半导体精细图形及鳍形场效应管的fin体的制作方法
CN102956484B (zh) * 2011-08-22 2016-03-30 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
US8569822B2 (en) * 2011-11-02 2013-10-29 Macronix International Co., Ltd. Memory structure
TWI467577B (zh) * 2011-11-02 2015-01-01 Macronix Int Co Ltd 記憶體結構及其製造方法
CN113345952B (zh) 2011-12-22 2025-05-13 英特尔公司 具有颈状半导体主体的半导体器件以及形成不同宽度的半导体主体的方法
US20130200459A1 (en) * 2012-02-02 2013-08-08 International Business Machines Corporation Strained channel for depleted channel semiconductor devices
JP5624567B2 (ja) * 2012-02-03 2014-11-12 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
CN103594342B (zh) * 2012-08-13 2016-03-16 中芯国际集成电路制造(上海)有限公司 形成鳍部的方法和形成鳍式场效应晶体管的方法
CN104465347A (zh) * 2013-09-24 2015-03-25 北大方正集团有限公司 多晶硅表面处理方法及系统
US9653584B2 (en) * 2013-12-23 2017-05-16 Intel Corporation Pre-sculpting of Si fin elements prior to cladding for transistor channel applications
US9711645B2 (en) 2013-12-26 2017-07-18 International Business Machines Corporation Method and structure for multigate FinFET device epi-extension junction control by hydrogen treatment
TWI620234B (zh) * 2014-07-08 2018-04-01 聯華電子股份有限公司 一種製作半導體元件的方法
CN105762071B (zh) * 2014-12-17 2019-06-21 中国科学院微电子研究所 鳍式场效应晶体管及其鳍的制造方法
US10424664B2 (en) * 2016-12-14 2019-09-24 Globalfoundries Inc. Poly gate extension source to body contact

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US6329124B1 (en) * 1999-05-26 2001-12-11 Advanced Micro Devices Method to produce high density memory cells and small spaces by using nitride spacer
US20020130354A1 (en) * 2001-03-13 2002-09-19 National Inst. Of Advanced Ind. Science And Tech. Double-gate field-effect transistor, integrated circuit using the transistor and method of manufacturing the same
US20020140039A1 (en) * 2000-11-13 2002-10-03 International Business Machines Corporation Double gate trench transistor
US6514849B1 (en) * 2001-04-02 2003-02-04 Advanced Micro Devices, Inc. Method of forming smaller contact size using a spacer hard mask
US6514378B1 (en) * 2000-03-31 2003-02-04 Lam Research Corporation Method for improving uniformity and reducing etch rate variation of etching polysilicon
US6583469B1 (en) * 2002-01-28 2003-06-24 International Business Machines Corporation Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same

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US6475869B1 (en) 2001-02-26 2002-11-05 Advanced Micro Devices, Inc. Method of forming a double gate transistor having an epitaxial silicon/germanium channel region
JP3543117B2 (ja) * 2001-03-13 2004-07-14 独立行政法人産業技術総合研究所 二重ゲート電界効果トランジスタ
JP3488916B2 (ja) * 2001-03-13 2004-01-19 独立行政法人産業技術総合研究所 半導体装置の製造方法
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US6645797B1 (en) * 2002-12-06 2003-11-11 Advanced Micro Devices, Inc. Method for forming fins in a FinFET device using sacrificial carbon layer
US6864164B1 (en) * 2002-12-17 2005-03-08 Advanced Micro Devices, Inc. Finfet gate formation using reverse trim of dummy gate
US6762483B1 (en) * 2003-01-23 2004-07-13 Advanced Micro Devices, Inc. Narrow fin FinFET
US6764884B1 (en) * 2003-04-03 2004-07-20 Advanced Micro Devices, Inc. Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device
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US6329124B1 (en) * 1999-05-26 2001-12-11 Advanced Micro Devices Method to produce high density memory cells and small spaces by using nitride spacer
US6514378B1 (en) * 2000-03-31 2003-02-04 Lam Research Corporation Method for improving uniformity and reducing etch rate variation of etching polysilicon
US20020140039A1 (en) * 2000-11-13 2002-10-03 International Business Machines Corporation Double gate trench transistor
US20020130354A1 (en) * 2001-03-13 2002-09-19 National Inst. Of Advanced Ind. Science And Tech. Double-gate field-effect transistor, integrated circuit using the transistor and method of manufacturing the same
US6514849B1 (en) * 2001-04-02 2003-02-04 Advanced Micro Devices, Inc. Method of forming smaller contact size using a spacer hard mask
US6583469B1 (en) * 2002-01-28 2003-06-24 International Business Machines Corporation Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same

Also Published As

Publication number Publication date
TWI376803B (en) 2012-11-11
US20050104091A1 (en) 2005-05-19
KR20060108629A (ko) 2006-10-18
TW200524159A (en) 2005-07-16
GB2424517B (en) 2007-07-11
GB2424517A (en) 2006-09-27
JP2007511071A (ja) 2007-04-26
CN1883041A (zh) 2006-12-20
US7029958B2 (en) 2006-04-18
DE112004002107B4 (de) 2010-05-06
KR101112046B1 (ko) 2012-02-27
GB0610759D0 (en) 2006-07-12
WO2005048339A1 (en) 2005-05-26
DE112004002107T5 (de) 2006-12-14

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Patentee after: Lattice chip (USA) integrated circuit technology Co.,Ltd.

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