WO2005048339A1 - Self aligned damascene gate - Google Patents

Self aligned damascene gate Download PDF

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Publication number
WO2005048339A1
WO2005048339A1 PCT/US2004/033251 US2004033251W WO2005048339A1 WO 2005048339 A1 WO2005048339 A1 WO 2005048339A1 US 2004033251 W US2004033251 W US 2004033251W WO 2005048339 A1 WO2005048339 A1 WO 2005048339A1
Authority
WO
WIPO (PCT)
Prior art keywords
fin
gate
forming
area
mosfet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2004/033251
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English (en)
French (fr)
Inventor
Cyrus E. Tabery
Shibly S. Ahmed
Matthew S. Buynoski
Srikanteswara Dakshina-Murphy
Zoran Krivokapic
Haihong Wang
Chih-Yuh Yang
Bin Yu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Priority to DE112004002107T priority Critical patent/DE112004002107B4/de
Priority to JP2006538035A priority patent/JP2007511071A/ja
Priority to KR1020067008094A priority patent/KR101112046B1/ko
Priority to GB0610759A priority patent/GB2424517B/en
Publication of WO2005048339A1 publication Critical patent/WO2005048339A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H10D30/0245—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET] by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions

Definitions

  • the present invention relates generally to semiconductor devices and, more particularly, to metal-oxide semiconductor field-effect transistor (MOSFET) devices with a self aligned damascene gate and methods of making these devices.
  • MOSFET metal-oxide semiconductor field-effect transistor
  • Scaling of device dimensions has been a primary factor driving improvements in integrated circuit performance and reduction in integrated circuit cost. Due to limitations associated with gate-oxide thicknesses and source/drain (S/D) junction depths, scaling of existing bulk MOSFET devices below the 0.1 ⁇ m process generation may be difficult, if not impossible. New device structures and new materials, thus, are likely to be needed to improve FET performance. Double-gate MOSFETs represent devices that are candidates for succeeding existing planar MOSFETs.
  • a FinFET is a double-gate structure that includes a channel formed in a vertical fin. Although a double-gate structure, the FinFET is similar to existing planar MOSFETs in layout and fabrication techniques. The FinFET also provides a range of channel lengths, CMOS compatibility, and large packing density compared to other double-gate structures.
  • SUMMARY OF THE INVENTION Implementations consistent with the principles of the invention provide FinFET devices that include a damascene gate formed with a self aligned gate mask and methods for manufacturing these devices.
  • a method for forming a metal-oxide semiconductor field-effect transistor includes patterning a fin (310) area, a source region, and a drain region on a substrate, forming a fin (310) in the fin (310) area, and forming a mask in the fin (310) area. The method further includes etching the mask to expose a channel area of the MOSFET, etching the fin (310) to thin a width of the fin (310) in the channel area, forming a gate over the fin, and forming contacts to the gate, the source region, and the drain region.
  • MOSFET metal-oxide semiconductor field-effect transistor
  • a method for forming a MOSFET includes forming a fin (310) on a substrate; forming a mask on the substrate; etching the mask to expose a channel area of the MOSFET; thinning a width of the fin (310) in the channel area; and forming a gate over the fin, where the gate extends on each side of the fin.
  • a MOSFET includes a fin (310) having a width of approximately 100 A to 400 A formed on a substrate, a gate dielectric formed on side surfaces of the fin, and a gate electrode formed covering the fin.
  • Fig. 1 illustrates an exemplary process for fabricating a MOSFET in accordance with an implementation consistent with the principles of the invention
  • Figs. 2A-6C illustrate exemplary top and cross-sectional views of a MOSFET fabricated according to the processing described in Fig. 1
  • Figs. 7A-7C illustrate a process for forming spacers according to another implementation consistent with the principles of the invention
  • Figs. 8A-8C illustrate an exemplary process for removing fin (310) sidewall damage
  • Fig. 1 illustrates an exemplary process for fabricating a MOSFET in accordance with an implementation consistent with the principles of the invention
  • Figs. 2A-6C illustrate exemplary top and cross-sectional views of a MOSFET fabricated according to the processing described in Fig. 1
  • Figs. 7A-7C illustrate a process for forming spacers according to another implementation consistent with the principles of the invention
  • Figs. 8A-8C illustrate an exemplary process for removing fin (310) sidewall damage
  • FIG. 9 illustrates an exemplary process for improving mobility of a FinFET device.
  • Implementations consistent with the principles of the invention provide FinFET devices that include a self aligned damascene gate and methods for manufacturing these devices. Such FinFET devices have certain advantages. For example, only the active area of the fin (310) is at the minimum channel length, which reduces source/drain resistance. The gate is also self aligned to the minimum channel area, which significantly reduces the parasitic source/drain resistance of the device.
  • Fig. 1 illustrates an exemplary process for fabricating a MOSFET in accordance with an implementation consistent with the principles of the invention. Figs.
  • semiconductor device 200 may include a silicon on insulator (SOI) structure that includes a silicon (Si) substrate 210, a buried oxide layer 220, and a silicon layer 230 on the buried oxide layer 220. Buried oxide layer 220 and silicon layer 230 may be formed on substrate 210 in a conventional manner.
  • the thickness of buried oxide layer 220 may range, for example, from about 1,000 A to 10,000 A.
  • the thickness of silicon layer 230 may range, for example, from about 400 A to 1,500 A.
  • the silicon thickness may be as thick as possible since increased thickness leads to enhanced width of the device (i.e., more current flow along the sidewall of the fin (310) and thereby higher drive current (in a MOSFET I oc W/L)).
  • MOSFET I oc W/L MOSFET I oc W/L
  • silicon layer 230 is used to form the fin.
  • substrate 210 and layer 230 may include other semiconductor materials, such as germanium, or combinations of semiconductor materials, such as silicon-germanium.
  • Buried oxide layer 220 may include a silicon oxide or other types of dielectric materials.
  • a silicon nitride, or another type of material may be formed on silicon layer 230 and may function as a bottom antireflective coating (BARC) 240 for subsequent processing, as illustrated in Figs. 2A and 2B.
  • the thickness of BARC layer 240 may range from approximately 150 A to 350 A.
  • a photoresist 250, or the like, may be deposited and patterned to facilitate formation of a large fin (310) area and the source and drain regions (act 110), as shown in Figs. 2A-2C.
  • Photoresist 250 may be deposited to a thickness ranging from about 1,000 A to 4,000 A.
  • Fig. 2C illustrates the top view of semiconductor device 200 of Figs.
  • Silicon layer 230 may be etched to form a fin (310) 310 (act 120), as shown in Figs. 3A and 3B.
  • the portion of silicon layer 230 not located under photoresist 250 may be etched with the etching terminating on buried oxide layer 220. Photoresist 250 may then be removed.
  • the width of fin (310) 310, as shown in Fig. 3B, may range from approximately 500 A to 800 A.
  • a damascene mask may be formed in the area of fin (310) 310 (act 130), as illustrated in Figs.
  • a damascene material 320 such as silicon oxide, silicon nitride, SiCOH, etc.
  • a damascene material 320 may be deposited over semiconductor device 200 to a thickness ranging from approximately 800 A to 2,200 A (to enclose fin (310) 310 and BARC 240) and then polished using known techniques, as illustrated in Figs. 3A and 3B.
  • Damascene material 320 may function as a BARC for subsequent processing.
  • Damascene material 320 may then be etched using a gate mask to expose a channel area 330 in the gate opening, as shown in Figs. 3A-3C.
  • the width of channel area 330 as illustrated in Fig. 3C, may range from approximately 300 A to 500 A.
  • the gate mask used to expose channel area 330 may be created using aggressive lithography and patterning techniques known to those skilled in the art.
  • the width of fin (310) 310 may then be reduced (act 140), as illustrated in Figs. 4A-4C.
  • One or more etching techniques may be used to laterally etch fin (310) 310 in channel area 330.
  • a thermal oxidation of Si followed by a dilute HF dip may be used.
  • Other types of etches may alternatively to be used.
  • Si may be etched in a downstream F plasma where the chemical selectivity of the Si etch in F species over oxide is very high, or a lateral Si etch in HBr based plasma chemistries may be used.
  • the amount of silicon removed may range from approximately 100 A to 200 A per side, as illustrated in Fig. 4B.
  • the resulting width of fin (310) 310 may range from approximately 100 A to 400 A.
  • BARC 240 may remain in implementations consistent with the principles of the invention, as illustrated in Fig. 4B. In other implementations, BARC 240 may be removed.
  • Fig. 4C illustrates a top view of semiconductor device 200 after fin (310) 310 has been thinned in channel area 330.
  • a gate may then be formed (act 150), as illustrated in Figs. 5A-5C.
  • a gate dielectric material 510 may be deposited or thermally grown on the side surfaces of fin (310) 310 using known techniques, as illustrated in Fig. 5B.
  • Gate dielectric material 510 may include conventional dielectric materials, such as an oxide (e.g., silicon dioxide), silicon oxy-nitride, or high dielectric constant (high K) materials, such as Hf0 2 . In other implementations, a silicon nitride or other materials may be used to form the gate dielectric. Gate dielectric material 510 may be formed at a thickness ranging from approximately 10 A to 20 A. A gate electrode material 520 may then be deposited over semiconductor device 200 and polished, as illustrated in Figs. 5A and 5B. Gate electrode material 520 may be polished (e.g., via chemical-mechanical polishing (CMP)) to remove any gate material over damascene material 320, as illustrated in Figs. 5A and 5B.
  • CMP chemical-mechanical polishing
  • gate electrode material 520 may include a polycrystalline silicon or other types of conductive material, such as germanium or combinations of silicon and germanium, or metals, such as W, WN, TaN, TiN, etc.
  • Gate electrode material 520 may be formed at a thickness ranging from approximately 700 A to 2,100 A, as illustrated in Fig. 5B, which may be approximately equal to the thickness of damascene material 320 (some of which may be lost due to the polishing).
  • Fig. 5C illustrates a top view of semiconductor 200 after gate electrode 520 is formed. The dotted lines in Fig. 5C represent the thinned portion of fin (310) 310. Gate dielectric layer 510 is not illustrated in Fig. 5C for simplicity.
  • Source, drain, and gate contacts may then be formed (act 160), as illustrated in Figs. 6A-6C.
  • large contact areas may be opened over fin (310) 310 on either side of the gate, as illustrated in Fig. 6A.
  • Source and drain contact areas 610 and 620 may be opened by etching through the extra amount of damascene material 320 left above fin (310) 310 and also removing BARC 240.
  • Gate contact area 630 may also be formed on gate electrode 520. It may be possible for these contact areas 610-630 to be larger than the actual dimensions of fin (310) 310 and the source/drain. Silicidation, such as CoSi 2 or iSi silicidation, can then occur in these openings.
  • CoSi 2 or NiSi silicidation occurs only where there is polysilicon (i.e., gate) or silicon (i.e., source/drain) and whatever fin (310) region (wide fin) is exposed.
  • the unreacted cobalt or nickel (wherever there is no silicon) can be etched away just as is done in typical self-aligned suicide schemes in use by the industry today.
  • damascene material 320 and BARC 240 may be removed from the top of fin (310) 310 and the source/drain. Then, a sidewall spacer may be formed on the sides of the gate and fin (310) 310.
  • a suicide metal such as cobalt or nickel
  • the resulting semiconductor device 200 may include a self aligned damascene gate formed on either side of fin (310) 310.
  • Fin (310) 310 is thinned in the channel area, as illustrated by the dotted lines in Fig. 6C.
  • spacers may be formed for the transfer of the damascene gate to make the gate length smaller.
  • Figs. 7A-7C illustrate an exemplary process for forming spacers according to an alternate implementation consistent with the principles of the invention. As illustrated in Figs.
  • a hardmask 710 may be opened (Fig. 7A), spacers 720 may be formed (Fig. 7B), and the transfer of the damascene gate may be performed in the opening (Fig. 7C).
  • the spacer formation inside the damascene gate opening may facilitate printing of small spaces (as mentioned above) in order to form small gate length devices.
  • the spacer technique enables the formation of smaller spaces than may be attained by photolithographic shrinking alone.
  • damascene gate shrink techniques such as the ones described in copending, commonly assigned applications entitled, "FINFET GATE FORMATION USING REVERSE TRIM AND OXIDE POLISH" (Serial No. 10/459,589) (Docket No.
  • HI 122 filed June 12, 2003, "FINFET GATE FORMATION USING REVERSE TRIM OF DUMMY GATE” (Serial No. 10/320,536) (Docket No. HI 121), filed December 17, 2002, and "ETCH STOP LAYER FOR ETCHING FINFET GATE OVER A LARGE TOPOGRAPHY” (Serial No. 10/632,989) (Docket No. HI 172), filed August 4, 2003, which are incorporated herein by reference.
  • a metal gate electrode may be used instead of the polysilicon damascene process described above.
  • a semiconductor device 800 may include a fin (310) layer 810 and a cover layer 820 formed on a substrate 830, as illustrated in Fig. 8A.
  • Fin (310) layer 810 may include a semiconductor material, such as silicon or germanium, or combinations of semiconductor materials.
  • Cover layer 820 may, for example, include a silicon nitride material or some other type of material capable of protecting fin (310) layer 810 during the fabrication , process.
  • Fin (310) layer 810 and cover layer 820 may be etched using a conventional dry etching technique to form fin (310) 840, as illustrated in Fig. 8B.
  • a conventional wet etching technique may then be used to remove fin (310) sidewall damage, as illustrated in Fig. 8C.
  • the width of fin (310) 840 may be thinned by approximately 20 A to 40 A per side.
  • Wet etching of silicon may also result in some buried oxide loss since it is difficult when wet etching to get good selectivity of silicon to silicon dioxide.
  • Fig. 9 illustrates an exemplary process for improving mobility of a FinFET device.
  • a die-attach material may be formed on a package, as illustrated in Fig. 9.
  • the die-attach material may be selected to induce stress (strain) in the FinFET channel.
  • a die may then be attached to the die-attach material, as illustrated in Fig. 9.
  • Tensile stress induced in the silicon FinFET channel may result in enhanced hole mobility, which can help significantly improve PMOS FinFET performance.
  • the die-attach material and process may be such that the residual stress in the silicon layer is tensile. For example, if the package material did not shrink as fast as the silicon layer after the (hot) die attach/solder/bump process, then the silicon layer could be in tensile stress when cooled to lower temperatures.
  • FinFET devices that include a damascene gate formed with a self aligned gate mask and methods for manufacturing these devices. These FinFET devices have certain advantages. For example, only the active area of the fin (310) is at the minimum channel length, the gate is self aligned to the minimum channel, and the gate patterning is performed on a planar substrate (e.g., a polished damascene material).
  • a planar substrate e.g., a polished damascene material.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)
PCT/US2004/033251 2003-11-04 2004-10-08 Self aligned damascene gate Ceased WO2005048339A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
DE112004002107T DE112004002107B4 (de) 2003-11-04 2004-10-08 Verfahren zur Herstellung eines MOSFET mit selbstjustiertem Damaszener-Gate
JP2006538035A JP2007511071A (ja) 2003-11-04 2004-10-08 セルフアラインされたダマシンゲート
KR1020067008094A KR101112046B1 (ko) 2003-11-04 2004-10-08 자기 정렬된 다마신 게이트
GB0610759A GB2424517B (en) 2003-11-04 2004-10-08 Self aligned damascene gate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/699,887 US7029958B2 (en) 2003-11-04 2003-11-04 Self aligned damascene gate
US10/699,887 2003-11-04

Publications (1)

Publication Number Publication Date
WO2005048339A1 true WO2005048339A1 (en) 2005-05-26

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Country Status (8)

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US (1) US7029958B2 (enExample)
JP (1) JP2007511071A (enExample)
KR (1) KR101112046B1 (enExample)
CN (1) CN100524655C (enExample)
DE (1) DE112004002107B4 (enExample)
GB (1) GB2424517B (enExample)
TW (1) TWI376803B (enExample)
WO (1) WO2005048339A1 (enExample)

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US20050104091A1 (en) 2005-05-19
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GB2424517B (en) 2007-07-11
CN100524655C (zh) 2009-08-05
GB2424517A (en) 2006-09-27
JP2007511071A (ja) 2007-04-26
CN1883041A (zh) 2006-12-20
US7029958B2 (en) 2006-04-18
DE112004002107B4 (de) 2010-05-06
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GB0610759D0 (en) 2006-07-12
DE112004002107T5 (de) 2006-12-14

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