JP2001508937A - プラスチック基板上に薄膜トランジスタを形成させる方法 - Google Patents
プラスチック基板上に薄膜トランジスタを形成させる方法Info
- Publication number
- JP2001508937A JP2001508937A JP53192397A JP53192397A JP2001508937A JP 2001508937 A JP2001508937 A JP 2001508937A JP 53192397 A JP53192397 A JP 53192397A JP 53192397 A JP53192397 A JP 53192397A JP 2001508937 A JP2001508937 A JP 2001508937A
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- layer
- gate
- plastic substrate
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
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Classifications
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
- H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
- H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
- H01L21/02686—Pulsed laser beam
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
- H01L29/78666—Amorphous silicon transistors with normal-type structure, e.g. with top gate
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Optics & Photonics (AREA)
- Crystallography & Structural Chemistry (AREA)
- High Energy & Nuclear Physics (AREA)
- Electromagnetism (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Materials Engineering (AREA)
- Thin Film Transistor (AREA)
- Recrystallisation Techniques (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.低温プラスチック基盤上にシリコンの薄膜トランジスタを組み立てる方法 であって、低温プラスチック基盤を提供すること、その基盤上に最初の絶縁層を 形成すること、その最初の絶縁層の上に無定形シリコンの層を形成すること、そ の無定形シリコン層の上に第二の絶縁層を形成すること、その第二の絶縁層の上 に金属層を形成すること、その金属層の一部を除去すること、少なくともそのシ リコン層の一部が露出した状態で残るように第二の絶縁層の一部を除去すること 、その露出されたシリコン層をパルスレーザー加工によって不純物を加えて結晶 化させること、その不純物を加えたシリコン層と残っている金属層の上に第三の 絶緑層を生成させること、その第三の絶縁層に接触路を形成すること、そしてそ の接触路にソース、ゲート及びドレーン接触及び相互接続金属化を形成すること とを含む方法。 2.さらに、第二の絶縁層を形成するに先立って、少なくとも無定形シリコン 層の一部ポリシリコンに変換させることを含む請求範囲第1項の方法。 3.その無定形シリコンのポリシリコンへの変換は、その無定形シリコンの少 なくとも一部の上に少なくとも一つのレーザーパルスを向けることによって実施 する請求範囲第2項の方法。 4.少なくとも一つのレーザーパルスをエキシマレーザーによって生じさせる 請求範囲第3項の方法。 5.第一及び第二の絶縁層がSiO2、SiN成いはポリアミドで形成されている請求 範囲第1項の方法。 6.ゲート金属層が、アルミニウム、銅、モリブデン、クロム、タンタル、タ ングステン、ニッケル、チタン、ケイ素、チタン−ケイ素合金、アルミニウム− ケイ素合金、アルミニウム−銅合金、チタン−アルミニウム合金、及びケイ化物 で形成されている請求範囲第1項の方法。 7.ソース、ゲート及びドレーンの相互接続金属化が、アルミニウム、銅、モ リブデン、クロム、タンタル、タングステン、ニッケル、チタン、チタン−ケイ 素合金、アルミニウム−ケイ素合金、アルミニウム−銅合金、チタン−アルミニ ウム合金、及びケイ化物で形成されている請求範囲第1項の方法。 8.露出したシリコンのドーピングを、PF5、BF3、B2H6及びAsF5から成る群か ら選ばれたドーパントガス中で実施する請求範囲第1項の方法。 9.イオンシャワー、イオン移植及びCVDE付着の群から選ばれた技術によって 予め付着されたドーパント膜を使用して、ドーピングを実施する請求範囲第1項 の方法。 10.露出されたシリコンの結晶化は、各レーザーパルス或いは多数のレーザー パルスの各グループに対するレーザーの影響を増加させながら、レーザーパルス をシリコンの上に向けることによって実 施する請求範囲第1項の方法。 11.前記レーザーの影響が30-600mJ/cm2の範囲にある請求範囲第10項の方法。 12.露出したシリコンのドーピング及び/或いは結晶化を真空条件下で実施す る請求範囲第1項の方法。 13.さらに、PET、E-CTFE、E-TFE、PES、PTFE、FEP及びHDPEから成る群から選 ばれた材料からその低温プラスチック基盤を形成させることを含む請求範囲第1 項の方法。 14.前記低温プラスチック基盤が、約250℃より高く維持された加工温度に耐 えることができない材料から成る請求範囲第1項の方法。 15.第一及び第二の絶縁層と無定形シリコン層の形成が、約100℃より高くな い温度で実施される請求範囲第1項の方法。 16.さらに、第一の絶縁層を低温プラスチック基盤の上に形成させるに先立ち 、その低温プラスチック基盤を約110から150℃の温度で焼きなますことを含む請 求範囲第1項の方法。 17.薄膜トランジスタであって、低温プラスチックから成る基盤と、そのプラ スチックの上のSiO2の断熱層と、その断熱SiO2層の上のシリコン層と、前記シリ コン層は不純物を加えられたシリコンの部分及び不純物を加えられていないシリ コンの部分から成り、 前記シリコン層はポリシリコンの部分を含んでいるシリコン層と、そのシリコン 層の少なくとも一部の上にSiO2のゲート誘電層と、そのSiO2のゲート誘電層の少 なくとも一部の上のゲート金属層と、前記シリコン層及び前記ゲート金属層の部 分の上の酸化物の層と、ソース、ゲート及びドレーン接続部及び相互接続部を明 示している前記シリコン層及び前記ゲート金属層の部分の上の金属接続部とを含 む薄膜トランジスタ。 18.前記不純物を加えられていないシリコンはポリシリコン或いは無定形シリ コンである請求範囲第17項の薄膜トランジスタ。 19.前記低温プラスチック基盤は、約250℃よりも高い温度に維持された加工 温度に耐えることができない請求範囲第17項の薄膜トランジスタ。 20.基盤上にシリコンを基にした薄膜トランジスタ(TFT)を形成させる方法 であって、約250℃よりも高い温度に維持された加工温度に耐えることができな い低温の柔軟性のある或いは固いプラスチック基盤を提供すること、その基盤に 損傷を与える加工温度を約100μs以上維持することなく、そのプラスチック基盤 上にTFT構造を組み立てることとを含む方法。
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US08/611,318 US5817550A (en) | 1996-03-05 | 1996-03-05 | Method for formation of thin film transistors on plastic substrates |
US08/611,318 | 1996-03-05 | ||
PCT/US1997/003489 WO1997033307A1 (en) | 1996-03-05 | 1997-03-05 | Method for formation of thin film transistors on plastic substrates |
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JP2001508937A true JP2001508937A (ja) | 2001-07-03 |
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JP53192397A Ceased JP2001508937A (ja) | 1996-03-05 | 1997-03-05 | プラスチック基板上に薄膜トランジスタを形成させる方法 |
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US (2) | US5817550A (ja) |
EP (2) | EP1667213A1 (ja) |
JP (1) | JP2001508937A (ja) |
AT (1) | ATE325428T1 (ja) |
AU (1) | AU2318797A (ja) |
DE (1) | DE69735815T2 (ja) |
WO (1) | WO1997033307A1 (ja) |
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CN105261592A (zh) * | 2015-10-30 | 2016-01-20 | 深圳市华星光电技术有限公司 | 一种降低表面粗糙度的低温多晶硅的制备方法及一种低温多晶硅 |
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US5254208A (en) * | 1990-07-24 | 1993-10-19 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing a semiconductor device |
JP3164321B2 (ja) * | 1991-03-26 | 2001-05-08 | キヤノン株式会社 | 液晶素子および表示装置、それらを用いた表示方法 |
US5424244A (en) * | 1992-03-26 | 1995-06-13 | Semiconductor Energy Laboratory Co., Ltd. | Process for laser processing and apparatus for use in the same |
JPH05315361A (ja) * | 1992-05-12 | 1993-11-26 | Ricoh Co Ltd | 半導体薄膜の製造方法及び半導体素子 |
US5346850A (en) * | 1992-10-29 | 1994-09-13 | Regents Of The University Of California | Crystallization and doping of amorphous silicon on low temperature plastic |
US5403762A (en) * | 1993-06-30 | 1995-04-04 | Semiconductor Energy Laboratory Co., Ltd. | Method of fabricating a TFT |
JP3173750B2 (ja) * | 1993-05-21 | 2001-06-04 | 株式会社半導体エネルギー研究所 | 電気光学装置の作製方法 |
US5523587A (en) * | 1993-06-24 | 1996-06-04 | At&T Corp. | Method for low temperature growth of epitaxial silicon and devices produced thereby |
JPH0781919A (ja) * | 1993-07-13 | 1995-03-28 | Toray Ind Inc | 多結晶シリコン膜およびその製造方法 |
US5395481A (en) * | 1993-10-18 | 1995-03-07 | Regents Of The University Of California | Method for forming silicon on a glass substrate |
US5399231A (en) * | 1993-10-18 | 1995-03-21 | Regents Of The University Of California | Method of forming crystalline silicon devices on glass |
US5414276A (en) * | 1993-10-18 | 1995-05-09 | The Regents Of The University Of California | Transistors using crystalline silicon devices on glass |
US5456763A (en) * | 1994-03-29 | 1995-10-10 | The Regents Of The University Of California | Solar cells utilizing pulsed-energy crystallized microcrystalline/polycrystalline silicon |
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1996
- 1996-03-05 US US08/611,318 patent/US5817550A/en not_active Expired - Lifetime
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- 1997-03-05 AU AU23187/97A patent/AU2318797A/en not_active Abandoned
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- 1997-03-05 EP EP06000732A patent/EP1667213A1/en not_active Withdrawn
- 1997-03-05 DE DE69735815T patent/DE69735815T2/de not_active Expired - Fee Related
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- 1997-03-05 WO PCT/US1997/003489 patent/WO1997033307A1/en active IP Right Grant
- 1997-03-05 AT AT97915872T patent/ATE325428T1/de not_active IP Right Cessation
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2007511071A (ja) * | 2003-11-04 | 2007-04-26 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | セルフアラインされたダマシンゲート |
JP2006339205A (ja) * | 2005-05-31 | 2006-12-14 | Dainippon Printing Co Ltd | 薄膜トランジスタ搭載パネル及びその製造方法 |
JP4579054B2 (ja) * | 2005-05-31 | 2010-11-10 | 大日本印刷株式会社 | 薄膜トランジスタ搭載パネル及びその製造方法 |
JP2007095989A (ja) * | 2005-09-29 | 2007-04-12 | Dainippon Printing Co Ltd | 薄膜トランジスタの製造方法 |
EP2355141A2 (en) | 2010-02-08 | 2011-08-10 | Fujifilm Corporation | Semiconductor device, method for producing the semiconductor device, substrate for semiconductor element and method for producing the substrate |
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ATE325428T1 (de) | 2006-06-15 |
DE69735815T2 (de) | 2007-04-05 |
DE69735815D1 (de) | 2006-06-08 |
US5817550A (en) | 1998-10-06 |
EP0956585A4 (en) | 2000-06-14 |
WO1997033307A1 (en) | 1997-09-12 |
EP0956585A1 (en) | 1999-11-17 |
AU2318797A (en) | 1997-09-22 |
US6680485B1 (en) | 2004-01-20 |
EP1667213A1 (en) | 2006-06-07 |
EP0956585B1 (en) | 2006-05-03 |
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