CN104299897B - 具改善阈值电压表现的取代金属栅极的集成电路及其制法 - Google Patents

具改善阈值电压表现的取代金属栅极的集成电路及其制法 Download PDF

Info

Publication number
CN104299897B
CN104299897B CN201410339986.5A CN201410339986A CN104299897B CN 104299897 B CN104299897 B CN 104299897B CN 201410339986 A CN201410339986 A CN 201410339986A CN 104299897 B CN104299897 B CN 104299897B
Authority
CN
China
Prior art keywords
groove
layer
overlying
barrier
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201410339986.5A
Other languages
English (en)
Other versions
CN104299897A (zh
Inventor
K·特雷维诺
Y-H·林
G·P·威尔斯
C·H·孟
T·韩
H·S·王
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries US Inc
Original Assignee
GlobalFoundries Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GlobalFoundries Inc filed Critical GlobalFoundries Inc
Publication of CN104299897A publication Critical patent/CN104299897A/zh
Application granted granted Critical
Publication of CN104299897B publication Critical patent/CN104299897B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Materials Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本发明提供具改善阈值电压表现的取代金属栅极的集成电路及其制法。一种方法包括：提供覆于半导体基板上的介电层。该介电层具有第一凹槽和第二凹槽。在该第一凹槽和该第二凹槽中形成栅极介电层。形成覆于该栅极介电层上的第一阻障层。在所述凹槽内形成功函数材料层。将该功函数材料层和该第一阻障层凹陷至该第一凹槽和该第二凹槽中。该功函数材料层和该第一阻障层形成斜表面。将该栅极介电层凹陷至该第一凹槽和该第二凹槽中。沉积导电栅极电极材料，使得该导电栅极电极材料填充该第一凹槽和该第二凹槽。将该导电栅极电极材料凹陷至该第一凹槽和该第二凹槽中。

Description

具改善阈值电压表现的取代金属栅极的集成电路及其制法
技术领域
本案涉及集成电路及制造集成电路的方法，尤指涉及具有改善的阈值电压表现的取代金属栅极的集成电路及其制造方法。
背景技术
例如为金氧半场效电晶体(metal oxide semiconductor field effecttransistor，MOSFET)、或单纯的场效电晶体(field effect transistor，FET)或金氧半电晶体(MOS transistor)的电晶体为绝大多数半导体集成电路(integrated circuit，IC)的重要组件。场效电晶体包括源极及漏极区域，于其间，电流能在偏压的影响下流经通道，该偏压施加于覆盖在该通道上的栅极电极。某些半导体集成电路，例如高表现微处理器，能包括数百万个场效电晶体。对于此种半导体集成电路而言，减小电晶体尺寸及增加电晶体密度在半导体制造产业中在传统上一直是高优先性。然而，即使电晶体的尺寸减小，仍然必须维持电晶体的表现。
鳍式场效电晶体(FinFET)是一种目标为减小电晶体尺寸又同时维持电晶体表现的电晶体。如图1所示，鳍式场效电晶体200为非平面、三维的电晶体，其部份形成为从半导体基板214向上延伸的薄形鳍片212。为简化说明，图1仅绘示一个栅极216及两个鳍片212，但通常集成电路能具有数千个鳍片及栅极。该半导体基板可为块体硅晶圆(bulk siliconwafer)，鳍片结构从该块体硅晶圆生成，或者，该半导体基板可为设置于支撑基板上的绝缘体上硅晶圆(silicon-on-insulator wafer,SOI wafer)。该绝缘体上硅晶圆包括硅氧化物层及覆于该硅氧化物层上的含硅材料层。鳍片结构从该含硅材料层形成。该鳍片结构通常是使用传统的光微影(photolithographic)或非等向性(anisotropic)蚀刻工艺形成(例如，反应性离子蚀刻(reactive ion etching，RIE)或相似者)。垂直栅极216设置于鳍片上方，使得鳍片的两个垂直侧壁218形成电晶体的通道。
取代金属栅极(Replacement metal gate，RMG)处理通常在鳍式电晶体形成期间使用。图2至图5绘示使用取代金属栅极工艺形成具有P型通道场效电晶体(PFET)12及N型通道场效电晶体(NFET)14的集成电路10的一部分的一种习知方法。根据图2，介电材料层16覆于半导体材料18上。该半导体材料为非平面电晶体例如鳍式电晶体的鳍片结构。该介电材料层例如为硅氧化物。对应于PFET 12的第一凹槽20以及对应于NFET 14的第二凹槽22形成于介电材料层16中。栅极介电层24沉积于该些凹槽中。第一阻障材料层或其组合26沉积覆于该栅极介电层24上，而第二阻障材料层或其组合28沉积覆于该第一阻障材料层或其组合26上。该第一阻障材料层或其组合26可以例如为覆于钛氮化物上的钽氮化物，而该第二阻障材料层或其组合28可以例如为钛氮化物。掩模材料30沉积覆于该第二阻障材料层或其组合28上，而光阻32形成覆于该掩模材料30上。
参考图3，光阻被图案化且掩模材料30被对应地蚀刻成覆盖凹槽20中的第二阻障材料层28的一部份。接着，第二阻障材料层28从凹槽22以及凹槽20的一部分被蚀刻掉。参考图4，光阻32和掩模材料30被移除，然后功函数材料34被共形地沉积在凹槽20和22内。功函数材料例如钛铝(TiAl)。额外的TiN层(未图示)沉积覆于功函数材料上，然后沉积例如钨的栅极电极材料36。接着，如图5所示，执行凹陷蚀刻以使栅极电极材料36凹陷于凹槽20和22内。
RMG的传统工艺造成难以填充的高长宽比的凹槽。如图5所示，钨的沉积通常会造成钨栅极电极内的孔洞。若栅极电极内出现孔洞，回蚀(etch back)该栅极电极以移除该孔洞会造成移除掉比期望还多的栅极电极。接着，这种移除孔洞的钨的回蚀会造成栅极电极高度变化。此外，传统工艺会留下栅极介电质「桁条(stringer)」40。这些桁条在此阶段不能被移除，因为若栅极介电质是铪氧化物或类似的高k介电常数材料(通常如此)，则湿蚀刻无法有效移除这些桁条且干等离子蚀刻这些栅极介电质桁条会损坏NFET 14的钛氮化物及钽氮化物层。这些缺点被视为不利于阈值电压表现。
因此，期望提供具有改善的阈值电压表现的取代金属栅极的集成电路制造方法。期望提供具有改善的阈值电压表现的取代金属栅极的集成电路。再者，从后述的实施方式以及所附权利要求书搭配随附图式以及此背景技术，其他的期望特征和特性将变得明显。
发明内容
提供具有改善的阈值电压表现的取代金属栅极的集成电路及其制造方法。根据例示实施例，一种集成电路制造方法包括：提供覆于半导体基板上的块体介电层。该块体介电层具有第一凹槽和第二凹槽。在该第一凹槽和该第二凹槽中形成栅极介电层。形成覆于该栅极介电层上的第一阻障层。在该第一凹槽和该第二凹槽内形成功函数材料层。将该功函数材料层和该第一阻障层凹陷至该第一凹槽和该第二凹槽中。该功函数材料层和该第一阻障层相对于该块体介电层的平坦表面形成斜表面(beveled surface)。将该栅极介电层凹陷至该第一凹槽和该第二凹槽中。沉积导电栅极电极材料，使得该导电栅极电极材料填充该第一凹槽和该第二凹槽。将该导电栅极电极材料凹陷至该第一凹槽和该第二凹槽中。
根据另一例示实施例，一种集成电路制造方法包括：提供覆于半导体基板上的介电层，该介电层具有第一凹槽和第二凹槽。在该第一凹槽和该第二凹槽中形成栅极介电层，且形成覆于该栅极介电层上的第一阻障金属层。沉积覆于该第一阻障金属层上的第二阻障金属层。形成图案化掩模，使得该图案化掩模部分地填充该第一凹槽以及覆于该第二阻障金属层的第一部分上。暴露该第二阻障金属层的第二部分。移除该第二阻障金属层的该第二部分，且移除该图案化掩模。在该第一凹槽和该第二凹槽内形成功函数材料层。在该第一凹槽和该第二凹槽内形成掩模材料，且蚀刻该掩模材料，使得该掩模材料填充该第一凹槽的一部分和该第二凹槽的一部分。非等向性蚀刻该功函数材料层的一部分和该第一阻障金属层的一部分。蚀刻该栅极介电层的一部分，且从该第一凹槽和该第二凹槽移除该掩模材料。沉积导电栅极材料覆于该第一凹槽和该第二凹槽中的该功函数材料层上。移除该第一凹槽和该第二凹槽内的该导电栅极材料的一部分。
根据例示实施例，一种具有金属栅极结构的集成电路，包括：栅极介电层，具有两个相对构件以及接合构件，该接合构件覆于半导体基板上以及接合该两个相对构件。第一阻障金属层，覆于该栅极介电层上，且功函数材料层，覆于该第一阻障金属层上。导电栅极电极，具有直线部分和剖面部分。该直线部分覆于该功函数材料层上。该剖面部分垂直于该直线部分以及覆于该栅极介电层、该第一阻障金属层和该功函数材料层上。该第一阻障金属层和该功函数材料层具有斜表面。
附图说明
以下将配合随附图式描述各种实施例，其中，相同的元件符号代表相似的元件，以及其中：
图1是先前技术中已知的单栅极FinFET的透视图；
图2至图5是先前技术中已知用于形成FinFET的步骤的剖面图；以及
图3至图11是根据例示实施例的提供具有改善的阈值电压表现的取代金属栅极的集成电路及其制造方法的剖面图。
符号说明
10 集成电路
12 P型通道场效电晶体、PFET
14 N型通道场效电晶体、NFET
16 介电材料层
18 半导体材料
20 第一凹槽
22 第二凹槽
24 栅极介电层
26 第一阻障材料层或其组合
28 第二阻障材料层或其组合
30 掩模材料
32 光阻
34 功函数材料
36 栅极电极材料
40 栅极介电质桁条
100 集成电路
102 半导体基板
104 介电层
106 第一凹槽
108 第二凹槽
110 PFET
112 NFET
114 栅极介电层
116 双层
118 钛氮化物层
120 掩模材料
122 光阻层
124 部分、未暴露部分
126 钛铝层
128 第二掩模材料层
130 暴露表面
131 斜、V形表面
132 表面
133 开口
134 导电栅极电极
200 鳍式场效电晶体
212 鳍片
214 半导体基板
216 栅极
218 侧壁
220 侧壁间隔件
222 介电层。
具体实施方式
下列实施方式在本质上仅为例示且无意限制各种实施例或其应用和用途。再者，无意受到前述背景技术或后述实施方式中所提的任何理论的限制。
在此提出具有改善的阈值电压表现的取代金属栅极的集成电路及其制造方法的各种实施例。NFET和PFET的实施例分别采用TiN/TaN/TiAl和TiN/TaN/TiN/TiAl的新颖的功函数布局设计。以现有的功函数组构所达成的传统阈值电压装置读出被认为不良，其中，装置导通时的高阈值电压测量值达到0.8V。此处所可考虑的各种实施例增加RMG填充能力，维持后续金属填充步骤的低长宽比并因而改善栅极电极金属凹陷工艺稳定性。另外，NFET布局藉由导入凹角(chamfer angle)而最佳化，该凹角将栅极电极沉积中可能产生的孔洞最小化或消除。整体而言，此新颖的布局包括得以驱动阈值电压表现的改良，其具有典型装置设计规格所需的可接受限度(亦即，0.3V)。
图6至图10显示一种具有改善的阈值电压的取代金属栅极的集成电路(IC)100的制造方法。制造IC的各种步骤众所周知，故为求简洁，许多传统步骤在此将仅简略提及或完全省略而不提供已知的工艺细节。如图6所示的IC 100的一部分在制造的早期阶段。该方法包含提供覆于由半导体材料形成的半导体基板102上的介电层104。如在此所使用者，用语「覆于…上(overlie)」意指直接置于其上或置于上方，使得中间材料至于其间。例如，介电层104可直接置于半导体基板102上或可覆于该半导体基板上，使得介电层或其他层置于该介电层104与该半导体基板102之间。在例示实施例中，半导体基板102为块体硅基板，而半导体材料包含硅。例如，块体硅基板能由相当纯的硅、与锗或碳混合的硅或与某些其他常用于制造集成电路的半导体材料混合的硅形成。或者，块体硅基板102的半导体材料可为锗、镓砷化物等等。半导体材料不需要被掺杂，但其可被极轻浓度掺杂为N型或P型，而不影响在此所述的工艺。或者，半导体基板102可被设在支撑基板上的绝缘体上硅(SOI)晶圆支撑。SOI晶圆包含硅氧化物层和覆于该硅氧化物层上的含硅材料层。半导体基板102可为含硅材料层。在另一实施例中，半导体基板102是由半导体材料形成的FinFET的鳍片结构。介电层104是由绝缘材料(例如，硅氧化物)形成。
第一凹槽106和第二凹槽108形成于介电层104中。PFET 110将随后形成在第一凹槽106中，以及NFET 112将随后形成在第二凹槽108中，如下详述。虽然于图6中图示两个凹槽，但应了解在介电层104中可形成超过两个凹槽。所述凹槽具有大约20纳米至大约500纳米的宽度。所述凹槽可使用例如N2/H2/CH4化学品以等离子蚀刻法进行蚀刻。虽然图6图示在介电层104中形成两个凹槽，但应了解到在此所述的取代金属栅极可形成在两个间隔件之间。就此而言，如图7所示，已知在先前技术中，虚拟栅极(dummy gate)例如由多晶硅形成，接着在该虚拟栅极周围形成侧壁间隔件220。介电层222沉积覆于虚拟栅极和侧壁间隔件上。介电层的平坦化藉由例如化学机械平坦化(CMP)而暴露虚拟栅极，然后移除虚拟栅极，留下侧壁间隔件之间的两个凹槽106和108。如在此使用者，用语「凹槽(trench)」是指开口或未占用的空间。
在一个实施例中，栅极介电层114是已沉积的绝缘体，例如硅氧化物、硅氮化物、任何种类的高介电常数(高k)材料，其中，介电常数是大于二氧化硅的介电常数(3.9)，例如铪氧化物等等。已沉积的绝缘体可藉由例如化学气相沉积(CVD)、原子层沉积(ALD)、低压化学气相沉积(LPCVD)或等离子增强化学气相沉积(PECVD)进行沉积。在一个实施例中，栅极介电层114具有大约10埃至大约20埃的厚度范围的铪氧化物，但该栅极介电层114的实际厚度可依据所实施的集成电路中所应用的FinFET来决定。
该方法继续，形成PFET 110的金属栅极和NFET 112的金属栅极。就此而言，阻障金属形成覆于栅极介电层114上。适合用作为阻障金属的金属包含那些避免栅极电极(将在后面讨论)的金属离子迁移进入栅极介电层114和介电层104中者。此外，针对粘附栅极电极(后面讨论)和栅极介电层114的能力来选择金属。在实施例中，钛氮化物层形成在凹槽内以及覆于栅极介电层114上。钛氮化物层可藉由例如物理气相沉积(PVD)进行沉积。钛氮化物层的厚度例如在大约5埃至大约15埃的范围内。钽氮化物在暴露凹槽中沉积覆于钛氮化物上以形成钽氮化物层。钽氮化物层藉由例如PVD沉积。在实施例中，钽氮化物层具有例如在大约3纳米至大约5纳米的范围内的厚度。覆于栅极介电层114上的钛氮化物层以及覆于钛氮化物层上的钽氮化物层在图式中标示为双层(bilayer)116。
另一钛氮化物层118如上所述藉由沉积钛氮化物而形成在钽氮化物层上。钛氮化物层能沉积至例如在大约3纳米至大约5纳米的范围内的厚度。掩模材料120沉积、填充第一凹槽106和第二凹槽108，而光阻层122形成覆于该掩模材料120上。掩模材料120可以是对钽氮化物具有蚀刻选择性的任何适合材料，以下将详细讨论。适合的掩模材料范例包含(但不限于)可从纽泽西的莫里斯敦的Honeywell International股份有限公司取得的DUOTM 248。掩模材料120藉由旋转涂布、滚轮涂布、喷雾等等形成覆于钛氮化物层118上。掩模材料120沉积至例如在大约130纳米至大约180纳米的范围内的厚度。
参考图8，光阻层122被图案化，掩模材料120被蚀刻成在PFET 110的第一凹槽106中覆盖钛氮化物层118的一部分124，然后移除该光阻层122。若掩模材料是Honeywell的DUO248，则掩模材料120可使用例如N2/H2/CH4化学品以等离子蚀刻法进行蚀刻。钛氮化物层118的暴露部分的从第一和第二凹槽移除，留下该第一凹槽106中的未暴露部分124。钛氮化物藉由例如SPN(硫酸和过氧化物)的化学品而被选择性移除，其中，钛氮化物对钽氮化物的选择性超过100纳米。然后，移除掩模材料120的剩余部分。
接着，如图9所示，沉积功函数材料(钛铝)以形成覆于钛氮化物层118的部分124以及钽氮化物与钛氮化物双层116上的钛铝层126。钛铝将装置阈值电压表现有效地稳定在大约0.3V的中心目标。在先进的半导体制造中，根据特定的布局设计来可靠控制阈值电压参数的能力很重要，用以保证有效的装置导通表现。在实施例中，钛铝层能藉由例如ALD沉积并具有在大约4纳米至大约8纳米的范围内的厚度。在沉积钛铝层后，第二掩模材料层128在凹槽106和108内共形地沉积覆于钛铝层126上。第二掩模材料层128沉积至大约130纳米至大约180纳米的范围内的厚度。第二掩模材料层可以是与掩模材料120相同的材料，并且可以使用与用来蚀刻掩模材料120相同的化学品来进行蚀刻。
该方法继续，参考图10，第二掩模材料128被蚀刻，直到凹入凹槽106和108中。在实施例中，第二掩模材料128被蚀刻成该第二掩模材料128的暴露表面130比钛氮化物层118中最接近凹槽106的开口133的表面132还靠近凹槽106的开口133。钛铝层126的一部分、暴露的阻障金属钛氮化物与钽氮化物116以及栅极介电层114从凹槽106和108移除。阻障金属材料和栅极介电层(例如铪氧化物)能藉由干等离子蚀刻法(例如使用BCl3/Cl2的反应性离子蚀刻(RIE))移除。第二掩模材料128保护钛铝层126和阻障金属钛氮化物与钽氮化物免于受到干等离子蚀刻。由于蚀刻是非等向性的，所以金属会相对于块体介电层104的平坦表面101形成靠近凹槽的开口133的斜或「V」形表面131。
参考图11，在蚀刻各种金属层和栅极介电质后，移除第二掩模材料128的剩余部分。执行钛氮化物沉积以全面性地形成钛氮化物层(未图示)。在实施例中，钽氮化物具有在大约2纳米至大约4纳米的范围内的厚度，例如2.5纳米。在沉积钛氮化物后，在PFET电晶体110的凹槽106以及NFET电晶体112的凹槽108内沉积导电栅极电极层134以填充所述凹槽。导电栅极电极134可由任何适合导电材料形成，例如铝或钨。由于阻障金属材料和功函数材料层的斜表面131，导电栅极电极134以「由下往上(bottum-up)」减少或消除其中的孔洞的方式沉积在凹槽内。执行CMP工艺以移除覆于介电层104上的覆盖层(overburden)。在实施例中，导电栅极电极134的一部分在凹槽内被移除，以在该凹槽内提供空间供绝缘盖层(未图示)覆盖该导电栅极电极134。若导电栅极电极为钨，则此钨能藉由使用氢氟酸化学的反应性离子蚀刻(RIE)而被蚀刻。
之后，以进一步的处理步骤继续集成电路的制造，能执行这些步骤完成集成电路，如技术领域中所熟知者。传统上，进一步的步骤包含，例如，在对齐取代金属栅极(藉由移除介电层以及植入导电率决定性离子至半导体基板中而形成者)的半导体基板中形成源极和漏极区域、形成接触件(藉由在绝缘层之上沉积光阻材料层、微影图案化、蚀刻形成接触孔洞、以及在该孔洞中沉积导电材料而形成接触件所形成者)、以及在该绝缘层上方对整个装置形成一层或多层图案化导电层等等。在此所揭露的主题并非意图排除任何后续形成及测试本技术领域中熟知的完成电路的处理步骤。此外，就上述的任何工艺步骤而言，能在沉积一层后，采用一道或多道加热处理及/或退火程序，如本技术领域中广为人知者。
因此，已描述具有改善的阈值电压表现的取代金属栅极的集成电路的制造方法以及具有改善的阈值电压表现的取代金属栅极的集成电路。取代金属栅极形成有金属层，该金属层具有允许以最少孔洞或毫无孔洞的情形形成导电栅极电极的斜或「V」形表面。因此，得以避免回蚀栅极电极以移除孔洞，并且得以最小化栅极电极变化。此外，因为在导电栅极电极中形成的孔洞都被最小化或消除，所以可以不必进行不想要的导电栅极电极蚀刻，而可让更多的导电栅极电极材料停留在凹槽中。这可大幅改善接触电阻。再者，在取代金属栅极中使用钛铝功函数材料以稳定阈值电压。栅极介电质桁条也被移除，因为凹槽中的金属层受到第二掩模材料层保护，该第二掩模材料层在功函数材料沉积后以及栅极电极材料沉积前沉积。就此而言，提供一种新颖布局，其包括得以驱动典型装置设计规格所需的阈值电压表现的改良。
虽然已在本发明的前述实施方式中提出至少一个例示实施例，但应了解仍存在大量变体。也应了解到，例示实施例仅为范例，无意以任何方式限制本发明的范围、应用性或组构。相反地，前述实施方式将提供本技术领域中具有通常知识者用于实施本发明的例示实施例的方便蓝图。应了解到，在不背离所附权利要求书中所提出的本发明范围的情形下，可对例示实施例中所述的功能及元件配置做出各种改变。

Claims (20)

1.一种制造集成电路的方法，该方法包括：
提供覆于半导体基板上的块体介电层，该块体介电层具有第一凹槽和第二凹槽；
在该第一凹槽和该第二凹槽中形成栅极介电层；
形成覆于该栅极介电层上的第一阻障层；
在该第一凹槽和该第二凹槽内形成功函数材料层；
将该功函数材料层和该第一阻障层凹陷至该第一凹槽和该第二凹槽中，其中，该功函数材料层和该第一阻障层相对于该块体介电层的平坦表面形成斜表面；
将该栅极介电层凹陷至该第一凹槽和该第二凹槽中；
沉积导电栅极电极材料，使得该导电栅极电极材料填充该第一凹槽和该第二凹槽，其中，该导电栅极电极材料覆盖且接触该功函数材料层和该第一阻障层形成的斜表面；以及
将该导电栅极电极材料凹陷至该第一凹槽和该第二凹槽中。
2.根据权利要求1所述的方法，进一步包括在形成该第一阻障层后形成第二阻障层，其中，该第二阻障层在该第一凹槽中覆于该第一阻障层的一部分上，但该第二凹槽中没有该第二阻障层。
3.根据权利要求2所述的方法，其中，形成该第二阻障层包括：
形成该第二阻障层覆于该第一阻障层上；
在该第二阻障层上形成掩模；
在该掩模上形成光阻；
图案化该光阻以形成图案化光阻；
使用该图案化光阻作为蚀刻掩模而蚀刻该掩模；
从该第二凹槽和该第一凹槽的一部分移除该第二阻障层。
4.根据权利要求3所述的方法，其中，形成该第二阻障层包括形成氮化钛层。
5.根据权利要求1所述的方法，其中，提供该块体介电层包括提供氧化铪层，以及其中，凹陷该栅极介电层包括使用干等离子蚀刻法蚀刻栅极介电层桁条。
6.根据权利要求1所述的方法，其中，沉积该第一阻障层包括沉积氮化钛层。
7.根据权利要求6所述的方法，其中，沉积该第一阻障层包括沉积覆于该氮化钛层上的氮化钽层。
8.根据权利要求1所述的方法，其中，形成该功函数材料层包括形成钛铝。
9.根据权利要求1所述的方法，其中，凹陷该功函数材料层和该第一阻障层包括：
在形成该功函数材料层后，沉积覆于该功函数材料层上的掩模材料；
在该掩模材料上形成图案化光阻；
使用该图案化光阻作为蚀刻掩模而蚀刻该掩模材料，其中，该掩模材料保留在该第一凹槽和该第二凹槽中；
使用该掩模材料、该第一阻障层和该栅极介电层作为蚀刻掩模而移除该功函数材料层的一部分；以及
使用该掩模材料、该功函数材料层和该栅极介电层作为蚀刻掩模而移除该第一阻障层的一部分。
10.根据权利要求1所述的方法，其中，沉积该导电栅极电极材料包括沉积钨。
11.根据权利要求1所述的方法，其中，提供覆于该半导体基板上的该块体介电层包括提供覆于后续形成的FinFET装置的鳍片结构上的该介电层。
12.根据权利要求1所述的方法，其中，该栅极介电层与侧壁间隔件实际接触。
13.一种制造集成电路的方法，该方法包括：
提供覆于半导体基板上的介电层，该介电层具有第一凹槽和第二凹槽；
在该第一凹槽和该第二凹槽中形成栅极介电层；
形成覆于该栅极介电层上的第一阻障金属层；
沉积覆于该第一阻障金属层上的第二阻障金属层；
形成图案化掩模，使得该图案化掩模部分地填充该第一凹槽以及覆于该第二阻障金属层的第一部分上，以及其中，暴露该第二阻障金属层的第二部分；
移除该第二阻障金属层的该第二部分；
移除该图案化掩模；
在该第一凹槽和该第二凹槽内形成功函数材料层；
在该第一凹槽和该第二凹槽内形成掩模材料；
蚀刻该掩模材料，使得该掩模材料填充该第一凹槽的一部分和该第二凹槽的一部分；
非等向性蚀刻该功函数材料层的一部分和该第一阻障金属层的一部分；
蚀刻该栅极介电层的一部分；
从该第一凹槽和该第二凹槽移除该掩模材料；
沉积导电栅极材料覆于该第一凹槽和该第二凹槽中的该功函数材料层上；以及
移除该第一凹槽和该第二凹槽内的该导电栅极材料的一部分。
14.根据权利要求13所述的方法，其中，蚀刻该栅极介电层的一部分包括使用干等离子工艺蚀刻该栅极介电层的一部分。
15.根据权利要求13所述的方法，其中，非等向性蚀刻该功函数材料层的一部分和该第一阻障金属层的一部分包括形成该第一阻障金属层和该功函数材料层的斜表面。
16.根据权利要求13所述的方法，其中，形成该栅极介电层包括形成氧化铪层。
17.根据权利要求13所述的方法，其中，形成该第一阻障金属层包括沉积氮化钛层以及沉积氮化钽层覆于该氮化钛层上。
18.根据权利要求13所述的方法，其中，形成该功函数材料层包括形成钛铝层。
19.根据权利要求13所述的方法，其中，沉积该第二阻障金属层包括沉积氮化钛层。
20.一种具有金属栅极结构的集成电路，包括：
栅极介电层，具有两个相对构件以及接合构件，该接合构件覆于半导体基板上以及接合该两个相对构件；
第一阻障金属层，覆于该栅极介电层上；
功函数材料层，覆于该第一阻障金属层上；以及
导电栅极电极，具有直线部分和剖面部分，其中，该直线部分覆于该功函数材料层上，其中，该剖面部分垂直于该直线部分以及覆于该栅极介电层、该第一阻障金属层和该功函数材料层上，以及其中，该第一阻障金属层和该功函数材料层形成有斜表面，且该第一阻障金属层和该功函数材料层与该导电栅极电极的该剖面部分接触。
CN201410339986.5A 2013-07-17 2014-07-17 具改善阈值电压表现的取代金属栅极的集成电路及其制法 Active CN104299897B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/943,944 2013-07-17
US13/943,944 US9147680B2 (en) 2013-07-17 2013-07-17 Integrated circuits having replacement metal gates with improved threshold voltage performance and methods for fabricating the same

Publications (2)

Publication Number Publication Date
CN104299897A CN104299897A (zh) 2015-01-21
CN104299897B true CN104299897B (zh) 2017-04-05

Family

ID=52319573

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410339986.5A Active CN104299897B (zh) 2013-07-17 2014-07-17 具改善阈值电压表现的取代金属栅极的集成电路及其制法

Country Status (3)

Country Link
US (1) US9147680B2 (zh)
CN (1) CN104299897B (zh)
TW (1) TWI524397B (zh)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI653762B (zh) * 2014-10-08 2019-03-11 聯華電子股份有限公司 具有金屬閘極之半導體元件之製作方法
TWI635535B (zh) * 2015-03-10 2018-09-11 聯華電子股份有限公司 具有不同臨界電壓的金屬閘極的半導體製程及半導體結構
KR102271239B1 (ko) * 2015-03-23 2021-06-29 삼성전자주식회사 반도체 장치 및 이의 제조 방법
KR102342847B1 (ko) * 2015-04-17 2021-12-23 삼성전자주식회사 반도체 소자 및 그 제조 방법
US9818841B2 (en) * 2015-05-15 2017-11-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure with unleveled gate structure and method for forming the same
US9583485B2 (en) 2015-05-15 2017-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field effect transistor (FinFET) device structure with uneven gate structure and method for forming the same
CN106531776B (zh) * 2015-09-11 2021-06-29 联华电子股份有限公司 半导体结构
US10008574B2 (en) * 2015-11-30 2018-06-26 Taiwan Semiconductor Manufacturing Co., Ltd. Gate structure and method of fabricating the same
KR102474431B1 (ko) 2015-12-08 2022-12-06 삼성전자주식회사 반도체 소자의 제조방법
US9437714B1 (en) 2015-12-09 2016-09-06 International Business Machines Corporation Selective gate contact fill metallization
US9865703B2 (en) * 2015-12-31 2018-01-09 International Business Machines Corporation High-K layer chamfering to prevent oxygen ingress in replacement metal gate (RMG) process
US10283605B2 (en) * 2016-01-29 2019-05-07 Taiwan Semiconductor Manufacturing Co., Ltd Self-aligned metal gate etch back process and device
US20170345912A1 (en) * 2016-05-26 2017-11-30 Globalfoundries Inc. Methods of recessing a gate structure using oxidizing treatments during a recessing etch process
US10043886B2 (en) * 2016-08-03 2018-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gate formation through etch back process
US10269917B2 (en) 2016-10-19 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a FinFET with work function tuning layers having stair-step increment sidewalls
US20180190546A1 (en) * 2016-12-29 2018-07-05 Globalfoundries Inc. Method for forming replacement metal gate and related device
US10319826B2 (en) * 2017-04-12 2019-06-11 International Business Machines Corporation Replacement metal gate stack with oxygen and nitrogen scavenging layers
US10056303B1 (en) * 2017-04-21 2018-08-21 Globalfoundries Inc. Integration scheme for gate height control and void free RMG fill
CN107464758A (zh) * 2017-09-07 2017-12-12 上海华力微电子有限公司 一种半导体器件的形成方法
US20190086809A1 (en) * 2017-09-21 2019-03-21 United Microelectronics Corp. Method for fabricating semiconductor structure involving cleaning mask material
US10636890B2 (en) * 2018-05-08 2020-04-28 Globalfoundries Inc. Chamfered replacement gate structures
KR102560369B1 (ko) * 2018-05-18 2023-07-28 삼성전자주식회사 반도체 소자
KR102593708B1 (ko) * 2018-08-14 2023-10-26 삼성전자주식회사 반도체 장치 및 반도체 장치의 제조 방법
US11069531B2 (en) * 2018-10-31 2021-07-20 Taiwan Semiconductor Manufacturing Company, Ltd. Replacement gate methods that include treating spacers to widen gate
US10833169B1 (en) * 2019-04-22 2020-11-10 Globalfoundries Inc. Metal gate for a field effect transistor and method
DE102020107241A1 (de) * 2019-10-29 2021-04-29 Taiwan Semiconductor Manufacturing Co., Ltd. Finnen-feldeffekttransistor-bauelement und verfahren zu dessen herstellung
US11690216B2 (en) * 2019-12-13 2023-06-27 Micron Technology, Inc. Structure to reduce bending in semiconductor devices
CN111627993B (zh) * 2020-06-05 2023-01-06 福建省晋华集成电路有限公司 栅极结构与其制作方法
CN111627992B (zh) * 2020-06-05 2023-04-04 福建省晋华集成电路有限公司 栅极结构与其制作方法
US11610982B2 (en) * 2020-09-15 2023-03-21 Taiwan Semiconductor Manufacturing Co., Ltd. Void elimination for gap-filling in high-aspect ratio trenches
CN117673032A (zh) * 2022-09-01 2024-03-08 长鑫存储技术有限公司 半导体结构及其制备方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7029959B1 (en) * 2003-05-06 2006-04-18 Advanced Micro Devices, Inc. Source and drain protection and stringer-free gate formation in semiconductor devices
DE102004031385B4 (de) * 2004-06-29 2010-12-09 Qimonda Ag Verfahren zur Herstellung von Stegfeldeffekttransistoren in einer DRAM-Speicherzellenanordnung, Feldeffekttransistoren mit gekrümmtem Kanal und DRAM-Speicherzellenanordnung
US7611943B2 (en) * 2004-10-20 2009-11-03 Texas Instruments Incorporated Transistors, integrated circuits, systems, and processes of manufacture with improved work function modulation
KR100793011B1 (ko) * 2007-02-16 2008-01-08 에스케이에너지 주식회사 리튬이차전지의 제조방법
US8268085B2 (en) * 2009-03-20 2012-09-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming metal gate transistors
US8357579B2 (en) * 2010-11-30 2013-01-22 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuits
CN102683397B (zh) * 2011-03-17 2016-04-06 联华电子股份有限公司 金属栅极结构及其制作方法
CN102760758A (zh) * 2011-04-26 2012-10-31 联华电子股份有限公司 金属栅极结构
US8461049B2 (en) * 2011-10-11 2013-06-11 United Microelectronics Corp. Method for fabricating semiconductor device

Also Published As

Publication number Publication date
US20150021694A1 (en) 2015-01-22
CN104299897A (zh) 2015-01-21
TW201505081A (zh) 2015-02-01
US9147680B2 (en) 2015-09-29
TWI524397B (zh) 2016-03-01

Similar Documents

Publication Publication Date Title
CN104299897B (zh) 具改善阈值电压表现的取代金属栅极的集成电路及其制法
TWI701830B (zh) 半導體裝置及其形成方法
US8334181B1 (en) Germanium MOSFET devices and methods for making same
US9564530B2 (en) Integrated circuit structure and method with solid phase diffusion
TWI683356B (zh) 半導體裝置及其形成方法
CN104867967B (zh) 半导体器件及其制造方法
TWI677981B (zh) 積體晶片及其形成方法
US8936986B2 (en) Methods of forming finfet devices with a shared gate structure
TWI484567B (zh) 半導體結構與其製造方法
TWI650804B (zh) 半導體元件及其製作方法
TWI518755B (zh) 積體電路結構及其製作方法
CN106711042A (zh) 用于半导体中段制程（meol）工艺的方法和结构
KR102102731B1 (ko) 반도체 디바이스 및 제조 방법
TWI721515B (zh) 用於中電壓裝置的凹槽閘極
US20240162290A1 (en) Integrated chip and method of forming thereof
TW201911386A (zh) 半導體元件及其製作方法
TW201742123A (zh) 半導體裝置及其形成方法
TW201725612A (zh) 半導體元件及其形成方法
US20230099320A1 (en) Method And Device For Forming Metal Gate Electrodes For Transistors
US11145508B2 (en) Forming a fin cut in a hardmask
US20220344491A1 (en) Multi-layer dielectric refill for profile control in semiconductor devices
TW202209678A (zh) 具有不同通道層的多重閘極裝置
CN113809011B (zh) 半导体结构及其形成方法
US20060121740A1 (en) Semiconductor integrated circuit device and method for fabricating the same
JP2019046874A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20210225

Address after: California, USA

Patentee after: Lattice chip (USA) integrated circuit technology Co.,Ltd.

Address before: Greater Cayman Islands, British Cayman Islands

Patentee before: GLOBALFOUNDRIES Inc.

TR01 Transfer of patent right