TWI524397B - 具有改善的閾値電壓表現的取代金屬閘極的積體電路及其製造方法 - Google Patents

具有改善的閾値電壓表現的取代金屬閘極的積體電路及其製造方法 Download PDF

Info

Publication number
TWI524397B
TWI524397B TW103104527A TW103104527A TWI524397B TW I524397 B TWI524397 B TW I524397B TW 103104527 A TW103104527 A TW 103104527A TW 103104527 A TW103104527 A TW 103104527A TW I524397 B TWI524397 B TW I524397B
Authority
TW
Taiwan
Prior art keywords
layer
recess
forming
barrier
mask
Prior art date
Application number
TW103104527A
Other languages
English (en)
Other versions
TW201505081A (zh
Inventor
克莉斯提娜 特拉維拉
遠宏 林
加布里 帕德朗 威爾斯
常和 孟
太俊 韓
孔成 翁
Original Assignee
格羅方德半導體公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 格羅方德半導體公司 filed Critical 格羅方德半導體公司
Publication of TW201505081A publication Critical patent/TW201505081A/zh
Application granted granted Critical
Publication of TWI524397B publication Critical patent/TWI524397B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Description

具有改善的閾值電壓表現的取代金屬閘極的積體電路及其製造方法
本案係關於積體電路及製造積體電路之方法，尤指關於具有改善的閾值電壓表現的取代金屬閘極之積體電路及其製造方法。
例如為金氧半場效電晶體(metal oxide semiconductor field effect transistor，MOSFET)、或單純的場效電晶體(field effect transistor，FET)或金氧半電晶體(MOS transistor)之電晶體係為絕大多數半導體積體電路(integrated circuit，IC)的重要組件。場效電晶體包括源極及汲極區域，於其間，電流係能在偏壓的影響下流經通道，該偏壓係施加於覆蓋在該通道上的閘極電極。某些半導體積體電路，例如高表現微處理器，係能包括數百萬個場效電晶體。對於此種半導體積體電路而言，減小電晶體尺寸及增加電晶體密度在半導體製造產業中在傳統上一直是高 優先性。然而，即使電晶體的尺寸減小，仍然必須維持電晶體的表現。
鰭式場效電晶體(FinFET)係一種目標為減 小電晶體尺寸又同時維持電晶體表現的電晶體。如第1圖所示，鰭式場效電晶體200係為非平面、三維之電晶體，其係部份形成為從半導體基板214向上延伸之薄形鰭片212。為簡化說明，第1圖僅繪示一個閘極216及兩個鰭片212，但通常積體電路能具有數千個鰭片及閘極。該半導體基板可為塊體矽晶圓(bulk silicon wafer)，鰭片結構係從該塊體矽晶圓生成，或者，該半導體基板可為設置於支撐基板上之絕緣體上矽晶圓(silicon-on-insulator wafer,SOI wafer)。該絕緣體上矽晶圓包括矽氧化物層及覆於該矽氧化物層上之含矽材料層。鰭片結構係從該含矽材料層形成。該鰭片結構通常是使用傳統的光微影或非等向性蝕刻製程形成(例如，反應性離子蝕刻(reactive ion etching，RIE)或相似者)。垂直閘極216係設置於鰭片上方，使得鰭片之兩個垂直側壁218形成電晶體之通道。
取代金屬閘極(Replacement metal gate，RMG) 處理通常係在鰭式電晶體形成期間使用。第2至5圖係繪示使用取代金屬閘極製程形成具有P型通道場效電晶體(PFET)12及N型通道場效電晶體(NFET)14之積體電路10之一部分的一種習知方法。根據第2圖，介電材料層16覆於半導體材料18上。該半導體材料係為非平面電晶體例如鰭式電晶體之鰭片結構。該介電材料層係例如為矽氧化 物。對應於PFET 12之第一凹槽20以及對應於NFET 14之第二凹槽22係形成於介電材料層16中。閘極介電層24係沉積於該些凹槽中。第一阻障材料層或其組合26係沉積覆於該閘極介電層24上，而第二阻障材料層或其組合28係沉積覆於該第一阻障材料層或其組合26上。該第一阻障材料層或其組合26可以例如為覆於鈦氮化物上的鉭氮化物，而該第二阻障材料層或其組合28可以例如為鈦氮化物。遮罩材料30係沉積覆於該第二阻障材料層或其組合28上，而光阻32係形成覆於該遮罩材料30上。
參考第3圖，光阻被圖案化且遮罩材料30 被對應地蝕刻成覆蓋凹槽20中之第二阻障材料層28之一部份。接著，第二阻障材料層28從凹槽22以及凹槽20之一部分被蝕刻掉。參考第4圖，光阻32和遮罩材料30係被移除，然後功函數材料34被共形地沉積在凹槽20和22內。功函數材料係例如鈦鋁(TiAl)。額外的TiN層(未圖示)係沉積覆於功函數材料上，然後沉積例如鎢之閘極電極材料36。接著，如第5圖所示，執行凹陷蝕刻以使閘極電極材料36凹陷於凹槽20和22內。
RMG之傳統製程造成難以填充之高長寬比 的凹槽。如第5圖所示，鎢之沉積通常會造成鎢閘極電極內的孔洞。若閘極電極內出現孔洞，回蝕(etch back)該閘極電極以移除該孔洞會造成移除掉比期望還多的閘極電極。接著，這種移除孔洞的鎢之回蝕會造成閘極電極高度變化。此外，傳統製程會留下閘極介電質「桁條(stringer)」 40。這些桁條在此階段不能被移除，因為若閘極介電質是鉿氧化物或類似的高k介電常數材料(通常如此)，則濕蝕刻無法有效移除這些桁條且乾電漿蝕刻這些閘極介電質桁條會損壞NFET 14之鈦氮化物及鉭氮化物層。這些缺點被視為不利於閾值電壓表現。
因此，期望提供具有改善的閾值電壓表現的取代金屬閘極的積體電路製造方法。期望提供具有改善的閾值電壓表現的取代金屬閘極的積體電路。再者，從後述之實施方式以及所附申請專利範圍搭配隨附圖式以及此先前技術，其他的期望特徵和特性將變得明顯。
提供具有改善的閾值電壓表現的取代金屬閘極的積體電路及其製造方法。根據例示實施例，一種積體電路製造方法包括：提供覆於半導體基板上之介電層，該介電層具有第一凹槽和第二凹槽；在該第一凹槽和該第二凹槽中形成閘極介電層；形成覆於該閘極介電層上之第一阻障層；在該第一凹槽和該第二凹槽內形成功函數材料；將該功函數材料和該第一阻障層凹陷至該第一凹槽和該第二凹槽中，該功函數材料和該第一阻障層相對於該半導體基板之平坦表面形成凹形表面；將該閘極介電層凹陷至該第一凹槽和該第二凹槽中；沉積導電閘極電極材料，使得該導電閘極電極材料填充該第一凹槽和該第二凹槽；以及將該導電閘極電極材料凹陷至該第一凹槽和該第二凹槽中。
根據另一例示實施例，一種積體電路製造方法包括：提供覆於半導體基板上之介電層，該介電層具有第一凹槽和第二凹槽；在該第一凹槽和該第二凹槽中形成閘極介電層；形成覆於該閘極介電層上之第一阻障金屬層；沉積覆於該第一阻障層上之第二阻障金屬層；形成圖案化遮罩，使得該圖案化遮罩部分地填充該第一凹槽以及覆於該第二阻障金屬層之第一部分上，以及其中，暴露該第二阻障金屬層之第二部分；移除該第二阻障金屬層之該第二部分；移除該圖案化遮罩；在該第一凹槽和該第二凹槽內形成功函數材料層；在該第一凹槽和該第二凹槽內形成遮罩材料；蝕刻該遮罩材料，使得該遮罩材料填充該第一凹槽之一部分和該第二凹槽之一部分；非等向性蝕刻該功函數材料層之一部分和該第一阻障金屬層之一部分；蝕刻該閘極介電層之一部分；從該第一凹槽和該第二凹槽移除該遮罩材料；沉積導電閘極材料覆於該第一凹槽和該第二凹槽中之該功函數材料層上；以及移除該第一凹槽和該第二凹槽內之該導電閘極材料之一部分。
根據例示實施例，一種具有金屬閘極結構之積體電路，包括：閘極介電層，係具有兩個相對構件以及接合構件，該接合構件覆於半導體基板上以及接合該兩個相對構件；第一阻障金屬層，係覆於該閘極介電層上；功函數材料層，係覆於該第一阻障金屬層上；導電閘極電極，係具有直線部分和剖面部分，其中，該直線部分覆於該功函數材料層上，其中，該剖面部分係垂直於該直線部 分以及覆於該閘極介電層、該第一阻障金屬層和該功函數材料層上，以及其中，該第一阻障金屬層和該功函數材料層具有凹形表面。
10、100‧‧‧積體電路
12‧‧‧P型通道場效電晶體、PFET
14‧‧‧N型通道場效電晶體、NFET
16‧‧‧介電材料層
18‧‧‧半導體材料
20、106‧‧‧第一凹槽
22、108‧‧‧第二凹槽
24、114‧‧‧閘極介電層
26‧‧‧第一阻障材料層或其組合
28‧‧‧第二阻障材料層或其組合
30、120‧‧‧遮罩材料
32‧‧‧光阻
34‧‧‧功函數材料
36‧‧‧閘極電極材料
40‧‧‧閘極介電質桁條
102、214‧‧‧半導體基板
104、222‧‧‧介電層
110‧‧‧PFET
112‧‧‧NFET
116‧‧‧雙層
118‧‧‧鈦氮化物層
122‧‧‧光阻層
124‧‧‧部分、未暴露部分
126‧‧‧鈦鋁層
128‧‧‧第二遮罩材料層
130‧‧‧暴露表面
131‧‧‧凹形、V形表面
132‧‧‧表面
133‧‧‧開口
134‧‧‧導電閘極電極
200‧‧‧鰭式場效電晶體
212‧‧‧鰭片
216‧‧‧閘極
218‧‧‧側壁
220‧‧‧側壁間隔件
以下將配合隨附圖式描述各種實施例，其中相同的元件符號代表相似的元件，以及其中：第1圖係先前技術中已知的單閘極FinFET之斜面圖；第2至5圖係先前技術中已知用於形成FinFET之步驟的剖面圖；第3至11圖係根據例示實施例之提供具有改善的閾值電壓表現的取代金屬閘極的積體電路及其製造方法的剖面圖。
下列實施方式在本質上僅為例示且無意限制各種實施例或其應用和用途。再者，無意受到前述先前技術或後述實施方式中所提之任何理論的限制。在此提出具有改善的閾值電壓表現的取代金屬閘極的積體電路及其製造方法的各種實施例。NFET和PFET之實施例分別採用TiN/TaN/TiAl和TiN/TaN/TiN/TiAl之新穎的功函數佈局設計。以現有的功函數組構所達成之傳統閾值電壓裝置讀出被認為不良，其中裝置導通時之高閾值電壓測量值達到0.8V。此處所可考慮之各種實施例增加RMG填充能力，維持後續金屬填充步驟之低長寬比並因而改善閘極電極金屬 凹陷製程穩定性。另外，NFET佈局係藉由導入凹角(chamfer angle)而最佳化，該凹角將閘極電極沉積中可能產生的孔洞最小化或消除。整體而言，此新穎的佈局包括得以驅動閾值電壓表現的改良，其具有典型裝置設計規格所需的可接受限度(亦即，0.3V)。
第6至10圖顯示一種具有改善的閾值電壓的取代金屬閘極的積體電路(IC)100的製造方法。製造IC的各種步驟眾所周知，故為求簡潔，許多傳統步驟在此將僅簡略提及或完全省略而不提供已知的製程細節。如第6圖所示之IC 100的一部分係在製造的早期階段。該方法包含提供覆於由半導體材料形成之半導體基板102上的介電層104。如在此所使用者，用語「覆於…上」意指直接置於其上或置於上方，使得中間材料至於其間。例如，介電層104可直接置於半導體基板102上或可覆於該半導體基板上，使得介電層或其他層置於該介電層104與該半導體基板102之間。在例示實施例中，半導體基板102為塊體矽基板，而半導體材料包含矽。例如，塊體矽基板能由相當純之矽、與鍺或碳混合之矽或與某些其他常用於製造積體電路之半導體材料混合之矽形成。或者，塊體矽基板102之半導體材料可為鍺、鎵砷化物等等。半導體材料不需要被摻雜，但其可被極輕濃度摻雜為N型或P型，而不影響在此所述之製程。或者，半導體基板102可被設在支撐基板上之絕緣體上矽(SOI)晶圓支撐。SOI晶圓包含矽氧化物層和覆於該矽氧化物層上之含矽材料層。半導體基板102 可為含矽材料層。在另一實施例中，半導體基板102是由半導體材料形成之FinFET的鰭片結構。介電層104是由絕緣材料(例如，矽氧化物)形成。
第一凹槽106和第二凹槽108係形成於介電層104中。PFET 110將隨後形成在第一凹槽106中，以及NFET 112將隨後形成在第二凹槽108中，如下詳述。雖然於第6圖中圖示兩個凹槽，但應瞭解在介電層104中可形成超過兩個凹槽。該等凹槽具有大約20奈米至大約500奈米之寬度。該等凹槽可使用例如N2/H2/CH4化學品以電漿蝕刻法進行蝕刻。雖然第6圖圖示在介電層104中形成兩個凹槽，但應了解到在此所述之取代金屬閘極可形成在兩個間隔件之間。就此而言，如第7圖所示，已知在先前技術中，虛擬閘極(dummy gate)係例如由多晶矽形成，接著在該虛擬閘極周圍形成側壁間隔件220。介電層222係沉積覆於虛擬閘極和側壁間隔件上。介電層的平坦化係藉由例如化學機械平坦化(CMP)而暴露虛擬閘極，然後移除虛擬閘極，留下側壁間隔件之間的兩個凹槽106和108。如在此使用者，用語「凹槽」是指開口或未佔用的空間。
在一個實施例中，閘極介電層114係已沉積之絕緣體，例如矽氧化物、矽氮化物、任何種類的高介電常數(高k)材料，其中介電常數是大於二氧化矽之介電常數(3.9)，例如鉿氧化物等等。已沉積之絕緣體可藉由例如化學氣相沉積(CVD)、原子層沉積(ALD)、低壓化學氣相沉積(LPCVD)或電漿增強化學氣相沉積(PECVD)進行沉積。在 一個實施例中，閘極介電層114係具有大約10埃(Å)至大約20埃之厚度範圍的鉿氧化物，但該閘極介電層114之實際厚度可依據所實施之積體電路中所應用的FinFET來決定。
該方法繼續，形成PFET 110之金屬閘極和NFET 112之金屬閘極。就此而言，阻障金屬係形成覆於閘極介電層114上。適合用作為阻障金屬之金屬包含那些避免閘極電極(將在後面討論)之金屬離子遷移進入閘極介電層114和介電層104中者。此外，係針對黏附閘極電極(後面討論)和閘極介電層114的能力來選擇金屬。在實施例中，鈦氮化物層係形成在凹槽內以及覆於閘極介電層114上。鈦氮化物層可藉由例如物理氣相沉積(PVD)進行沉積。鈦氮化物層之厚度係例如在大約5埃至大約15埃的範圍內。鉭氮化物係在暴露凹槽中沉積覆於鈦氮化物上以形成鉭氮化物層。鉭氮化物層係藉由例如PVD沉積。在實施例中，鉭氮化物層具有例如在大約3奈米至大約5奈米的範圍內的厚度。覆於閘極介電層114上之鈦氮化物層以及覆於鈦氮化物層上之鉭氮化物層係在圖式中標示為雙層(bilayer)116。
另一鈦氮化物層118係如上所述藉由沉積鈦氮化物而形成在鉭氮化物層上。鈦氮化物層能沉積至例如在大約3奈米至大約5奈米的範圍內的厚度。遮罩材料120係沉積、填充第一凹槽106和第二凹槽108，而光阻層122係形成覆於該遮罩材料120上。遮罩材料120可以是 對鉭氮化物具有蝕刻選擇性的任何適合材料，以下將詳細討論。適合的遮罩材料範例包含(但不限於)可從紐澤西的莫里斯敦的Honeywell International股份有限公司取得的DUOTM 248。遮罩材料120係藉由旋轉塗佈、滾輪塗佈、噴霧等等形成覆於鈦氮化物層118上。遮罩材料120係沉積至例如在大約130奈米至大約180奈米的範圍內的厚度。
參考第8圖，光阻層122被圖案化，遮罩材料120被蝕刻成在PFET 110之第一凹槽106中覆蓋鈦氮化物層118之一部分124，然後移除該光阻層122。若遮罩材料是Honeywell的DUO 248，則遮罩材料120可使用例如N2/H2/CH4化學品以電漿蝕刻法進行蝕刻。鈦氮化物層118之暴露部分係從第一和第二凹槽移除，留下該第一凹槽106中的未暴露部分124。鈦氮化物藉由例如SPN(硫酸和過氧化物)之化學品而被選擇性移除，其中鈦氮化物對鉭氮化物之選擇性超過100奈米。然後，移除遮罩材料120之剩餘部分。
接著，如第9圖所示，沉積功函數材料(鈦鋁)以形成覆於鈦氮化物層118之部分124以及鉭氮化物與鈦氮化物雙層116上的鈦鋁層126。鈦鋁將裝置閾值電壓表現有效地穩定在大約0.3V的中心目標。在先進的半導體製造中，根據特定的佈局設計來可靠控制閾值電壓參數的能力很重要，用以保證有效的裝置導通表現。在實施例中，鈦鋁層能藉由例如ALD沉積並具有在大約4奈米至大約8奈米的範圍內的厚度。在沉積鈦鋁層之後，第二遮罩材料 層128係在凹槽106和108內共形地沉積覆於鈦鋁層126上。第二遮罩材料層128係沉積至大約130奈米至大約180奈米的範圍內的厚度。第二遮罩材料層可以是與遮罩材料120相同的材料，並且可以使用與用來蝕刻遮罩材料120相同的化學品來進行蝕刻。
該方法繼續，參考第10圖，第二遮罩材料128被蝕刻，直到凹入凹槽106和108中。在實施例中，第二遮罩材料128被蝕刻成該第二遮罩材料128之暴露表面130比鈦氮化物層118中最接近凹槽106之開口133的表面132還靠近凹槽106之開口133。鈦鋁層126之一部分、暴露之阻障金屬鈦氮化物與鉭氮化物116以及閘極介電層114係從凹槽106和108移除。阻障金屬材料和閘極介電層(例如鉿氧化物)能藉由乾電漿蝕刻法(例如使用BCl3/Cl2的反應性離子蝕刻(RIE))移除。第二遮罩材料128保護鈦鋁層126和阻障金屬鈦氮化物與鉭氮化物免於受到乾電漿蝕刻。由於蝕刻是非等向性的，所以金屬會相對於半導體基板102之平坦表面101形成靠近凹槽之開口133的傾斜形或「V」形表面131。
參考第11圖，在蝕刻各種金屬層和閘極介電質之後，移除第二遮罩材料128之剩餘部分。執行鈦氮化物沉積以全面性地形成鈦氮化物層(未圖示)。在實施例中，鉭氮化物具有在大約2奈米至大約4奈米的範圍內的厚度，例如2.5奈米。在沉積鈦氮化物之後，在PFET電晶體110之凹槽106以及NFET電晶體112之凹槽108內沉積 導電閘極電極層134以填充該等凹槽。導電閘極電極134可由任何適合導電材料形成，例如鋁或鎢。由於阻障金屬材料和功函數材料層之凹形表面131，導電閘極電極134係以「由下往上(bottum-up)」減少或消除其中之孔洞的方式沉積在凹槽內。執行CMP製程以移除覆於介電層104上的覆蓋層(overburden)。在實施例中，導電閘極電極134之一部分係在凹槽內被移除，以在該凹槽內提供空間供絕緣蓋層(未圖示)覆蓋該導電閘極電極134。若導電閘極電極為鎢，則此鎢能藉由使用氫氟酸化學的反應性離子蝕刻(RIE)而被蝕刻。
之後，以進一步的處理步驟繼續積體電路的製造，能執行這些步驟完成積體電路，如技術領域中所熟知者。傳統上，進一步的步驟包含，例如，在對齊取代金屬閘極(藉由移除介電層以及植入導電率決定性離子至半導體基板中而形成者)的半導體基板中形成源極和汲極區域、形成接觸件(藉由在絕緣層之上沉積光阻材料層、微影圖案化、蝕刻形成接觸孔洞、以及在該孔洞中沉積導電材料而形成接觸件所形成者)、以及在該絕緣層上方對整個裝置形成一層或多層圖案化導電層等等。在此所揭露之主題並非意圖排除任何後續形成及測試本技術領域中熟知之完成電路的處理步驟。此外，就上述之任何製程步驟而言，能在沉積一層之後，採用一道或多道加熱處理及/或退火程序，如本技術領域中廣為人知者。
因此，已描述具有改善的閾值電壓表現的 取代金屬閘極的積體電路的製造方法以及具有改善的閾值電壓表現的取代金屬閘極的積體電路。取代金屬閘極係形成有金屬層，該金屬層具有允許以最少孔洞或毫無孔洞的情形形成導電閘極電極的凹形或「V」形表面。因此，得以避免回蝕閘極電極以移除孔洞，並且得以最小化閘極電極變化。此外，因為在導電閘極電極中形成的孔洞都被最小化或消除，所以可以不必進行不想要的導電閘極電極蝕刻，而可讓更多的導電閘極電極材料停留在凹槽中。這可大幅改善接觸電阻。再者，在取代金屬閘極中使用鈦鋁功函數材料以穩定閾值電壓。閘極介電質桁條也被移除，因為凹槽中的金屬層受到第二遮罩材料層保護，該第二遮罩材料層係在功函數材料沉積之後以及閘極電極材料沉積之前沉積。就此而言，提供一種新穎佈局，其包括得以驅動典型裝置設計規格所需的閾值電壓表現的改良。
雖然已在本發明之前述實施方式中提出至少一個例示實施例，但應了解仍存在大量變體。也應了解到，例示實施例係僅為範例，係無意以任何方式限制本發明之範圍、應用性或組構。相反地，前述實施方式將提供本技術領域中具有通常知識者用於實施本發明之例示實施例的方便藍圖。應了解到，在不背離所附申請專利範圍中所提出之本發明範圍的情形下，可對例示實施例中所述之功能及元件配置做出各種改變。
102‧‧‧半導體基板
104‧‧‧介電層
114‧‧‧閘極介電層
116‧‧‧雙層
118‧‧‧鈦氮化物層
126‧‧‧鈦鋁層
134‧‧‧導電閘極電極

Claims (19)

  1. 一種製造積體電路之方法，該方法包括：提供覆於半導體基板上之介電層，該介電層具有第一凹槽和第二凹槽；在該第一凹槽和該第二凹槽中形成閘極介電層；形成覆於該閘極介電層上之第一阻障層；在該第一凹槽和該第二凹槽內形成功函數材料層；將該功函數材料層和該第一阻障層凹陷至該第一凹槽和該第二凹槽中，其中，該功函數材料層和該第一阻障層相對於該半導體基板之平坦表面形成斜形表面；將該閘極介電層凹陷至該第一凹槽和該第二凹槽中；沉積導電閘極電極材料，使得該導電閘極電極材料填充該第一凹槽和該第二凹槽；以及將該導電閘極電極材料凹陷至該第一凹槽和該第二凹槽中。
  2. 如申請專利範圍第1項所述之方法，更包括在形成該第一阻障層之後形成第二阻障層，其中，該第二阻障層在該第一凹槽中覆於該第一阻障層之一部分上，但該第二凹槽中沒有該第二阻障層。
  3. 如申請專利範圍第2項所述之方法，其中，形成該第二阻障層包括：形成該第二阻障層覆於該第一阻障層上；在該第二阻障層上形成遮罩； 在該遮罩上形成光阻；圖案化該光阻以形成圖案化光阻；使用該圖案化光阻作為蝕刻遮罩而蝕刻該遮罩；從該第二凹槽和該第一凹槽之一部分移除該第二阻障層。
  4. 如申請專利範圍第3項所述之方法，其中，形成該第二阻障層包括形成氮化鈦層。
  5. 如申請專利範圍第1項所述之方法，其中，提供該介電層包括提供氧化鉿層，以及其中，凹陷該閘極介電層包括使用乾電漿蝕刻法蝕刻閘極介電層桁條。
  6. 如申請專利範圍第1項所述之方法，其中，沉積該第一阻障層包括沉積氮化鈦層。
  7. 如申請專利範圍第6項所述之方法，其中，沉積該第一阻障層包括沉積覆於該氮化鈦層上之氮化鉭層。
  8. 如申請專利範圍第1項所述之方法，其中，形成該功函數材料層包括形成鈦鋁層。
  9. 如申請專利範圍第1項所述之方法，其中，凹陷該功函數材料層和該第一阻障層包括：在形成該功函數材料層之後，沉積覆於該功函數材料層上之遮罩材料；在該遮罩材料上形成圖案化光阻；使用該圖案化光阻作為蝕刻遮罩而蝕刻該遮罩材料，其中，該遮罩材料保留在該第一凹槽和該第二凹槽中； 使用該遮罩材料、該第一阻障層和該閘極介電層作為蝕刻遮罩而移除該功函數材料層之一部分；使用該遮罩材料、該功函數材料層和該閘極介電層作為蝕刻遮罩而移除該第一阻障層之一部分。
  10. 如申請專利範圍第1項所述之方法，其中，沉積該導電閘極電極材料包括沉積鎢。
  11. 如申請專利範圍第1項所述之方法，其中，提供覆於半導體基板上之該介電層包括提供覆於後續形成之FinFET裝置之鰭片結構上的該介電層。
  12. 如申請專利範圍第1項所述之方法，其中，該閘極介電層係與側壁間隔件實際接觸。
  13. 一種製造積體電路之方法，該方法包括：提供覆於半導體基板上之介電層，該介電層具有第一凹槽和第二凹槽；在該第一凹槽和該第二凹槽中形成閘極介電層；形成覆於該閘極介電層上之第一阻障金屬層；沉積覆於該第一阻障層上之第二阻障金屬層；形成圖案化遮罩，使得該圖案化遮罩部分地填充該第一凹槽以及覆於該第二阻障金屬層之第一部分上，以及其中，暴露該第二阻障金屬層之第二部分；移除該第二阻障金屬層之該第二部分；移除該圖案化遮罩；在該第一凹槽和該第二凹槽內形成功函數材料層；在該第一凹槽和該第二凹槽內形成遮罩材料； 蝕刻該遮罩材料，使得該遮罩材料填充該第一凹槽之一部分和該第二凹槽之一部分；非等向性蝕刻該功函數材料層之一部分和該第一阻障金屬層之一部分；蝕刻該閘極介電層之一部分；從該第一凹槽和該第二凹槽移除該遮罩材料；沉積導電閘極材料覆於該第一凹槽和該第二凹槽中之該功函數材料層上；以及移除該第一凹槽和該第二凹槽內之該導電閘極材料之一部分。
  14. 如申請專利範圍第13項所述之方法，其中，蝕刻該閘極介電層之一部分包括使用乾電漿製程蝕刻該閘極介電層之一部分。
  15. 如申請專利範圍第13項所述之方法，其中，非等向性蝕刻該功函數材料層之一部分和該第一阻障金屬層之一部分包括形成該第一阻障金屬層和該功函數材料層之斜形表面。
  16. 如申請專利範圍第13項所述之方法，其中，形成該閘極介電層包括形成氧化鉿層。
  17. 如申請專利範圍第13項所述之方法，其中，形成該第一阻障金屬層包括沉積氮化鈦層以及沉積氮化鉭層覆於該氮化鈦層上。
  18. 如申請專利範圍第13項所述之方法，其中，形成該功函數材料層包括形成鈦鋁層。
  19. 如申請專利範圍第13項所述之方法，其中，沉積該第二阻障金屬層包括沉積氮化鈦層。
TW103104527A 2013-07-17 2014-02-12 具有改善的閾値電壓表現的取代金屬閘極的積體電路及其製造方法 TWI524397B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/943,944 US9147680B2 (en) 2013-07-17 2013-07-17 Integrated circuits having replacement metal gates with improved threshold voltage performance and methods for fabricating the same

Publications (2)

Publication Number Publication Date
TW201505081A TW201505081A (zh) 2015-02-01
TWI524397B true TWI524397B (zh) 2016-03-01

Family

ID=52319573

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103104527A TWI524397B (zh) 2013-07-17 2014-02-12 具有改善的閾値電壓表現的取代金屬閘極的積體電路及其製造方法

Country Status (3)

Country Link
US (1) US9147680B2 (zh)
CN (1) CN104299897B (zh)
TW (1) TWI524397B (zh)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI653762B (zh) * 2014-10-08 2019-03-11 聯華電子股份有限公司 具有金屬閘極之半導體元件之製作方法
TWI635535B (zh) * 2015-03-10 2018-09-11 聯華電子股份有限公司 具有不同臨界電壓的金屬閘極的半導體製程及半導體結構
KR102271239B1 (ko) * 2015-03-23 2021-06-29 삼성전자주식회사 반도체 장치 및 이의 제조 방법
KR102342847B1 (ko) * 2015-04-17 2021-12-23 삼성전자주식회사 반도체 소자 및 그 제조 방법
US9818841B2 (en) 2015-05-15 2017-11-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure with unleveled gate structure and method for forming the same
US9583485B2 (en) 2015-05-15 2017-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field effect transistor (FinFET) device structure with uneven gate structure and method for forming the same
CN106531776B (zh) * 2015-09-11 2021-06-29 联华电子股份有限公司 半导体结构
US10008574B2 (en) * 2015-11-30 2018-06-26 Taiwan Semiconductor Manufacturing Co., Ltd. Gate structure and method of fabricating the same
KR102474431B1 (ko) 2015-12-08 2022-12-06 삼성전자주식회사 반도체 소자의 제조방법
US9437714B1 (en) 2015-12-09 2016-09-06 International Business Machines Corporation Selective gate contact fill metallization
US9865703B2 (en) * 2015-12-31 2018-01-09 International Business Machines Corporation High-K layer chamfering to prevent oxygen ingress in replacement metal gate (RMG) process
US10283605B2 (en) * 2016-01-29 2019-05-07 Taiwan Semiconductor Manufacturing Co., Ltd Self-aligned metal gate etch back process and device
US20170345912A1 (en) * 2016-05-26 2017-11-30 Globalfoundries Inc. Methods of recessing a gate structure using oxidizing treatments during a recessing etch process
US10043886B2 (en) 2016-08-03 2018-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gate formation through etch back process
US10269917B2 (en) * 2016-10-19 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a FinFET with work function tuning layers having stair-step increment sidewalls
US20180190546A1 (en) * 2016-12-29 2018-07-05 Globalfoundries Inc. Method for forming replacement metal gate and related device
US10319826B2 (en) * 2017-04-12 2019-06-11 International Business Machines Corporation Replacement metal gate stack with oxygen and nitrogen scavenging layers
US10056303B1 (en) * 2017-04-21 2018-08-21 Globalfoundries Inc. Integration scheme for gate height control and void free RMG fill
CN107464758A (zh) * 2017-09-07 2017-12-12 上海华力微电子有限公司 一种半导体器件的形成方法
US20190086809A1 (en) * 2017-09-21 2019-03-21 United Microelectronics Corp. Method for fabricating semiconductor structure involving cleaning mask material
US10636890B2 (en) * 2018-05-08 2020-04-28 Globalfoundries Inc. Chamfered replacement gate structures
KR102560369B1 (ko) * 2018-05-18 2023-07-28 삼성전자주식회사 반도체 소자
KR102593708B1 (ko) * 2018-08-14 2023-10-26 삼성전자주식회사 반도체 장치 및 반도체 장치의 제조 방법
US11069531B2 (en) 2018-10-31 2021-07-20 Taiwan Semiconductor Manufacturing Company, Ltd. Replacement gate methods that include treating spacers to widen gate
US10833169B1 (en) * 2019-04-22 2020-11-10 Globalfoundries Inc. Metal gate for a field effect transistor and method
DE102020107241A1 (de) * 2019-10-29 2021-04-29 Taiwan Semiconductor Manufacturing Co., Ltd. Finnen-feldeffekttransistor-bauelement und verfahren zu dessen herstellung
US11690216B2 (en) * 2019-12-13 2023-06-27 Micron Technology, Inc. Structure to reduce bending in semiconductor devices
CN111627993B (zh) * 2020-06-05 2023-01-06 福建省晋华集成电路有限公司 栅极结构与其制作方法
CN111627992B (zh) * 2020-06-05 2023-04-04 福建省晋华集成电路有限公司 栅极结构与其制作方法
CN117673032A (zh) * 2022-09-01 2024-03-08 长鑫存储技术有限公司 半导体结构及其制备方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7029959B1 (en) * 2003-05-06 2006-04-18 Advanced Micro Devices, Inc. Source and drain protection and stringer-free gate formation in semiconductor devices
DE102004031385B4 (de) * 2004-06-29 2010-12-09 Qimonda Ag Verfahren zur Herstellung von Stegfeldeffekttransistoren in einer DRAM-Speicherzellenanordnung, Feldeffekttransistoren mit gekrümmtem Kanal und DRAM-Speicherzellenanordnung
US7611943B2 (en) * 2004-10-20 2009-11-03 Texas Instruments Incorporated Transistors, integrated circuits, systems, and processes of manufacture with improved work function modulation
KR100793011B1 (ko) * 2007-02-16 2008-01-08 에스케이에너지 주식회사 리튬이차전지의 제조방법
US8268085B2 (en) * 2009-03-20 2012-09-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming metal gate transistors
US8357579B2 (en) * 2010-11-30 2013-01-22 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuits
CN102683397B (zh) * 2011-03-17 2016-04-06 联华电子股份有限公司 金属栅极结构及其制作方法
CN102760758A (zh) * 2011-04-26 2012-10-31 联华电子股份有限公司 金属栅极结构
US8461049B2 (en) * 2011-10-11 2013-06-11 United Microelectronics Corp. Method for fabricating semiconductor device

Also Published As

Publication number Publication date
CN104299897A (zh) 2015-01-21
US20150021694A1 (en) 2015-01-22
TW201505081A (zh) 2015-02-01
US9147680B2 (en) 2015-09-29
CN104299897B (zh) 2017-04-05

Similar Documents

Publication Publication Date Title
TWI524397B (zh) 具有改善的閾値電壓表現的取代金屬閘極的積體電路及其製造方法
TWI701830B (zh) 半導體裝置及其形成方法
TWI618242B (zh) 半導體裝置及其形成方法
US8952451B2 (en) Semiconductor device having metal gate and manufacturing method thereof
US9391075B2 (en) Integrated circuit and method for fabricating the same having a replacement gate structure
TWI712084B (zh) 半導體裝置以及其製作方法
US8420473B2 (en) Replacement gate devices with barrier metal for simultaneous processing
CN109727854B (zh) 半导体装置及其形成方法
TWI573274B (zh) 半導體結構及其製造方法
US8759208B2 (en) Method for manufacturing contact holes in CMOS device using gate-last process
US20190035786A1 (en) Metal gate structure and methods thereof
CN107516668B (zh) 半导体装置及其制造方法
TW201628090A (zh) 半導體元件及其製作方法
US20060157750A1 (en) Semiconductor device having etch-resistant L-shaped spacer and fabrication method thereof
KR20130069289A (ko) 복수의 임계 전압을 가진 ｆｉｎｆｅｔ들
TWI714583B (zh) 半導體裝置及其形成方法
KR20170065271A (ko) 반도체 소자 및 그 제조 방법
US20150024584A1 (en) Methods for forming integrated circuits with reduced replacement metal gate height variability
TWI667698B (zh) 半導體元件及其形成方法
TWI721515B (zh) 用於中電壓裝置的凹槽閘極
US20140099760A1 (en) Method for fabricating semiconductor device
JP2010098157A (ja) 半導体装置の製造方法
TWI708282B (zh) 完全矽化閘控裝置及其形成方法
JP2005259945A (ja) 半導体装置の製造方法及び半導体装置
TWI802217B (zh) 半導體裝置和製造方法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees