TWI518755B - 積體電路結構及其製作方法 - Google Patents

積體電路結構及其製作方法 Download PDF

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TWI518755B
TWI518755B TW102126304A TW102126304A TWI518755B TW I518755 B TWI518755 B TW I518755B TW 102126304 A TW102126304 A TW 102126304A TW 102126304 A TW102126304 A TW 102126304A TW I518755 B TWI518755 B TW I518755B
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Taiwan
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dielectric layer
contact
width
gate electrode
gate
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TW102126304A
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TW201435997A (zh
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劉繼文
王昭雄
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台灣積體電路製造股份有限公司
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Description

積體電路結構及其製作方法
本發明是有關於一種積體電路結構，特別是有關於一種鰭型場效電晶體。
隨著積體電路(integrated circuit structure，IC)的尺寸不斷縮小，且對於積體電路的速度需求不斷提升，電晶體必須在越來越小的尺寸中具有更高的驅動電流。因此，發展出鰭型場效電晶體(fin field-effect transistors，FinFET)。在典型的鰭型場效電晶體中，部份的基材被蝕刻以形成垂直式鰭型結構。垂直式鰭型結構係沿著側向方向形成源極/汲極，並於鰭部內形成通道區。閘極沿著垂直方向形成在鰭部的通道區上，以形成鰭型場效電晶體。接著，形成內層介電(inter-layer dielectric，ILD)層與複數個內連線層(interconnect layers)於鰭型場效電晶體上。內層介電層包含複數個閘極接觸(gate contacts)，前述閘極接觸藉由前述內連線層以電性連結閘極至積體電路內其他複數個主動元件。
一般而言，閘極接觸的寬度會比閘極窄，因此閘極接觸面積也相對較小。閘極接觸面積小會造成閘極與閘極接觸之間的高接觸阻抗(contact resistance)。遺憾地，由於設計法則的限制，不容易增加或調整閘極接觸的寬度。
因此，本發明之一態樣就是在提供一種積體電路結構及其製造方法，其中接觸在閘極電極的上具有第一寬度，以及接觸在閘極電極中具有第二寬度，且第一寬度小於第二寬度，以降低減少閘極與接觸層之間的接觸阻抗。
根據本發明之上述態樣，提出一種積體電路結構，包含基材、閘極介電層、閘極電極以及接觸。基材之一部分向上延伸以形成鰭部。閘極介電層係在鰭部之頂表面與複數個側壁之至少複數個部分上。閘極電極係在閘極介電層上。接觸係在閘極電極上並延伸至閘極電極中，其中接觸在閘極電極上具有第一寬度，接觸在閘極電極中具有第二寬度，且第一寬度小於第二寬度。
依據本發明之一實施例，上述之第二寬度與鰭部之第三寬度之比值係介於1.2至2.5之間。
依據本發明之另一實施例，上述之積體電路結構更包含接觸阻障層於接觸與閘極電極之間，其中接觸阻障層更覆蓋接觸層之複數個側壁上。
依據本發明之又一實施例，上述之接觸阻障層包含氮化鈦或氮化鉭。
依據本發明之再一實施例，上述之接觸阻障層包含氮化鈦鋁、氮化鈦鋁鎢、氮化鉭鋁或氮化鉭鋁鎢。
依據本發明之再一實施例，上述之接觸層包含鎢、銅或鋁。
依據本發明之再一實施例，上述之閘極介電層包含矽氧化物、矽氮化物或一高介電常數(k)介電材料。
根據本發明之上述態樣，提出一種積體電路結構，包含基材、半導體鰭部、閘極介電層、閘極電極、內層介電層、接觸以及接觸阻障層。半導體鰭部係在基材上並連接至基材。閘極介電層係在鰭部之頂表面以及複數個側壁上。閘極電極在閘極介電層上。內層介電(inter-later dielectric；ILD)層係在閘極介電層上。接觸係自內層介電層之頂表面延伸至閘極電極，其中接觸在內層介電層具有第一部份，接觸在閘極電極中具有第二部份，且其中第一部份與第二部份分別具有第一寬度與第二寬度，而第二寬度係大於第一寬度。接觸阻障層覆蓋接觸之底表面與複數個側壁。
依據本發明之一實施例，上述之第二寬度與鰭部之第三寬度之比值係介於1.2至2.5之間。
依據本發明之另一實施例，上述之接觸阻障層包含氮化鈦或氮化鉭。
依據本發明之又一實施例，上述之接觸阻障層包含氮化鈦鋁、氮化鈦鋁鎢、氮化鉭鋁或氮化鉭鋁鎢。
依據本發明之再一實施例，上述之積體電路結構更 包含界面層，其中界面層係於閘極介電層與鰭部之間。
依據本發明之再一實施例，上述之積體電路結構更包含介電層於閘極介電層與鰭部之間，其中介電層包含第一部分與第二部分，且第一部分與第二部分係設於鰭部之複數個相對側邊。
依據本發明之再一實施例，上述之閘極電極包含一信號金屬與一功函數金屬。
根據本發明之上述態樣，提出一種形成積體電路結構的方法，包含蝕刻基材以形成鰭部。接著，形成閘極介電層在鰭部之頂表面與複數個側壁之至少一部分上。然後，形成閘極電極在閘極介電層上。接著，形成內層介電層在閘極電極上。隨後，圖案化內層介電層，以於內層介電層中形成開口且曝露出閘極電極，其中開口具有第一寬度。隨之，對閘極電極之一部分進行等向性蝕刻步驟，使開口延伸至閘極電極，其中開口在閘極電極中之一部分具有第二寬度，且其中第二寬度係大於第一寬度。之後，形成接觸阻障層覆蓋開口之底表面與複數個側壁。隨即，將金屬材料填入開口，以形成接觸。
依據本發明之一實施例，上述之閘極電極之部分的等向性蝕刻步驟包含利用溼式蝕刻方法結合無偏差乾式蝕刻方法進行。
依據本發明之另一實施例，上述之形成積體電路結構的方法，更包含對積體電路結構進行退火步驟。
依據本發明之又一實施例，上述之該積體電路結構 之該退火步驟係於250℃至450℃進行。
依據本發明之再一實施例，上述之形成積體電路結構的方法，更包含形成界面層於鰭部與閘極電極之間。
依據本發明之再一實施例，上述之形成積體電路結構的方法，在形成閘極介電層之前，更包含形成介電層在基材上。之後，使介電層內縮，以暴露出鰭部之至少一部分。
100‧‧‧積體電路結構
102‧‧‧基材
104‧‧‧緩衝層
106‧‧‧罩幕層
108‧‧‧光阻層
110‧‧‧鰭部
112‧‧‧介電層
114‧‧‧閘極介電層
116‧‧‧閘極電極
118‧‧‧閘極間隙壁
120‧‧‧第一內層介電層
122‧‧‧第二內層介電層
124‧‧‧開口
126‧‧‧接觸阻障層
128‧‧‧接觸
W1‧‧‧第一寬度
W2‧‧‧第二寬度
W3‧‧‧第三寬度
為更完整了解本發明實施例以及其優點，參照現在下述之描述並結合所附圖式，其中：
第1圖至第9圖係繪示依照本發明之不同實施例之積體電路結構在製程中間階段的剖面示意圖。
實施例之製造與使用將於後述詳細討論。然而，應可理解的是，下列揭露內容提供許多可應用的概念，以各種特定描述具體實現。所討論之特定實施例僅以特定方式說明揭露客體的製造與使用，並非用以限制於不同的實施例的範圍。
積體電路結構之實施例將以相當於特定描述被說明，即為鰭型場效電晶體。其他電晶體〔(例如隧道場效電晶體(tunnel field-effect transistor)或奈米線場效電晶體(nano-wire field-effect transistor)〕以及相似結構係在本揭 露內容之範圍內。鰭型場效電晶體可被包含於微處理器、記憶元件及/或其他的積體電路。
第1圖至第9圖係繪示依照本發明之不同實施例之積體電路結構在製程中間階段的剖面示意圖，其中剖面示意圖係鰭部之剖面，而非汲極區或源極區。在本發明揭露內容中，半導體結構(integrated circuits，IC)100係指鰭型場效電晶體100。鰭型場效電晶體100係指任何具有鰭部與多個閘極的電晶體。鰭型場效電晶體100包含在垂直式鰭部上的閘極。閘極之頂部分被等向性蝕刻，以於閘極接觸與閘極之間形成延伸接觸面積，但不增加閘極接觸之寬度。藉由這種方式，可減少閘極與閘極接觸之間的接觸阻抗可被但不違反設計法則。在一實施例中，延伸接觸之寬度與鰭部之寬度的比值係介於1.2至2.5之間。
第1圖係繪示鰭型場效電晶體100之剖面示意圖，其中包含基材102。基材102可為塊狀基材或絕緣體上半導體(semiconductor-on-insulator，SOI)基材。基材102可為矽或矽化鍺所形成，亦可使用其他半導體材料，包含III族、IV族以及V族元素。
緩衝層104與罩幕層106可形成於半導體基材102上。緩衝層104可利用例如熱氧化製程而形成之氧化矽。緩衝層104可作為黏著層並可減少半導體基材102與罩幕層106之間的應變。在蝕刻罩幕層106，緩衝層104更可作為蝕刻終止層。罩幕層106為利用例如低壓化學氣相沉積(low-pressure chemical vapor deposition，LPCVD)、熱氮化 矽、電漿輔助化學氣象沉積(plasma enhanced chemical vapor deposition，PECVD)或電漿離子氮化而形成之氮化矽。在後續的微影製程中，罩幕層106係作為硬罩幕。在罩幕層106上形成並圖案化光阻層108，以暴露出下方部分的罩幕層106。
請參閱第2圖，透過光阻層複數個108之開口蝕刻罩幕層106與緩衝層104。然後，蝕刻半導體基材102，以形成鰭部110。雖然第2圖僅繪示一鰭部，然而在其他實施例中，可於相同製程步驟中形成多個鰭部(例如：形成一個多鰭部的鰭型場效電晶體，或同時形成多個鰭型場效電晶體)。接著，移除光阻層108。另外，可藉由於基材102上沉積氧化層(例如氧化矽)、圖案化氧化層、及磊晶成長，而形成鰭部。
在第3圖中，在基材102上沉積介電層112。介電層112可由氧化矽所形成，亦可使用其他介電物質，例如氮化矽(SiN)，碳化矽(SiC)或者其他的類似物。介電層112可以毯覆式沉積於半導體基材102上。在一實施例中，鰭型場效電晶體包含多個鰭部，而介電層112可作為絕緣層以隔離個別的鰭部。於介電層112上可進行化學機械研磨(CMP)製程，以暴露出鰭部110之頂部分，使介電層112之頂表面與鰭部110之頂表面具有相同水平。
第4圖係繪示，利用例如蝕刻步驟使介電層112內縮。內縮步驟的結果，使鰭部110之一部分被暴露出來並延伸至介電層112之頂表面上。當鰭型場效電晶體100完 全形成時，鰭部110延伸在介電層112頂表面上的部分，可作為通道區。
第5圖係繪示在鰭型110上形成閘極介電層114與閘極電極116。閘極電極116可包含功函數金屬(work function metal)與信號金屬(signal metal)。為易於說明，並未個別繪示出閘極電極116的複數層。閘極介電層包含矽氧化物、矽氮化物或具有介電常數(k)值高於7.0的介電材料。高介電常數介電材料可包含金屬氧化物。可作為高介電常數介電材料之金屬氧化物可包含鋰(Li)、鈹(Be)、鎂(Mg)、鈣(Ca)、鍶(Sr)、鈧(Sc)、釔(Y)、鋯(Zr)、鉿(Hf)、鋁(Al)、鑭(La)、鈰(Ce)、鐠(Pr)、釹(Nd)、釤(Sm)、銪(Eu)、釓(Gd)、鋱(Tb)、鏑(Dy)、鈥(Ho)、鉺(Er)、銩(Tm)、鐿(Yb)、鎦(Lu)之氧化物及其任意組合。在一些實施例中，閘極介電層114之厚度係5埃(Å)至30Å。閘極介電層114可藉由熱氧化製程形成於鰭部110的頂表面與複數個側壁上，或藉由化學氣相沉積(chemical vapor deposition，CVD)製程、原子層沉積(atomic layer deposition，ALD)製程毯覆式沉積於鰭部110上。然後功函數金屬，如鋁、鈦鋁、鎢、氮化鈦、氮化鉭、碳化鉭等可形成於閘極介電層上。當鰭型場效電晶體100完成後，當供給適當的偏電壓，功函數金屬在通道區(例如：鰭部)引發電荷。一般而言，功函數金屬的接觸阻抗可能相對較高。因此，較低阻抗的信號金屬可形成於功函數金屬上，以減少整個裝置的接觸阻抗。信號金屬可由鋁、鋁銅等所形成，亦可使用其他金屬材質。閘極 電極116(例如：高功函數金屬與信號金屬)可藉由化學氣相沉積(CVD)、電鍍(plating)、原子層沉積(ALD)或其他適合的技術形成。
此外，界面層(圖未繪示)可形成於閘極介電層114之下方，且在鰭部110與介電層112上。界面層可包含氧化矽並且可作為閘極介電層114與鰭部110之間的黏著層/緩衝層。
第6圖係繪示形成閘極間隙壁118與第一內層介電層120。閘極間隙壁118可由氧化矽、氮化矽及類似物所形成。接著，鰭型場效電晶體100的其餘部分，包含源極/汲極和源極/汲極矽化物(圖未繪示)沿著側向方向形成。然後，第一內層介電層120可由氧化矽、磷矽酸鹽玻璃(phosphosilicate glass，PSG)、硼磷矽玻璃(borophosphosilicate glass，BPSG)等所形成。第一內層介電層120可毯覆式沉積於介電層112與閘極間隙壁118上。上述元件之製程為本技術領域之通常知識，在此不贅。
如第7圖所示，第二內層介電層122係形成在第一內層介電層120、閘極間隙壁118以及包含閘極電極116的鰭型場效電晶體100上。第二內層介電層122利用與第一內層介電層120實質上相同材料與相同技術所形成。另外，第二內層介電層122可利用與第一內層介電層120不同的材料所形成。舉例而言，第一內層介電層120可利用PSG所形成，而第二內層介電層122可利用氧化矽所形成。將第二內層介電層122圖案化，以形成開口124而暴露出下 層的閘極電極116。開口124可利用例如光微影成像(photolithographic)與蝕刻技術所形成。
第8圖係繪示經由附加的蝕刻延伸開口124。閘極電極116頂表面被等向性蝕刻以延伸開口124。閘極電極116可藉由溼式蝕刻方法結合無偏差乾式蝕刻方法進行。舉例而言，閘極電極116可利用稀釋氟氫酸(diluted hydrofluoric acid，DHF)進行溼式蝕刻，且結合利用含有氯的氣體進行無偏差乾式蝕刻。舉例而言，可於電源功率為550瓦(W)至850瓦，壓力為10毫托(mTorr)至200毫托，且利用氯氣(Cl2)、溴化氫(HBr)以及氦氣(He)作為蝕刻氣體下進行乾式蝕刻。值得注意的是，開口124位於閘極電極116的部份係大於開口124位於第二內層介電層122的部份。
第9圖係繪示於開口124內形成接觸阻障層126與接觸128。接觸阻障層126可由氮化鈦、氮化鉭等所形成。在一些實施例中，接觸阻障層126之厚度係3埃(Å)至20Å。接觸阻障層126包覆開口124之底表面與複數個側壁。然後開口124被填充以形成接觸128。接觸128可由鎢、鋁或銅以及其他金屬材質所形成。接觸層128與接觸阻障層126可進行化學機械研磨，以去除接觸阻障層126中突出於第二內層介電層122的多餘部份。化學機械研磨亦可使接觸層128的頂表面水平於第二內層介電層122的頂表面。接觸阻障層126有助於預防接觸128的金屬元素擴散至第二內層介電層122。
在又一實施例中，接觸阻障層126可被退火以引發金屬擴散。舉例而言，接觸阻障層126可被退火到250℃至450℃，以引發金屬元素(例如：鋁)擴散至接觸阻障層126。絕緣接觸阻障層126可包含氮化鈦鋁、氮化鈦鋁鎢、氮化鉭鋁或氮化鉭鋁鎢等。
接觸128具有兩個寬度，第一寬度W1(位於第二內層介電層122)與第二寬度W2(位於閘極電極116)。在一實施例中，第二寬度W2的寬度較寬於第一寬度W1的寬度，以增加接觸層128與閘極電極116的訊號金屬之間的接觸面積。增加的接觸面積降低接觸層128與閘極電極116之間的接觸阻抗。第一寬度W1的寬度可因不同技術節點的設計法則，而受限於特定的尺寸；然而，第二寬度W2的寬度則不受此限。在一實施例中，第二寬度W2與鰭部之第三寬度的比值係介於1.2至2.5之間為較佳。相對地，典型的閘極接觸寬度(例如：第一寬度W1)與第三寬度的比值係小於1.2(例如：1)。因此，根據上述之實施例，接觸層128與閘極電極116之間的接觸面積增加，以減少接觸阻抗，且不需違反不同技術節點的設計法則限制。雖然鰭型場效電晶體100被描繪為單一鰭部的鰭型場效電晶體(例如：閘極被形成於單一個鰭部上)，在其他實施例中，亦可應用於多個鰭部的鰭型場效電晶體。
依據一實施例，積體電路結構包含基材。基材之一部分向上延伸以形成鰭部。積體電路結構更包含在鰭部之頂表面與複數個側壁之至少複數個部分上的閘極介電層、 在閘極介電層上的閘極電極、在閘極電極上並延伸至閘極電極中的接觸。接觸在閘極電極上具有第一寬度，接觸在閘極電極中具有第二寬度，且第一寬度小於第二寬度。
依據又一實施例，積體電路結構，包含基材以及在基材上並連接至基材的半導體鰭部。積體電路結構更包含在鰭部之頂表面以及複數個側壁上的閘極介電層、閘極介電層上的閘極電極、在閘極介電層上的內層介電層、自內層介電層之頂表面延伸至閘極電極的接觸、覆蓋接觸之底表面與複數個側壁的接觸阻障層。
接觸在內層介電層具有第一部份，接觸在閘極電極具有第二部份，且其中第一部份與第二部份分別具有第一寬度與第二寬度，而第二寬度係大於第一寬度。
依據另一實施例，一種形成積體電路結構的方法，包含蝕刻基材以形成鰭部，形成閘極介電層在鰭部之頂表面與複數個側壁之至少一部分上，形成閘極電極在閘極介電層上，形成內層介電層在閘極電極上，圖案化內層介電層，以於內層介電層中形成開口且暴露出閘極電極，其中開口具有第一寬度，以及對閘極電極之一部分進行等向性蝕刻步驟，使開口延伸至閘極電極，其中開口在閘極電極中之一部分具有第二寬度，且其中第二寬度係大於第一寬度。上述之方法更包含在開口之底表面與複數個側壁形成接觸阻障層，並將金屬材料填入開口，以形成接觸。
雖然本發明實施例以及其優點已經被詳細揭露，應被理解的是，在不脫離後附之申請專利範圍所界定之精神 和範圍內，可做出各種改變、替換和變化。
此外，本發明之範圍不限於說明書所述之特定製程、儀器、設備、組成物、手段、方法或步驟。本技術領域的通常知識者由本揭露內容、製程、儀器、設備、組成物、手段、方法或步驟，現存或將開發的技術，可以輕易理解後，利用根據本揭露內容執行與本發明之實施例實質相同的功能、或實現實質相同的結果。
100‧‧‧積體電路結構
102‧‧‧基材
112‧‧‧介電層
114‧‧‧閘極介電層
116‧‧‧閘極電極
118‧‧‧閘極間隙壁
120‧‧‧第一內層介電層
122‧‧‧第二內層介電層
126‧‧‧接觸阻障層
128‧‧‧接觸
W1‧‧‧第一寬度
W2‧‧‧第二寬度
W3‧‧‧第三寬度

Claims (10)

  1. 一種積體電路結構，包含：一基材，其中該基材之一部分向上延伸以形成一鰭部；一閘極介電層在該鰭部之一頂表面與複數個側壁之至少複數個部分上；一閘極電極在該閘極介電層上；以及一接觸在該閘極電極上並延伸至該閘極電極中，其中該接觸在該閘極電極上具有一第一寬度，該接觸在該閘極電極中具有一第二寬度，且該第一寬度小於該第二寬度，其中該閘極電極的一頂表面高於該接觸的一底表面。
  2. 如請求項1所述之積體電路結構，其中該第二寬度與該鰭部之一第三寬度之一比值係介於1.2至2.5之間。
  3. 如請求項1所述之積體電路結構，更包含一接觸阻障層於該接觸與該閘極電極之間，其中該接觸阻障層更覆蓋該接觸之複數個側壁上，且該接觸阻障層包含氮化鈦、氮化鉭、氮化鈦鋁、氮化鈦鋁鎢、氮化鉭鋁或氮化鉭鋁鎢。
  4. 一種積體電路結構，包含：一基材；一半導體鰭部在該基材上並連接至該基材；一閘極介電層在該鰭部之一頂表面以及複數個側壁上； 一閘極電極在該閘極介電層上；一內層介電(inter-later dielectric；ILD)層在該閘極介電層上；一接觸自該內層介電層之一頂表面延伸至該閘極電極，其中該接觸在該內層介電層具有一第一部份，該接觸在該閘極電極具有一第二部份，且其中該第一部份與該第二部份分別具有一第一寬度與一第二寬度，而該第二寬度係大於該第一寬度，其中該閘極電極的一頂表面高於該接觸的一底表面；以及一接觸阻障層覆蓋該接觸之一底表面與複數個側壁。
  5. 如請求項4所述之積體電路結構，其中該第二寬度與該鰭部之一第三寬度之一比值係介於1.2至2.5之間。
  6. 如請求項4所述之積體電路結構，其中該接觸阻障層包含氮化鈦、氮化鉭、氮化鈦鋁、氮化鈦鋁鎢、氮化鉭鋁或氮化鉭鋁鎢，且該閘極電極包含一信號金屬與一功函數金屬。
  7. 如請求項4所述之積體電路結構，更包含一界面層與一介電層於該閘極介電層與該鰭部之間，其中該介電層包含一第一部分與一第二部分，且該第一部分與該第二部分係設於該鰭部之複數個相對側邊。
  8. 一種形成積體電路結構的方法，包含：蝕刻一基材以形成一鰭部；形成一閘極介電層在該鰭部之一頂表面與複數個側壁之至少一部分上；形成一閘極電極在該閘極介電層上；形成一內層介電層在該閘極電極上；圖案化該內層介電層，以於該內層介電層中形成一開口且曝露出該閘極電極，其中該開口具有一第一寬度；對該閘極電極之一部分進行一等向性蝕刻步驟，使該開口延伸至該閘極電極，其中該開口在該閘極電極中之一部分具有一第二寬度，且其中該第二寬度係大於該第一寬度；形成一接觸阻障層覆蓋該開口之一底表面與複數個側壁；以及將一金屬材料填入該開口，以形成一接觸。
  9. 如請求項8所述之形成積體電路結構的方法，更包含對該積體電路結構形成一界面層於該鰭部與該閘極電極之間與進行一退火步驟，其中該退火步驟係於250℃至450℃進行。
  10. 如請求項8所述之形成積體電路結構的方法，在形成該閘極介電層之前，更包含：形成一介電層在該基材上；以及 使該介電層內縮，以暴露出該鰭部之至少一部分。
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KR20140110682A (ko) 2014-09-17
US20160300720A1 (en) 2016-10-13
US9385069B2 (en) 2016-07-05
TW201435997A (zh) 2014-09-16
US20140252496A1 (en) 2014-09-11

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