JP2007123825A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP2007123825A JP2007123825A JP2006176863A JP2006176863A JP2007123825A JP 2007123825 A JP2007123825 A JP 2007123825A JP 2006176863 A JP2006176863 A JP 2006176863A JP 2006176863 A JP2006176863 A JP 2006176863A JP 2007123825 A JP2007123825 A JP 2007123825A
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- gas
- nitride film
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- semiconductor substrate
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- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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Abstract
【解決手段】半導体基板の表面を窒化する第1窒化ガスと、製造中に前記半導体基板と実質的に反応しない第1希釈ガスとを含み、前記第1希釈ガスの分圧と前記第1窒化ガスの分圧の和と、前記第1窒化ガスの分圧との比が5以上でかつ全圧が40Torr以下である雰囲気中に前記半導体基板を置き、前記半導体基板の表面に窒化膜を形成する工程を備えている。
【選択図】図1
Description
を備えたことを特徴とする。
本発明の第1実施形態による半導体装置の製造方法を、図1および図2を参照して説明する。図1は、本実施形態による半導体装置の製造方法の製造工程を示すフローチャートであり、図2は本実施形態の製造方法によって製造された半導体装置の断面図である。
(1)シリコン基板表面に到達した希釈ガスは、シリコン表面を泳動しているシリコン原子と衝突し、シリコン原子の運動エネルギーを奪う。
(2)これにより、シリコン基板表面の原子の動きが準静的になる。
(3)窒素原子は基板表面のシリコンの第2原子層が一番安定な吸着サイトであるから(例えば、K. Kato, Y. Nakasaki, D. Matsushita, and K. Muraoka, Proc. 27th ICPS, 2004、参照)、第2原子層に集中的に吸着しつつ、ストレスによりシリコン原子が吐き出される。吐き出されたシリコン原子は表面を泳動するが、N2により動きを奪われるためシリコン基板表面およびシリコン基板中まで拡散することは少なく、降ってきた窒化ガスNH3と反応し、格子間シリコンの発生が抑えられる。
次に、本発明の第2実施形態による半導体装置の製造方法を、図10を参照して説明する。図10は、本実施形態の製造方法の製造工程を示すフローチャートである。本実施形態の半導体装置の製造方法は、第1実施形態の製造方法において、希釈ガスとしてN2ガスのほかに更にHeガスを用いた製造方法である。
次に、本発明の第3実施形態による半導体装置の製造方法を、図15および図16を参照して説明する。図15は本実施形態による半導体装置の製造方法の製造工程を示すフローチャート、図16は本実施形態の製造方法の製造工程を示す断面図である。本実施形態による半導体装置の製造方法は、窒化ガスに希釈ガスを混ぜることによって、シリコン基板上に窒化膜を形成した後、酸化処理を行い、少なくとも、シリコン窒化膜とシリコン基板との界面に酸素が含まれたシリコン酸窒化層を形成するものである。
次に、本発明の第4実施形態による半導体装置の製造方法を、図24乃至図25(c)を参照して説明する。
次に、本発明の第5実施形態による半導体装置の製造方法を、図30乃至図31(d)を参照して説明する。この第5実施形態による製造方法は、窒化膜を酸化する際に、フラットバンド電圧のシフト量ΔVfbを最大限改善したSiON膜を形成することを目的とした半導体装置の製造方法であって、製造工程を図30乃至図31(g)に示す。
次に、本発明の第6実施形態による半導体装置の製造方法を説明する。本実施形態の製造方法によって製造される半導体装置は、FG(フローティングゲート)型の不揮発性メモリあって、複数のメモリセルを備えている。本実施形態のメモリの製造方法について図34(a)乃至図38(b)を参照して説明する。図34(a)乃至図38(b)においては、各図の(a)と、図の(b)は互いに直行する断面を示している。
次に、本発明の第7実施形態による半導体装置の製造方法を説明する。本実施形態の製造方法によって製造される半導体装置は、MONOS(Metal(金属)-Oxide(SiO2)-Nitride(Si3N4)-Oxide(SiO2)-Siの積層構造)型の不揮発性メモリであって、複数のメモリセルを備えている。本実施形態のメモリの製造方法について図44(a)乃至図48(b)を参照して説明する。図44(a)乃至図48(b)においては、各図の(a)と、図の(b)は互いに直行する断面を示している。
次に、本発明の第8実施形態による半導体装置の製造方法を説明する。本実施形態の製造方法は、MISFETの製造方法であって、その製造工程を図50(a)乃至図52(b)に示す。
次に、本発明の第9実施形態による半導体装置の製造方法を、図54乃至図55(b)を参照して説明する。
次に、本発明の第10実施形態による半導体装置の製造方法を、図58を参照して説明する。この第10実施形態による半導体装置の製造方法は、図54に示す第9実施形態の製造方法において、ステップS58の後、すなわち、窒化膜84aを酸化して窒化膜84aを挟むように酸窒化層84b、84cを形成した後、熱処理を行う工程(図58のステップS59)を付加したものとなっている。この熱処理の条件は、本実施形態においては、チャンバー内の雰囲気を、例えば分圧50TorrのN2とし、シリコン基板82の表面を950℃に設定して300秒間維持する(図58)。これにより、シリコン酸窒化膜84中のダングリングボンドがお互い再結合し、安定なSi−O−N結合が形成されることにより、シリコン酸窒化膜中の欠陥が減少する。
次に、本発明の第11実施形態による半導体装置の製造方法を、図60を参照して説明する。この第11実施形態による半導体装置の製造方法は、図58に示す第10実施形態の製造方法において、酸化処理後の熱処理のステップS59に用いるガスを分圧50TorrのN2ガスから分圧50TorrのHeガスに換えた工程(図60のステップ59A)となっている。本実施形態の製造方法も、上記酸化処理後の熱処理により、シリコン酸窒化膜中のダングリングボンドがお互い再結合し、安定なSi−O−N結合を形成することが可能となり、シリコン酸窒化膜中の欠陥が減少する。
次に、本発明の第12実施形態による半導体装置の製造方法を、図63乃至図64(c)を参照して説明する。
4 シリコン窒化膜
6 シリコン酸窒化層
8 シリコン酸窒化層
Claims (23)
- 半導体基板の表面を窒化する第1窒化ガスと、製造中に前記半導体基板と実質的に反応しない第1希釈ガスとを含み、前記第1希釈ガスの分圧と前記第1窒化ガスの分圧の和と、前記第1窒化ガスの分圧との比が5以上でかつ全圧が40Torr以下である雰囲気中に前記半導体基板を置き、前記半導体基板の表面に窒化膜を形成する工程を備えたことを特徴とする半導体装置の製造方法。
- 前記第1窒化ガスは、NH3、N*、N2 *のいずれかであることを特徴とする請求項1記載の半導体装置の製造方法。
- 前記雰囲気の全圧は30Torr以下であることを特徴とする請求項1または2記載の半導体装置の製造方法。
- 前記第1希釈ガスは、N2ガスを含むことを特徴とする請求項1乃至3のいずれかに記載の半導体装置の製造方法。
- 前記第1希釈ガスは、前記半導体基板と前記窒化膜との界面の原子振動エネルギーに近い固有振動エネルギーを有する成分を含むことを特徴とする請求項1乃至4のいずれかに記載の半導体装置の製造方法。
- 前記半導体基板の表面に前記窒化膜を形成した後、前記半導体基板を、前記半導体基板と実質的に反応しないガスの雰囲気中に置き、熱処理する工程を更に備えたことを特徴とする請求項1乃至5のいずれかに記載の半導体装置の製造方法。
- 前記半導体基板と実質的に反応しないガスはN2ガスまたはHeガスのいずれかであることを特徴とする請求項6記載の半導体装置の製造方法。
- 前記窒化膜を形成する雰囲気は、前記第1希釈ガスの分圧と前記第1窒化ガスの分圧の和と、前記第1窒化ガスの分圧との比が10000以下でかつ全圧が3Torr以上であることを特徴とする請求項1乃至7のいずれかに記載の半導体装置の製造方法。
- 前記窒化膜は500℃以上850℃以下の温度で形成することを特徴とする請求項1乃至8のいずれかに記載の半導体装置の製造方法。
- 半導体基板の表面を窒化する第1窒化ガスと、製造中に前記半導体基板と実質的に反応しない第1希釈ガスとを含み、前記第1希釈ガスの分圧と前記第1窒化ガスの分圧の和と、前記第1窒化ガスの分圧との比が5以上でかつ全圧が40Torr以下である雰囲気中に前記半導体基板を置き、前記半導体基板の表面に窒化膜を形成する工程と、
ラジカルな第2窒化ガスの雰囲気中に、表面に前記窒化膜が形成された前記半導体基板を置き、前記半導体基板と前記窒化膜との間に第1窒化層を形成するとともに前記窒化膜上に第2窒化層を形成する工程と、
を備えたことを特徴とする半導体装置の製造方法。 - 前記窒化膜の膜厚は、4Å以上1nm以下であることを特徴とする請求項10記載の半導体装置の製造方法。
- 前記第2窒化ガスは、N*またはN2 *のいずれかであることを特徴とする請求項10記載の半導体装置の製造方法。
- 半導体基板の表面を窒化する第1窒化ガスと、製造中に前記半導体基板と実質的に反応しない第1希釈ガスとを含み、前記第1希釈ガスの分圧と前記第1窒化ガスの分圧の和と、前記第1窒化ガスの分圧との比が5以上でかつ全圧が40Torr以下である雰囲気中に前記半導体基板を置き、前記半導体基板の表面に窒化膜を形成する工程と、
表面に前記窒化膜が形成された前記半導体基板を、酸化ガスと、製造中に前記半導体基板と実質的に反応しない第2希釈ガスとを含む雰囲気中に置き、前記半導体基板と前記窒化膜との間に第1酸窒化層を形成するとともに前記窒化膜の表面に第2酸窒化層を形成する工程と、
を備えたことを特徴とする半導体装置の製造方法。 - 前記酸化ガスは、O2、N2O、NO、O*のいずれかであることを特徴とする請求項13記載の半導体装置の製造方法。
- 前記第2希釈ガスはN2ガスであることを特徴とする請求項13または14に記載の半導体装置。
- 前記窒化膜を形成する工程と前記第1酸窒化層を形成する工程との間に、表面に前記窒化膜が形成された前記半導体基板を、前記半導体基板と実質的に反応しないガスの雰囲気中に置き、第1熱処理する工程を更に備えたことを特徴とする請求項13乃至15のいずれかに記載の半導体装置の製造方法。
- 前記第1および第2酸窒化層を形成する工程は、800℃以上950℃以下であることを特徴とする請求項13乃至16のいずれかに記載の半導体装置の製造方法。
- 前記第1および第2酸窒化層を形成した後、前記半導体基板を、前記半導体基板と実質的に反応しないガスの雰囲気中に置き、第2熱処理する工程を更に備えたことを特徴とする請求項13乃至17のいずれかに記載の半導体装置の製造方法。
- 前記半導体基板と実質的に反応しないガスはN2ガスまたはHeガスのいずれかであることを特徴とする請求項18記載の半導体装置の製造方法。
- 前記第1および第2酸窒化層を形成した後、前記第2熱処理をする前に、前記第2酸窒化層に窒素を導入する工程を更に備えたことを特徴とする請求項18または19のいずれかに記載の半導体装置の製造方法。
- 前記窒化膜は、フローティングゲート型不揮発性メモリのトンネル絶縁膜であることを特徴とする請求項1乃至20のいずれかに記載の半導体装置の製造方法。
- 前記窒化膜は、MONOS型不揮発性メモリのトンネル絶縁膜であることを特徴とする請求項1乃至20のいずれかに記載の半導体装置の製造方法。
- 前記窒化膜は、MISFETのゲート絶縁膜であることを特徴とする請求項1乃至20のいずれかに記載の半導体装置の製造方法。
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US9136114B2 (en) | 2010-11-04 | 2015-09-15 | Hitachi Kokusai Electric Inc. | Method of manufacturing semiconductor device, substrate processing method, computer-readable medium with program for executing a substrate processing method, and substrate processing apparatus |
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Also Published As
Publication number | Publication date |
---|---|
EP1929513A1 (en) | 2008-06-11 |
KR100880309B1 (ko) | 2009-01-28 |
US20110003481A1 (en) | 2011-01-06 |
WO2007037094A1 (en) | 2007-04-05 |
KR20070097543A (ko) | 2007-10-04 |
JP5283833B2 (ja) | 2013-09-04 |
US20080305647A1 (en) | 2008-12-11 |
US8557717B2 (en) | 2013-10-15 |
US7772129B2 (en) | 2010-08-10 |
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